AD9253-DSCC: Military Data Sheet

REVISIONS
LTR
DESCRIPTION
DATE
Prepared in accordance with ASME Y14.24
APPROVED
Vendor item drawing
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PMIC N/A
PREPARED BY
Phu H. Nguyen
Original date of drawing
YY MM DD
CHECKED BY
13-09-19
4
Phu H. Nguyen
APPROVED BY
Thomas M. Hess
SIZE
A
REV
AMSC N/A
CODE IDENT. NO.
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DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil/
TITLE
MICROCIRCUIT, DIGITAL-LINEAR, QUAD, 14BIT, 125 MSPS SERIAL LVDS 1.8 V ANALOG-TODIGITAL CONVERTER, MONOLITHIC SILICON
DWG NO.
V62/13627
16236
PAGE
1
OF
14
5962-V085-13
1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance quad, 14-bit, 125 MSPS serial LVDS 1.8 V
analog-to-digital converter microcircuit, with an operating temperature range of -55°C to +125°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/13627
-
Drawing
number
01
X
E
Device type
(See 1.2.1)
Case outline
(See 1.2.2)
Lead finish
(See 1.2.3)
1.2.1 Device type(s).
Device type
Generic
01
AD9253-EP
Circuit function
Quad, 14-bit, 125 MSPS serial LVDS 1.8 V
analog-to-digital converter
1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter
Number of pins
X
48
JEDEC PUB 95
Package style
JEDEC MO-220-WKKD
Lead Lead Frame Chip Scale Package
1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
A
B
C
D
E
Z
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Material
Hot solder dip
Tin-lead plate
Gold plate
Palladium
Gold flash palladium
Other
SIZE
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CODE IDENT NO.
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1.3 Absolute maximum ratings.
1/
AVDD to AGND ......................................................................................................
DRVDD to AGND ...................................................................................................
Digital outputs (D0±x, D1±x, DCO+, DCO-, FCO+, FCO-) to AGND ......................
CLK+, CLK- to AGND .............................................................................................
VIN+x, VIN-x to AGND ...........................................................................................
SCLK/DTP, SDIO/OLM, CSB to AGND .................................................................
SYNC, PDWN to AGND .........................................................................................
RBIAS to AGND .....................................................................................................
VREF, SENSE to AGND ........................................................................................
Operating temperature range (Ambient) ................................................................
Maximum junction temperature ..............................................................................
Lead temperature (Soldering, 10 sec) ....................................................................
Storage temperature range (Ambient) ....................................................................
-0.3 V to +2.0 V
-0.3 V to +2.0 V
-0.3 V to +2.0 V
-0.3 V to +2.0 V
-0.3 V to +2.0 V
-0.3 V to +2.0 V
-0.3 V to +2.0 V
-0.3 V to +2.0 V
-0.3 V to +2.0 V
-55°C to +125°C
150°C
300°C
-65°C to 150°C
1.5 Thermal characteristics.
Thermal resistance
Case outline
Case X
Air flow
velocity
(m/sec)
0.0
1.0
2.5
θJA
2/
20.3
17.6
16.5
ψJT
0.10
0.16
0.20
ψJB
5.9
N/A 3/
N/A 3/
θJC
θJC
TOP
BOTTOM
6.1
N/A 3/
N/A 3/
1.0
N/A 3/
N/A 3/
Unit
°C/W
°C/W
°C/W
2. APPLICABLE DOCUMENTS
JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)
JEP95
–
Registered and Standard Outlines for Semiconductor Devices
(Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association, 3103
North 10th Street, Suite 240–S, Arlington, VA 22201-2107).
1/
2/
3/
Stresses above those listed under “Absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions above those beyond indicated in the operational
section of this specifications is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
θJA for a 4-layer printed circuit board (PCB) with solid ground plane (simulated). Exposed pad soldered to PCB.
N/A = not applicable.
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3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.
Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)
3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as
specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1
Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2
Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3
Terminal function description. The Terminal function description shall be as shown in figure 3.
3.5.4
Functional block diagram. The functional block diagram shall be as shown in figure 4.
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TABLE I. Electrical performance characteristics. 1/
Test 2/
Test conditions
3/
Temp
Limits
Min
Unit
Typ
Max
DC SPECIFICATIONS
Resolution
Accuracy
No missing codes
Offset error
Offset matching
Gain error
Gain matching
14
Full
Full
Full
Full
Full
Full
25°C
Full
25°C
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Temperature drift
Offset error
Gain error
Internal voltage reference
Output voltage (1 V Mode)
Load regulation at 1.0 mA (VREF = 1 V)
Input resistance
Input referred noise
VREF = 1.0 V
Analog inputs
Differential input voltage (VREF = 1 V)
Common mode voltage
Differential input resistance
Differential input capacitance
Power supply
AVDD
DRVDD
IAVDD 4/
IDRVDD(ANSI-644 mode) 4/
IDRVDD(Reduce range mode) 4/
Total power consumption
DC input
Sine wave input (Four channels including output drivers
ANSI 644 mode)
Sine wave input (Four channels including output drivers
reduced range mode)
Power down mode
Standby mode 5/
-0.8
-0.6
-12
Guaranteed
-0.3
+0.2
-3
1.1
+0.1
+0.6
+2
1.6
+1.9
% FSR
% FSR
% FSR
% FSR
LSB
LSB
+4.5
±2.0
LSB
LSB
±2
±50
ppm/°C
ppm/°C
-0.8
±0.8
-4.5
Full
Full
Full
Full
Full
Bits
0.98
1.0
2
7.5
1.02
V
mV
kΩ
25°C
0.94
LSB rms
Full
Full
2
0.9
5.2
3.5
V p-p
V
kΩ
pF
Full
Full
Full
Full
Full
1.7
1.7
25°C
1.8
1.8
183
61
53
1.9
1.9
205
63
Full
Full
403
440
25°C
425
mW
Full
Full
2
235
mW
mW
480
V
V
mA
mA
mA
mW
mW
See footnote at end of table.
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TABLE I. Electrical performance characteristics - Continued. 1/
Test 2/
Test conditions
3/
Temp
Limits
Unit
Min
Typ
Max
dBFS
72
75.3
75.2
74.1
72.2
70.7
dBFS
71.7
75.2
75.1
74.0
71.9
70.4
25°C
25°C
Full
25°C
25°C
12.2
12.2
12.0
11.7
11.4
Bits
25°C
25°C
Full
25°C
25°C
98
92
90
85
83
dBc
25°C
25°C
Full
25°C
25°C
-98
-92
-90
-85
-83
dBc
25°C
25°C
Full
25°C
25°C
-101
-100
-95
-96
-92
25°C
Full
25°C
86
-95
-89
dBc
dB
dB
25°C
25°C
25°C
48
75
650
dB
dB
MHz
AC SPECIFICATIONS
Signal to Noise Ratio (SNR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
Signal to Noise And Distortion ratio (SINAD)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
Effective Number Of Bits (ENOB)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
Spurious Free Dynamic Range (SFDR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
Worst Harmonic (Second or Third)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
Worst other Harmonic (Excluding Second or Third)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
Two tone Intermodulation Distortion (IMD) –AN1 and AND2 = -7.0 dBFS
fIN1 = 70.5 MHz, fIN2 = 72.5 MHz
Crosstalk
6/
Crosstalk (Overrange condition)
7/
Power Supply Rejection Ratio (SPRR) 8/
AVDD
DRVDD
Analog input bandwidth, Full power
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
76
-76
dBFS
-83
See footnote at end of table.
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TABLE I. Electrical performance characteristics - Continued. 1/
Test 2/
Test conditions
3/
Temp
Limits
Min
Unit
Typ
Max
DIGITAL SPECIFICATIONS
Clock inputs (CLK+, CLK-)
Logic compliance
Differential input voltage 9/
Input voltage range
Input common mode voltage
Input resistance (Differential)
25°C
CMOS/LVDS/LVPECL
0.2
3.6
AGND – 0.2
AGND + 0.2
0.9
15
Input capacitance
Logic inputs (PDWN, SYNC, SCLK)
Logic 1 voltage
Logic 0 voltage
Input resistance
Input capacitance
Logic input (CSB)
Logic 1 voltage
Logic 0 voltage
Input resistance
25°C
4
25°C
Input capacitance
Logic input (SDIO/OLM)
Logic 1 voltage
Logic 0 voltage
Input resistance
25°C
25°C
26
V
V
kΩ
Input capacitance
Logic output (SDIO/OLM) 10/
Logic 1 voltage (IOH = 800 µA)
Logic 0 voltage (IOL = 50 µA)
Digital outputs (D0±x, D1±x), ANSI-644
Logic compliance
Differential output voltage (VOD)
Output offset voltage (VOS)
Output coding (Default)
Digital outputs (D0±x, D1±x), low power, reduced signal option
Logic compliance
Differential output voltage (VOD)
Output offset voltage (VOS)
Output coding (Default)
25°C
5
pF
Full
Full
1.79
Full
Full
Full
Full
Full
1.2
0
Full
Full
Full
Full
pF
AVDD + 0.2
0.8
V
V
kΩ
pF
AVDD + 0.2
0.8
26
V
V
kΩ
2
pF
30
2
25°C
25°C
V p-p
V
V
kΩ
1.2
0
1.2
0
AVDD + 0.2
0.8
V
V
0.05
Full
Full
290
1.15
LVDS
345
400
1.25
1.35
Twos complement
mV
V
Full
Full
LVDS
160
200
230
1.15
1.25
1.35
Twos complement
mV
V
See footnote at end of table.
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7
TABLE I. Electrical performance characteristics - Continued. 1/
Test 2/
11/
Clock
Input clock rate
Conversion rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
Output parameters 12/
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO Propagation Delay (tFCO)
DCO Propagation Delay (tCPD)
Test conditions
3/
Temp
Limits
Min
SWITCHING SPECIFICATIONS
Typ
Full
Full
Full
Full
Unit
Max
10
10
1000
125
MHz
MSPS
ns
ns
4.00
4.00
DCO-to-Data Delay (tDATA)
13/
DCO-to-FCO Delay (tFRAME) 13/
Lane Delay (tLD)
Data to Data Skew (tDATA-MAX − tDATA-MIN)
Wake-Up Time (Standby)
25°C
2.3
300
300
2.3
tFCO +
(tSAMPLE/16)
(tSAMPLE/16)
(tSAMPLE/16)
90
±50
250
Wake-Up Time (Power-Down)
Pipeline Latency
25°C
Full
375
16
µs
Clock
cycles
Aperture
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
25°C
25°C
1
135
ns
fs ms
Out-of-Range Recovery Time
25°C
1
Clock
cycles
13/
14/
Full
Full
Full
Full
Full
Full
Full
1.5
(tSAMPLE/16) - 300
(tSAMPLE/16) - 300
Full
ns
ps
ps
ns
ns
3.1
(tSAMPLE/16) + 300
(tSAMPLE/16) + 300
±200
ops
ps
ps
ps
ns
See footnote at end of table.
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TABLE I. Electrical performance characteristics - Continued. 1/
1/
2/
3/
4/
5/
6/
7/
8/
9/
10/
11/
12/
13/
14/
Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not
necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or
design.
See the AN-835 manufacturer’s application note. Understanding high speed ADC testing and evaluation, for definitions and for
details on how these tests were completed.
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -1.0 dBFS, unless otherwise noted.
Measured with a low input frequency, full scale sine wave of all four channels.
It can be controlled via the SPI.
Crosstalk is measured at 70 MHz with an −1.0 dBFS analog input on one channel and no input on the adjacent channel.
The over range condition is specified with 3 dB of the full-scale input range.
PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT.
PSRR is calculated as the ratio of the amplitudes of the spur voltage over the pin voltage, expressed in decibels.
This is specified for LVDS and LVPECL only.
This is specified for 13 SDIO/OLM pins sharing the same connection.
Measured on standard FR-4 material.
Can be adjusted via the SPI. The conversion rate is the clock rate after the divider.
tSAMPLE/16 is based on the number of bits in two LVDS data lanes. tSAMPLE = 1/fS.
Wake-up time is defined as the time required to return to normal operation from power-down mode.
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Case X
D/E
48
1
PIN 1 AREA
TOP VIEW
A2
A
SEATING
PLANE
0.08
A1
PIN 1
INDICATOR
1
S
12
13
48
EXPOSED PAD
D1/E1
37
36
b
48 PLS
Symbol
A
A1
A2
b
D/E
25
S1
e
BOTTOM VIEW
Dimensions
Millimeters
Symbol
Min
Max
0.70
24
0.80
0.05
0.20 REF
0.18
0.30
6.90
7.10
D1/E1
e
S
S1
Millimeters
Min
Max
5.55
5.65
0.50 BSC
0.35
0.45
0.20
NOTES:
1. All linear dimensions are in millimeters.
2. Falls within JEDEC STANDARDS MO-220-WKKD.
FIGURE 1. Case outline.
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Case outline X
Terminal
number
Terminal symbol
Terminal
number
Terminal symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VIN+D
VIN-D
AVDD
AVDD
CLKCLK+
AVDD
DRVDD
D1-D
D1+D
D0-D
D0+D
D1-C
D1+C
D0-C
D0+C
DCODCO+
FCOFCO+
D1-B
D1+B
D0-B
D0+B
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VIN+C
VIN-C
AVDD
AVDD
SYNC
VCM
VREF
SENSE
RBIAS
AVDD
VIN-B
VIN+B
VIN+A
VIN-A
AVDD
PDWN
CSB
SDIO/OLM
SCLK/DTP
DRVDD
D0+A
D0-A
D1+A
D1-A
NOTE:
1. The exposed thermal PAD on the bottom of the package provides
the analog ground for the part, this exposed PAD must be
connected to ground for proper operation.
FIGURE 2. Terminal connections
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Case outline X
Pin No.
0
1
2
3, 4, 7, 34,
39, 45, 46
5, 6
8, 29
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
30
31
32
Mnemonic
AGND,
Exposed Pad
VIN+D
VIN−D
AVDD
CLK−, CLK+
DRVDD
D1−D
D1+D
D0−D
D0+D
D1−C
D1+C
D0−C
D0+C
DCO−
DCO+
FCO−
FCO+
D1−B
D1+B
D0−B
D0+B
D1−A
D1+A
D0−A
D0+A
SCLK/DTP
SDIO/OLM
CSB
33
PDWN
35
36
37
38
40
41
42
43
44
47
48
VIN−A
VIN+A
VIN+B
VIN−B
RBIAS
SENSE
VREF
VCM
SYNC
VIN−C
VIN+C
Description
Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides the
analog ground for the part. This exposed pad must be connected to ground for proper operation.
ADC D Analog Input True.
ADC D Analog Input Complement.
1.8 V Analog Supply Pins.
Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.
Digital Output Driver Supply.
Channel D Digital Output 1 Complement.
Channel D Digital Output 1 True.
Channel D Digital Output 0 Complement.
Channel D Digital Output 0 True.
Channel C Digital Output 1 Complement.
Channel C Digital Output 1 True.
Channel C Digital Output 0 Complement.
Channel C Digital Output 0 True.
Data Clock Output Complement.
Data Clock Output True.
Frame Clock Output Complement.
Frame Clock Output True.
Channel B Digital Output 1 Complement.
Channel B Digital Output 1 True.
Channel B Digital Output 0 Complement.
Channel B Digital Output 0 True.
Channel A Digital Output 1 Complement.
Channel A Digital Output 1 True.
Channel A Digital Output 0 Complement.
Channel A Digital Output 0 True.
SPI Clock Input/Digital Test Pattern.
SPI Data Input and Output Bidirectional SPI Data/Output Lane Mode.
SPI Chip Select Bar. Active low enable; 30 kΩ internal pull-up.
Digital Input, 30 kΩ Internal Pull-Down.
PDWN high = power-down device.
PDWN low = run device, normal operation.
ADC A Analog Input Complement.
ADC A Analog Input True.
ADC B Analog Input True.
ADC B Analog Input Complement.
Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
Reference Mode Selection.
Voltage Reference Input and Output.
Analog Input Common-Mode Voltage.
Digital Input. SYNC input to clock divider.
ADC C Analog Input Complement.
ADC C Analog Input True.
FIGURE 3. Terminal function description.
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AVDD
VIN+A
PDWN
PIPELINE
ADC
VIN-A
VIN+B
PIPELINE
ADC
VIN-B
14
14
DRVDD
DIGITAL
SERIALIZER
DIGITAL
SERIALIZER
RBIAS
VREF
SENSE
+
-
REF
SELECT
PIPELINE
ADC
VIN-C
VIN+D
PIPELINE
ADC
14
DIGITAL
SERIALIZER
SERIAL
LVDS
D0+B
SERIAL
LVDS
D1+B
D1-A
D0-B
D1-B
SERIAL
LVDS
D0+C
SERIAL
LVDS
D1+C
SERIAL
LVDS
D0+D
SERIAL
LVDS
D1+D
D0-C
D1-C
D0-D
D1-D
DCO+
DCO-
CLK-
CLK+
SYNC
14
DIGITAL
SERIALIZER
CLOCK
MANAGEMENT
SCLK/DTP
D1+A
FCO-
SERIAL PORT
INTERFACE
SDIO/OLM
VCM
SERIAL
LVDS
D0-A
FCO+
CSB
VIN-D
D0+A
1V
AGND
VIN+C
SERIAL
LVDS
FIGURE 4. Functional block diagram.
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4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,
classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of
present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current
sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Vendor item drawing
administrative control
number 1/
Device
manufacturer
CAGE code
V62/13627-01XE
24355
Transport media
Vendor part number
Tray, 260
AD9253TCPZ-125EP
Tape and reel
AD9253TCPZR7-125EP
1/ The vendor item drawing establishes an administrative control number for
identifying the item on the engineering documentation.
CAGE code
24355
DLA LAND AND MARITIME
COLUMBUS, OHIO
Source of supply
Analog Devices
1 Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/13627
PAGE
14
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