ADSP-BF561 EZ-KIT Lite Evaluation System Manual (Rev. 3.3)

ADSP-BF561 EZ-KIT Lite®
Evaluation System Manual
Revision 3.3, July 2012
Part Number
82-000811-01
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106
a
Copyright Information
© 2012 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.
Printed in the USA.
Disclaimer
Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice
The Analog Devices logo, Blackfin, CrossCore, EngineerZone,
EZ-Extender, EZ-KIT Lite, and VisualDSP++ are registered trademarks of
Analog Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.
Regulatory Compliance
The ADSP-BF561 EZ-KIT Lite is designed to be used solely in a laboratory environment. The board is not intended for use as a consumer end
product or as a portion of a consumer end product. The board is an open
system design which does not include a shielded enclosure and therefore
may cause interference to other electrical devices in close proximity. This
board should not be used in or near any medical equipment or RF devices.
The ADSP-BF561 EZ-KIT Lite has been certified to comply with the
essential requirements of the European EMC directive 89/336/EEC
amended by 93/68/EEC and therefore carries the “CE” mark.
The ADSP-BF561 EZ-KIT Lite has been appended to Analog Devices,
Inc. Technical File (TCF) referenced ‘DSPTOOLS1’ dated
December 21, 1997 and was awarded CE Certification by an appointed
European Competent Body as listed below.
Technical Certificate No: Z600ANA1.016
Issued by: Technology International (Europe) Limited
60 Shrivenham Hundred Business Park
Shrivenham, Swindon, SN6 8TY, UK
The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge)
sensitive devices. Electrostatic charges readily accumulate on the human
body and equipment and can discharge without detection. Permanent
damage may occur on devices subjected to high-energy discharges. Proper
ESD precautions are recommended to avoid performance degradation or
loss of functionality. Store unused EZ-KIT Lite boards in the protective
shipping package.
CONTENTS
PREFACE
Product Overview ........................................................................... xi
Purpose of This Manual ................................................................ xiii
Intended Audience ........................................................................ xiii
Manual Contents ........................................................................... xiv
What’s New in This Manual ........................................................... xiv
Technical Support ........................................................................... xv
Supported Processors ...................................................................... xvi
Product Information ...................................................................... xvi
Analog Devices Web Site .......................................................... xvi
EngineerZone .......................................................................... xvii
Related Documents ...................................................................... xviii
Notation Conventions .................................................................. xviii
USING THE ADSP-BF561 EZ-KIT LITE
Package Contents .......................................................................... 1-2
Default Configuration ................................................................... 1-3
CCES Install and Session Startup .................................................. 1-4
Session Startup ........................................................................ 1-6
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
v
Contents
VisualDSP++ Install and Session Startup ....................................... 1-8
CCES Evaluation License ........................................................... 1-10
VisualDSP++ Evaluation License ................................................. 1-11
Memory Map ............................................................................. 1-11
LEDs and Push Buttons .............................................................. 1-14
Audio Interface ........................................................................... 1-15
Video Interface ........................................................................... 1-16
Board Design Database ............................................................... 1-17
Example Programs ...................................................................... 1-18
Flash Programming Utility .......................................................... 1-18
ADSP-BF561 EZ-KIT LITE HARDWARE REFERENCE
System Architecture ...................................................................... 2-2
External Bus Interface Unit ..................................................... 2-3
SPORT Audio Interface .......................................................... 2-3
SPI Interface ........................................................................... 2-3
Programmable Flags ................................................................ 2-4
PPI Interfaces ......................................................................... 2-5
Video Output (PPI1) .......................................................... 2-7
Video Input (PPI0) ............................................................. 2-7
UART Port ............................................................................. 2-8
Expansion Interface ................................................................. 2-8
JTAG Emulation Port ............................................................. 2-9
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Contents
Jumper and DIP Switch Settings .................................................. 2-10
Video Configuration Switch (SW2) ....................................... 2-10
Boot Mode Switch (SW3) ...................................................... 2-11
Push Button Enable Switch (SW4) ......................................... 2-12
PPI Clock Select Switch (SW5) .............................................. 2-13
Test DIP Switches (SW10 and SW11) .................................... 2-13
Audio Enable Switch (SW12) ................................................ 2-13
SPIS1/SPISS Select (SW13) ................................................... 2-14
Video Encoder Clock Select Jumper (JP1) .............................. 2-14
VDDINT Select Jumpers (JP2 and JP3) ................................. 2-14
UART Loop Jumper (P1) ....................................................... 2-15
LEDs and Push Buttons .............................................................. 2-15
Reset Push Button (SW1) ...................................................... 2-16
Programmable Flag Push Buttons (SW6–9) ............................ 2-16
Power LED (LED1) ............................................................... 2-16
Reset LED (LED2) ................................................................ 2-17
USB Monitor LED (ZLED3) ................................................. 2-17
User LEDs (LED5–12, LED13–20) ....................................... 2-17
Connectors ................................................................................. 2-18
Expansion Interface (J1–3) .................................................... 2-19
Audio (J4 and J5) .................................................................. 2-19
Video (J6) ............................................................................. 2-20
Power (J7) ............................................................................. 2-20
RS-232 (P2) .......................................................................... 2-20
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
vii
Contents
SPORT1 (P3) ....................................................................... 2-21
SPI (P5) ................................................................................ 2-21
USB Debug Agent Connector (ZJ1) ...................................... 2-21
JTAG (ZP4) .......................................................................... 2-22
ADSP-BF561 EZ-KIT LITE BILL OF MATERIALS
ADSP-BF561 EZ-KIT LITE SCHEMATIC
INDEX
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ADSP-BF561 EZ-KIT Lite Evaluation System Manual
PREFACE
Thank you for purchasing the ADSP-BF561 EZ-KIT Lite®, Analog
Devices, Inc. evaluation system for Blackfin® processors.
Blackfin processors embody a type of embedded processor designed specifically to meet the computational demands and power constraints of
today’s embedded audio, video, and communications applications. They
deliver breakthrough signal-processing performance and power efficiency
within a reduced instruction set computing (RISC) programming model.
Blackfin processors support a media instruction set computing (MISC)
architecture. This architecture is the natural merging of RISC, media
functions, and digital signal processing (DSP) characteristics. Blackfin
processors deliver signal-processing performance in a microprocessor-like
environment.
Based on the Micro Signal Architecture (MSA), Blackfin processors combine a 32-bit RISC instruction set, dual 16-bit multiply accumulate
(MAC) DSP functionality, and eight-bit video processing performance
that had previously been the exclusive domain of very-long instruction
word (VLIW) media processors.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
ix
The evaluation board is designed to be used in conjunction with the
CrossCore® Embedded Studio (CCES) and VisualDSP++® development
environments to test the capabilities of the ADSP-BF561 Blackfin processors. The VisualDSP++ development environment gives you the ability to
perform advanced application code development and debug, such as:
• Create, compile, assemble, and link application programs written
in C++, C, and ADSP-BF561 assembly
• Load, run, step, halt, and set breakpoints in application programs
• Read and write data and program memory
• Read and write core and peripheral registers
• Plot memory
Access to the ADSP-BF561 processor from a personal computer (PC) is
achieved through a USB port or an optional JTAG emulator. The USB
interface gives unrestricted access to the ADSP-BF561 processor and the
evaluation board peripherals. Analog Devices JTAG emulators offer faster
communication between the host PC and target hardware. Analog Devices
carries a wide range of in-circuit emulation products. To learn more about
Analog Devices emulators and processor development tools, go to
http://www.analog.com/dsp/tools.
The ADSP-BF561 EZ-KIT Lite provides example programs to demonstrate the capabilities of the evaluation board.
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ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Preface
Product Overview
The board features:
• Analog Devices ADSP-BF561 Blackfin processor
• 256-pin mini-BGA package
• 30 MHz CLKIN oscillator
• Synchronous dynamic random access memory (SDRAM)
• 64 MB (16M x 16 bits x 2 chips)
• Flash memory
• 8 MB (4M x 16 bits)
• Analog audio interface
• AD1836 A – Analog Devices 96 kHz audio codec
• 4 input RCA phono jacks (2 stereo channels)
• 6 output RCA phono jacks (3 stereo channels)
• Analog video interface
• ADV7183A video decoder w/ 3 input RCA phono jacks
• ADV7179 video encoder w/ 3 output RCA phono jacks
• Universal asynchronous receiver/transmitter (UART)
• ADM3202 RS-232 line driver/receiver
• DB9 male connector
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
xi
Product Overview
• LEDs
• 20 LEDs: 1 power (green), 1 board reset (red), 1 USB (red),
16 general-purpose (amber), and 1 USB monitor (amber)
• Push buttons
• 5 push buttons with debounce logic: 1 reset,
4 programmable flags
• Expansion interface
•
PPI0, PPI1, SPI, EBIU, Timers11-0, UART,
programmable flags, SPORT0, SPORT1
• Other features
• JTAG ICE 14-pin header
The EZ-KIT Lite board holds 8 MB of flash memory, which can be used
to store user-specific boot code, allowing the board to run as a stand-alone
unit. The board also holds 512-Mb SDRAM, which can be used at runtime. For more information see “Memory Map” on page 1-11.
interfaces with the AD1836A audio codec, facilitating creation of
audio signal processing applications. SPORT0 also attaches to an off-board
connector to allow communication with other serial devices. For information about SPORT0, see “SPORT Audio Interface” on page 2-3.
SPORT0
The parallel peripheral interfaces (PPIs) of the processor connect to both a
video encoder and video decoder, facilitating creation of video signal processing applications. For information on how the board utilizes the
processor’s PPIs, see “PPI Interfaces” on page 2-5.
The UART of the processor connects to an RS-232 line driver and a DB9
male connector, allowing you to interface with a PC or other serial device.
For information about the UART, see “UART Port” on page 2-8.
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ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Preface
Additionally, the EZ-KIT Lite board provides access to most of the processor’s peripheral ports. Access is provided in the form of a
three-connector expansion interface. For information about the expansion
interface, see “Expansion Interface” on page 2-8.
Purpose of This Manual
The ADSP-BF561 EZ-KIT Lite Evaluation System Manual provides
instructions for installing the product hardware (board). The text
describes operation and configuration of the board components and provides guidelines for running your own code on the ADSP-BF561 EZ-KIT
Lite. Finally, a schematic and a bill of materials are provided as a reference
for future designs.
Intended Audience
The primary audience for this manual is a programmer who is familiar
with Analog Devices processors. This manual assumes that the audience
has a working knowledge of the appropriate processor architecture and
instruction set.
Programmers who are unfamiliar with Analog Devices processors can use
this manual but should supplement it with other texts that describe your
target architecture. For the locations of these documents, see “Related
Documents”.
Programmers who are unfamiliar with CCES or VisualDSP++ should refer
to the online help and user’s manuals.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
xiii
Manual Contents
Manual Contents
The manual consists of:
• Chapter 1, “Using the ADSP-BF561 EZ-KIT Lite” on page 1-1
Describes the EZ-KIT Lite functionality from a programmer’s perspective and provides an easy-to-access memory map
• Chapter 2, “ADSP-BF561 EZ-KIT Lite Hardware Reference” on
page 2-1
Provides information on the EZ-KIT Lite hardware components.
• Appendix A, “ADSP-BF561 EZ-KIT Lite Bill Of Materials” on
page A-1
Provides a list of components used to manufacture the EZ-KIT
Lite board.
• Appendix B, “ADSP-BF561 EZ-KIT Lite Schematic” on page B-1
Provides the resources to allow EZ-KIT Lite board-level debugging
or to use as a reference design. Appendix B is part of the online
help.
What’s New in This Manual
This is revision 3.3 of the ADSP-BF561 EZ-KIT Lite Evaluation System
Manual. The manual has been updated to include CCES information. In
addition, modifications and corrections based on errata reports against the
previous manual revision have been made.
For the latest version of this manual, please refer to the Analog Devices
Web site.
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ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Preface
Technical Support
You can reach Analog Devices processors and DSP technical support in
the following ways:
• Post your questions in the processors and DSP support community
at EngineerZone®:
http://ez.analog.com/community/dsp
• Submit your questions to technical support directly at:
http://www.analog.com/support
• E-mail your questions about processors, DSPs, and tools development software from CrossCore Embedded Studio or
VisualDSP++:
Choose Help > Email Support. This creates an e-mail to
and automatically attaches
your CrossCore Embedded Studio or VisualDSP++ version information and license.dat file.
[email protected]
• E-mail your questions about processors and processor applications
to:
[email protected] or
[email protected] (Greater China support)
• In the USA only, call 1-800-ANALOGD (1-800-262-5643)
• Contact your Analog Devices sales office or authorized distributor.
Locate one at:
www.analog.com/adi-sales
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
xv
Supported Processors
• Send questions by mail to:
Processors and DSP Technical Support
Analog Devices, Inc.
Three Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
USA
Supported Processors
This evaluation system supports Analog Devices ADSP-BF561 Blackfin
embedded processors.
Product Information
Product information can be obtained from the Analog Devices Web site
and the online help system.
Analog Devices Web Site
The Analog Devices Web site, www.analog.com, provides information
about a broad range of products—analog integrated circuits, amplifiers,
converters, and digital signal processors.
To access a complete technical library for each processor family, go to
http://www.analog.com/processors/technical_library. The manuals
selection opens a list of current manuals related to the product as well as a
link to the previous revisions of the manuals. When locating your manual
title, note a possible errata check mark next to the title that leads to the
current correction report against the manual.
Also note, myAnalog is a free feature of the Analog Devices Web site that
allows customization of a Web page to display only the latest information
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ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Preface
about products you are interested in. You can choose to receive weekly
e-mail notifications containing updates to the Web pages that meet your
interests, including documentation errata against all manuals.
myAnalog provides access to books, application notes, data sheets, code
examples, and more.
Visit myAnalog (found on the Analog Devices home page) to sign up. If
you are a registered user, just log on. Your user name is your e-mail
address.
EngineerZone
EngineerZone is a technical support forum from Analog Devices. It allows
you direct access to ADI technical support engineers. You can search
FAQs and technical information to get quick answers to your embedded
processing and DSP design questions.
Use EngineerZone to connect with other DSP developers who face similar
design challenges. You can also use this open forum to share knowledge
and collaborate with the ADI support team and your peers. Visit
http://ez.analog.com to sign up.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
xvii
Related Documents
Related Documents
For additional information about the product, refer to the following
publications.
Table 1. Related Processor Publications
Title
Description
ADSP-BF561 Blackfin Embedded Symmetric
Multiprocessor Data Sheet
General functional description, pinout, and
timing of the processor
ADSP-BF561 Blackfin Processor Hardware
Reference
Description of the internal processor architecture and all register functions
Blackfin Processor Programming Reference
Description of all allowed processor assembly
instructions
Notation Conventions
Text conventions used in this manual are identified and described as
follows.
Example
Description
Close command
(File menu)
Titles in reference sections indicate the location of an item within the
development environment’s menu system (for example, the Close command appears on the File menu).
{this | that}
Alternative required items in syntax descriptions appear within curly
brackets and separated by vertical bars; read the example as this or
that. One or the other is required.
[this | that]
Optional items in syntax descriptions appear within brackets and separated by vertical bars; read the example as an optional this or that.
[this,…]
Optional item lists in syntax descriptions appear within brackets delimited by commas and terminated with an ellipse; read the example as an
optional comma-separated list of this.
.SECTION
Commands, directives, keywords, and feature names are in text with
letter gothic font.
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ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Preface
Example
Description
filename
Non-keyword placeholders appear in text with italic style format.

Note: For correct operation, ...
A Note provides supplementary information on a related topic. In the
online version of this book, the word Note appears instead of this
symbol.

Caution: Incorrect device operation may result if ...
Caution: Device damage may result if ...
A Caution identifies conditions or inappropriate usage of the product
that could lead to undesirable results or product damage. In the online
version of this book, the word Caution appears instead of this symbol.

Warning: Injury to device users may result if ...
A Warning identifies conditions or inappropriate usage of the product
that could lead to conditions that are potentially hazardous for the
devices users. In the online version of this book, the word Warning
appears instead of this symbol.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
xix
Notation Conventions
xx
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
1 USING THE ADSP-BF561
EZ-KIT LITE
This chapter provides specific information to assist you with development
of programs for the ADSP-BF561 EZ-KIT Lite evaluation system.
The information appears in the following sections.
• “Package Contents” on page 1-2
Lists the items contained in your ADSP-BF561 EZ-KIT Lite
package.
• “Default Configuration” on page 1-3
Shows the default configuration of the ADSP-BF561 EZ-KIT Lite.
• “CCES Install and Session Startup” on page 1-4
Instructs how to start a new or open an existing
ADSP-BF561EZ-KIT Lite session using CCES.
• “VisualDSP++ Install and Session Startup” on page 1-8
Instructs how to start a new or open an existing
ADSP-BF561EZ-KIT Lite session using VisualDSP++.
• “CCES Evaluation License” on page 1-10
Describes the CCES demo license shipped with the EZ-KIT Lite.
• “VisualDSP++ Evaluation License” on page 1-11
Describes the VisualDSP++ demo license shipped with the EZ-KIT
Lite.
• “Memory Map” on page 1-11
Defines the ADSP-BF561 EZ-KIT Lite’s external memory map.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
1-1
Package Contents
• “LEDs and Push Buttons” on page 1-14·
Describes the board’s LEDs and push buttons.
• “Audio Interface” on page 1-15
Describes the board’s audio interface.
• “Video Interface” on page 1-16
Describes the board’s video interface.
• “Board Design Database” on page 1-17
Describes the board design.
• “Example Programs” on page 1-18
Provides information about the example programs included in the
ADSP-BF561 EZ-KIT Lite evaluation system.
• “Flash Programming Utility” on page 1-18
Highlights the advantages of the Flash Programmer utility.
For information on the graphical user interface, including the boot loading, target options, and other facilities of the EZ-KIT Lite system, refer to
the online help.
For more detailed information about the ADSP-BF561 Blackfin processor, see the documents referred to at “Related Documents”.
Package Contents
Your ADSP-BF561 EZ-KIT Lite evaluation system package contains the
following items.
• ADSP-BF561 EZ-KIT Lite board
• Universal 7V DC power supply
• USB 2.0 cable
1-2
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Using the ADSP-BF561 EZ-KIT Lite
If any item is missing, contact the vendor where you purchased your
EZ-KIT Lite or contact Analog Devices, Inc.
Default Configuration
The EZ-KIT Lite evaluation system contains ESD (electrostatic
discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without
detection. Permanent damage may occur on devices subjected to
high-energy discharges. Proper ESD precautions are recommended
to avoid performance degradation or loss of functionality. Store
unused EZ-KIT Lite boards in the protective shipping package.
The ADSP-BF561 EZ-KIT Lite board is designed to run outside your personal computer as a standalone unit. You do not have to open your
computer case.
When removing the EZ-KIT Lite board from the package, handle the
board carefully to avoid the discharge of static electricity, which may
damage some components. Figure 1-1 shows the default jumper settings,
DIP switch, connector locations, and LEDs used in installation. Confirm
that your board is set up in the default configuration before using the
board.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
1-3
CCES Install and Session Startup
Figure 1-1. EZ-KIT Lite Hardware Setup
CCES Install and Session Startup
For information about CCES and to download the software, go to
www.analog.com/CCES. A link for the ADSP-BF561 EZ-KIT Lite Board
Support Package (BSP) for CCES can be found at
http://www.analog.com/Blackfin/EZKits.
Follow these instructions to ensure correct operation of the product software and hardware.
1-4
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Using the ADSP-BF561 EZ-KIT Lite
Step 1: Connect the EZ-KIT Lite board to a personal computer (PC) running CCES using one of two options: an Analog Devices emulator or via
the debug agent.
Using an Emulator:
1. Plug one side of the USB cable into the USB connector of the emulator. Plug the other side into a USB port of the PC running
CCES.
2. Attach the emulator to the header connector ZP4 (labeled JTAG) on
the EZ-KIT Lite board.
Using the on-board Debug Agent:
1. Plug one side of the USB cable into the USB connector of the
debug agent ZJ1 (labeled USB).
2. Plug the other side of the cable into a USB port of the PC running
CCES.
Step 2: Attach the provided cord and appropriate plug to the power
adaptor.
1. Plug the jack-end of the power adaptor into the power connector
J7 (labeled Power) on the EZ-KIT Lite board.
2. Plug the other side of the power adaptor into a power outlet. The
power LED (labeled LED1) is lit green when power is applied to the
board.
3. Power the emulator (if used). Plug the jack-end of the assembled
power adaptor into the emulator and plug the other side of the
power adaptor into a power outlet. The enable/power is lit green
when power is applied.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
1-5
CCES Install and Session Startup
Step 3 (if connected through the debug agent): Verify that the yellow
USB monitor LED (labeled ZLED3) on the debug agent is on. This signifies
that the board is communicating properly with the host PC and ready to
run CCES.
Session Startup
It is assumed that the CrossCore Embedded Studio software is installed
and running on your PC.
If you connect the board or emulator first (before installing
 Note:
CCES) to the PC, the Windows driver wizard may not find the
board drivers.
1. Navigate to the CCES environment via the Start menu.
Note that CCES is not connected to the target board.
2. Use the system configuration utility to connect to the EZ-KIT Lite
board.
If a debug configuration exists already, select the appropriate
configuration and click Apply and Debug or Debug. Go to step 8.
To create a debug configuration, do one of the following:
• Click the down arrow next to the little bug icon, select
Debug Configurations
• Choose Run > Debug Configurations.
The Debug Configuration dialog box appears.
3. Select CrossCore Embedded Studio Application and click
(New launch configuration).
The Select Processor page of the Session Wizard appears.
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ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Using the ADSP-BF561 EZ-KIT Lite
4. Ensure Blackfin is selected in Processor family. In Processor type,
select ADSP-BF561. Click Next.
The Select Connection Type page of the Session Wizard appears.
5. Select one of the following:
• For standalone debug agent connections, EZ-KIT Lite and
click Next.
• For emulator connections, Emulator and click Next.
The Select Platform page of the Session Wizard appears.
6. Do one of the following:
• For standalone debug agent connections, ensure that the
selected platform is ADSP-BF561 EZ-KIT Lite via Debug
Agent.
• For emulator connections, choose the type of emulator that
is connected to the board.
7. Click Finish to close the wizard.
The new debug configuration is created and added to the program(s) to load list.
8. In the Program(s) to load section, choose the program to load
when connecting to the board. If not loading any program upon
connection to the target, do not make any changes.
Note that while connected to the target, there is no way to choose a
program to download. To load a program once connected, terminate the session.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
1-7
VisualDSP++ Install and Session Startup
a configuration, go to the Debug Configurations dialog
 Toboxdelete
and select the configuration to delete. Click
and choose Yes
when asked if you wish to delete the selected launch configuration.
Then Close the dialog box.
from the target board, click the terminate button
 To(reddisconnect
box) or choose Run > Terminate.
To delete a session, choose Target > Session > Session List. Select
the session name from the list and click Delete. Click OK.
VisualDSP++ Install and Session Startup
For information about VisualDSP++ and to download the software, go to
www.analog.com/VisualDSP.
1. Verify that the yellow USB monitor LED (ZLED3, located near the
USB connector) is lit. This signifies that the board is communicating properly with the host PC and is ready to run VisualDSP++.
2. If you are running VisualDSP++ for the first time, navigate to the
VisualDSP++ environment via the Start > Programs menu. The
main window appears. Note that VisualDSP++ does not connect to
any session. Skip the rest of this step to step 3.
If you have run VisualDSP++ previously, the last opened session
appears on the screen. You can override the default behavior and
force VisualDSP++ to start a new session by pressing and holding
down the Ctrl key while starting VisualDSP++. Do not release the
Ctrl key until the Session Wizard appears on the screen. Go to
step 4.
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ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Using the ADSP-BF561 EZ-KIT Lite
3. To connect to a new EZ-KIT Lite session, start Session Wizard by
selecting one of the following.
• From the Session menu, New Session.
• From the Session menu, Session List. Then click New Session from the Session List dialog box.
• From the Session menu, Connect to Target.
4. The Select Processor page of the wizard appears on the screen.
Ensure Blackfin is selected in Processor family. In Choose a target
processor, select ADSP-BF561. Click Next.
5. The Select Connection Type page of the wizard appears on the
screen. Select EZ-KIT Lite and click Next.
6. The Select Platform page of the wizard appears on the screen.
In the Select your platform list, select ADSP-BF561 EZ-KIT Lite
via Debug Agent. In Session name, highlight or specify the session
name.
The session name can be a string of any length; although, the box
displays approximately 32 characters. The session name can
include space characters. If you do not specify a session name,
VisualDSP++ creates a session name by combining the name of the
selected platform with the selected processor. The only way to
change a session name later is to delete the session and to open a
new session.
Click Next.
7. The Finish page of the wizard appears on the screen. The page displays your selections. If you are satisfied, click Finish. If not, click
Back to make changes.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
1-9
CCES Evaluation License
disconnect from a session, click the disconnect button
 Toor select
Session > Disconnect from Target.
To delete a session, select Session > Session List. Select the session
name from the list and click Delete. Click OK.
CCES Evaluation License
The ADSP-BF561 EZ-KIT Lite software is part of the Board Support
Package (BSP) for the Blackfin ADSP-BF56x family. The EZ-KIT Lite is
a licensed product that offers an unrestricted evaluation license for 90 days
after activation. Once the evaluation period ends, the evaluation license
becomes permanently disabled. If the evaluation license is installed but
not activated, it allows 10 days of unrestricted use and then becomes disabled. The license can be re-enabled by activation.
An evaluation license can be upgraded to a full license. Licenses can be
purchased from:
• Analog Devices directly. Call (800) 262-5645 or 781-937-2384 or
go to:
http://www.analog.com/buyonline.
• Analog Devices, Inc. local sales office or authorized distributor. To
locate one, go to:
http://www.analog.com/salesdir/continent.asp.
EZ-KIT Lite hardware must be connected and powered up to
 The
use CCES with a valid evaluation or full license.
1-10
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Using the ADSP-BF561 EZ-KIT Lite
VisualDSP++ Evaluation License
The ADSP-BF561 EZ-KIT Lite installation is part of the VisualDSP++
installation. The EZ-KIT Lite is a licensed product that offers an unrestricted evaluation license for the first 90 days. Once the initial
unrestricted 90-day evaluation license expires:
• VisualDSP++ allows a connection to the ADSP-BF561 EZ-KIT
Lite via the USB Debug Agent interface only. Connections to simulators and emulation products are no longer allowed.
• The linker restricts a user’s program to 41 KB of memory for code
space with no restrictions for data space.
avoid errors when opening VisualDSP++, the EZ-KIT Lite
 Tohardware
must be connected and powered up. This is true for using
VisualDSP++ with a valid evaluation or full license.
Memory Map
The EZ-KIT Lite board includes two types of external memory, 64-MB
SDRAM and 8-MB flash. See the external memory map in Table 1-1. The
complete configuration of the ADSP-BF561 processor internal SRAM is
detailed in Figure 1-2.
Table 1-1. EZ-KIT Lite External Memory Map
Start Address
End Address
Description
0x00000000
0x3FFFFFF
SDRAM bank 0; see “Memory Map” on page 1-11
0x20000000
0x207FFFFF
ASYNC memory bank 0; see “Memory Map” on page 1-11.
All other locations
Not used
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
1-11
Memory Map
CORE A MEMORY MAP
CORE B MEMORY MAP
0XFFFF FFFF
CORE MMR REGISTERS
0XFFE0 0000
0XFFB0 1000
0XFFB0 0000
0XFFA1 4000
0XFFA1 0000
0XFFA0 4000
0XFFA0 0000
0XFF90 8000
0XFF90 4000
0XFF90 0000
0XFF80 8000
0XFF80 4000
0XFF80 0000
RESERVED
L1 SCRATCHPAD SRAM (4K)
RESERVED
L1 INSTRUCTION SRAM/CACHE (16K)
RESERVED
L1 INSTRUCTION SRAM (16K)
L1 DATA BANK B SRAM (16K)
RESERVED
L1 DATA BANK A SRAM/CACHE (16K)
L1 DATA BANK A SRAM (16K)
RESERVED
L1 SCRATCHPAD SRAM (4K)
0XFF70 0000
RESERVED
0XFF61 4000
L1 INSTRUCTION SRAM/CACHE (16K)
0XFF61 0000
RESERVED
0XFF60 4000
0XFF50 8000
0XFF50 4000
0XFF50 0000
0XFF40 8000
0XFF40 4000
0XFF40 0000
0XFEB2 0000
0XFEB0 0000
0XEF00 0800
RESERVED
RESERVED
L1 DATA BANK B SRAM/CACHE (16K)
0XFF70 1000
0XFF60 0000
CORE MMR REGISTERS
SYSTEM MMR REGISTERS
0XFFC0 0000
RESERVED
L1 INSTRUCTION SRAM (16K)
RESERVED
L1 DATA BANK B SRAM/CACHE (16K)
L1 DATA BANK B SRAM (16K)
RESERVED
L1 DATA BANK A SRAM/CACHE (16K)
L1 DATA BANK A SRAM (16K)
RESERVED
L2 SRAM (128K)
RESERVED
Figure 1-2. ADSP-BF561 Processor Internal Memory Map
The 8 MB of flash memory is organized as 4M x 16 bit and mapped into a
ADSP-BF561 processor’s ASYNC memory bank 0. The AMS0 memory
select signal connects to the output enable pin of flash memory.
The 64 MB of SDRAM is organized as 16M x 32 bits wide. The processor’s memory select pin SMS0 is configured for SDRAM. Three SDRAM
control registers must be initialized in order to access the SDRAM
memory.
1-12
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Using the ADSP-BF561 EZ-KIT Lite
When in a CCES or VisualDSP++ session, you can configure the SDRAM
registers automatically:
• CCES users, choose Target > Settings > Target Options > Use
XML reset values
• VisualDSP++ users, choose Settings > Target Options > Use XML
reset values
The EBIU_SDGCTL, EBIU_SDBCTL, and EBIU_SDRRC register values have been
set in the ADSP-BF561-proc.xml file found in your System\ArchDef folder.
These values can be changed to be more optimal depending on the SCLK
frequency.
The values in Table 1-2 are set by default whenever bank 0 is accessed
through the debugger (for example, when viewing memory windows or
loading a program). The numbers are derived for maximum flexibility and
work for a system clock frequency between 60 MHz and 133 MHz.
Table 1-2. EZ-KIT Lite Session SDRAM Default Settings
Register
Value
Function
EBIU_SDGCTL
0x0091998D
Calculated with SCLK = 133 MHz
EBIU_SDBCTL
0x00000013
EBIU_SDRRC
0x000001CF
Calculated with SCLK = 120 MHz
The EBIU_SDGCTL register can be written once after the processor comes
out of reset. Therefore, the user code should not re-initialize the register.
Clearing the Use XML reset values check box allows manual configuration of the EBIU registers. For more information, see online help.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
1-13
LEDs and Push Buttons
Automatic configuration of SDRAM is not optimized for a specific SCLK
frequency. Table 1-3 shows the optimized configuration of the SDRAM
registers using a 120 MHz SCLK. The frequency of 120 MHz is the maximum SCLK frequency when using a 600 MHz core frequency, the
maximum frequency for the EZ-KIT Lite. Only the EBIU_SDRRC register
needs to be modified in the user code to achieve maximum performance.
Table 1-3. SDRAM Optimum Settings1
Register
Value
EBIU_SDGCTL
0x0091998D
EBIU_SDBCTL
0x00000013
EBIU_SDRRC
0x000003A0
1 Calculated with SCLK = 120 MHz
For more information, see “External Bus Interface Unit” on page 2-3.
program is included in the EZ-KIT installation direc Antoryexample
to demonstrate the SDRAM interface setup.
LEDs and Push Buttons
The EZ-KIT Lite provides four push buttons and sixteen LEDs for general-purpose IO.
Sixteen LEDs, labeled LED5 through LED20, are controlled by the processor’s programmable flags PF32 through PF47 (equivalent to PPI0_D15–8
and PPI1_D15–8). These LEDs are accessed through the FLAG 2 registers.
First, the direction must be configured to output by setting the bits of the
FIO2_DIR register to 1. Then the value of the LEDs are modified using one
of the FIO2_FLAG_D, FIO2_FLAG_C, FIO2_FLAG_S, or FIO2_FLAG_T registers.
The four general-purpose push buttons are labeled SW6 through SW9. The
buttons connect to the programmable flags PF8–5. A status of each
1-14
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Using the ADSP-BF561 EZ-KIT Lite
individual button can be read through the FIO0_FLAG_D register. A switch
is being pressed-on when the corresponding bit of the register reads 1.
When the switch is released, the bit reads 0. A connection between the
push button and PF input is established through the SW4 DIP switch.
For information on how to disconnect the switch from the programmable
flag and use it for another objective, see “Push Button Enable Switch
(SW4)”.
example program is included in the EZ-KIT Lite installation
 Andirectory
to demonstrate functionality of the LEDs and push
buttons.
Audio Interface
The AD1836A audio codec provides three channels of stereo audio output
and two channels of multichannel 96 kHz input. The SPORT0 interface of
the processor links with the stereo audio data input and output pins of the
AD1836A codec. The processor is capable of transferring data to the
audio codec in time-division multiplexed (TDM) or 2-wire serial interface
(TWI) mode.
In TWI mode, the codec can operate at a 96 kHz sample rate but restricts
the output to two channels. In TDM mode, the codec can operate at a
maximum of 48 kHz sample rate but allows simultaneous use of all input
and output channels. When using TWI mode, the TSCLK0 and RSCLK0 pins
(as well as the TFS0 and RFS0 pins of the processor) must be tied together
externally to the processor. This is accomplished with the SW4 DIP switch.
See “Push Button Enable Switch (SW4)” on page 2-12 for more
information.
The AD1836A audio codec’s internal configuration registers are configured using the processor’s PF4 programmable flag pin, used as the select
for the audio device. For more information on how to configure the
multichannel codec, go to www.analog.com/AD1836A.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
1-15
Video Interface
The AD1836A codec reset is controlled by the processor’s programmable
flag PF15. When PF15 is 0, the reset is asserted. When PF15 is 1, the reset is
de-asserted. Note that when PF15 is not driven (configured as input), the
AD1836A reset is asserted due to the pull-down resistor. See “Programmable Flags” on page 2-4 for more information.
programs are included in the EZ-KIT Lite installation
 Example
directory to demonstrate the AD1836A codec operation.
Video Interface
The board supports video input and output applications. The ADV7179
video encoder provides up to three output channels of analog video, while
the ADV7183A video decoder provides up to three input channels of analog video. The video encoder connects to the parallel peripheral
interface 1 (PPI1), while the video decoder connects to the parallel peripheral interface 0, (PPI0). Each PPI interface has an individual clock that is
configured by the SW5 switch settings. See “PPI Clock Select Switch
(SW5)” on page 2-13 for more information.
Both the encoder and the decoder connect to the parallel peripheral interfaces (PPI input clock) of the processor. For additional information on the
video interface hardware, refer to “PPI Interfaces” on page 2-5.
For the video interface to be operational, the following basic steps must be
performed.
1. Configure the SW2 DIP switch as required by the application. Refer
to “Video Configuration Switch (SW2)” on page 2-10 for details.
2. De-assert the video device’s reset by setting high a corresponding
programmable flag. PF14 controls the ADV7179 encoder’s reset,
while PF13 controls the ADV7183A decoder’s reset.
1-16
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Using the ADSP-BF561 EZ-KIT Lite
3. If using the ADV7183A decoder:
• Enable device by driving programmable flag output PF2 to
0.
• Select PPI0 clock; for details, refer to “PPI Clock Select
Switch (SW5)” on page 2-13.
4. Program internal registers of the video device in use. Both video
encoder and decoder use a 2-wire serial interface to access internal
registers. The PF0 programmable flag functions as a serial clock
(SCL), and PF1 functions as a serial data (SDAT).
5. Program the ADSP-BF561 processor’s PPI interfaces (configuration registers, DMA, and so on).
programs are included in the EZ-KIT Lite installation
 Example
directory to demonstrate the capabilities of the video interface.
Board Design Database
A .zip file containing all of the electronic information required for the
design, layout, fabrication and assembly of the product is available for
download from the Analog Devices board design database at:
http://www.analog.com/board-design-database.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
1-17
Example Programs
Example Programs
Example programs are provided with the ADSP-BF561 EZ-KIT Lite to
demonstrate various capabilities of the product. The programs are
included in the product installation kit and can be found in the Examples
folder of the installation. Refer to a readme file provided with each example for more information.
CCES users are encouraged to use the example browser to find examples
included with the EZ-KIT Lite Board Support Package.
Flash Programming Utility
The ADSP-BF561 EZ-KIT Lite evaluation system includes a flash programming utility. The utility allows you to program flash memory on the
EZ-KIT Lite. The utility installed with VisualDSP++ is called Flash Programmer. The utility installed with CCES is called Device Programmer.
The flash programming driver is core-specific (core A) and must be loaded
to core A in order to operate correctly. The flash programming utility
relies on the user to set the correct core focus. To set the correct core,
select core A in the multiprocessor window before opening the utility
interface.
For more information on the flash programming utility, refer to the
online help.
1-18
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2 ADSP-BF561 EZ-KIT LITE
HARDWARE REFERENCE
This chapter describes the hardware design of the ADSP-BF561 EZ-KIT
Lite board. The following topics are covered.
• “System Architecture” on page 2-2
Describes the ADSP-BF561 EZ-KIT Lite configuration and
explains how the board components interface with the processor.
• “Jumper and DIP Switch Settings” on page 2-10
Shows the locations and describes the configuration jumpers and
switches.
• “LEDs and Push Buttons” on page 2-15
Shows the locations and describes the LEDs and push buttons.
• “Connectors” on page 2-18
Shows the locations and provides part numbers for the on-board
connectors. In addition, the manufacturer and part number information is provided for the mating parts.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-1
System Architecture
System Architecture
This section describes the processor’s configuration on the EZ-KIT Lite
board.
Figure 2-1. System Architecture
This EZ-KIT Lite has been designed to demonstrate the capabilities of the
ADSP-BF561 Blackfin processor. The processor has an IO voltage of
3.3V. The core voltage and the core clock rate can be set on the fly by the
processor. The input clock is 30 MHz.
2-2
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
ADSP-BF561 EZ-KIT Lite Hardware Reference
External Bus Interface Unit
The external bus interface unit (EBIU) connects external memory to the
ADSP-BF561 processor. It includes a 32-bit wide data bus, an address bus
(A25–2), and a control bus. All of the 8-bit, 16-bit, and 32-bit accesses are
supported. On the EZ-KIT Lite board, the EBI unit connects to SDRAM
and flash memory. For more information on using the external memory
see “Memory Map” on page 1-11.
All of the address, data, and control signals are available externally via the
expansion interface connectors (J1–3). The pinout of these connectors can
be found in “ADSP-BF561 EZ-KIT Lite Schematic” on page B-1.
SPORT Audio Interface
The SPORT0 interface connects to the AD1836A audio codec and the
expansion interface. The AD1836A codec uses both the primary and secondary data transmit and receive pins to input and output data from the
audio input and outputs.
The SPORT1 interface connects to the SPORT connector (P3).
The pinout of the SPORT and expansion interface connectors can be found
in “ADSP-BF561 EZ-KIT Lite Schematic” on page B-1.
SPI Interface
The processor’s serial peripheral interface (SPI) connects to the AD1836A
audio codec and the expansion interface. The SPI connection to the
AD1836A codec is used to access the control registers of the device. The
PF4 flag of the processor acts as the device select for the SPI port.
The SPI signals are available on the expansion interface and on the SPI
connector (P5). The pinout for the interface can be found in
“ADSP-BF561 EZ-KIT Lite Schematic” on page B-1.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-3
System Architecture
Programmable Flags
The processor has 48 programmable flag pins (PFs). Many of the flags are
multi-functional and depend on the processor’s setup. Table 2-1 shows
how the programmable flag pins are used on the EZ-KIT Lite.
Table 2-1. Programmable Flag Connections
2-4
Processor PF Pin
Processor Function
EZ-KIT Lite Function
PF0
SPI select S, timer 0
Serial clock for programming ADV7179 video
encoder and ADV7183A video decoder.
PF1
SPI select 1, timer 1
Serial data for programming ADV7179 video encoder
and ADV7183A video decoder.
PF2
SPI select 2, timer 2
ADV7183A video decoder’s OE.
PF3
SPI select 3, timer 3
ADV7183A FIELD pin. See “Video Configuration
Switch (SW2)” on page 2-10.
PF4
SPI select 4, timer 4
AD1836A audio codec’s SPI select.
PF5
SPI select 5, timer 5
Push button (SW6). See “LEDs and Push Buttons” on
page 1-14 and “Push Button Enable Switch (SW4)”
on page 2-12 for information on how to disable the
push button.
PF6
SPI select 6, timer 6
Push button (SW7). See “LEDs and Push Buttons” on
page 1-14 and “Push Button Enable Switch (SW4)”
on page 2-12 for information on how to disable the
push button.
PF7
SPI select 7, timer 7
Push button (SW8). See “LEDs and Push Buttons” on
page 1-14 and “Push Button Enable Switch (SW4)”
on page 2-12 for information on how to disable the
push button.
PF8
Push button (SW9). See “LEDs and Push Buttons”
on page 1-14 and “Push Button Enable Switch
(SW4)” on page 2-12 for information on how to disable the push button.
PF9–12
Not used
PF13
ADV7183A video decoder’s reset
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
ADSP-BF561 EZ-KIT Lite Hardware Reference
Table 2-1. Programmable Flag Connections (Cont’d)
Processor PF Pin
Processor Function
EZ-KIT Lite Function
PF14
ADV7179 video encoder’s reset
PF15
AD1836 codec’s reset
PF16
SPORT0
transmit frame sync pin
PF17
SPORT0
transmit data secondary pin
PF18
SPORT0
transmit data primary pin
PF19
SPORT0
receive frame sync pin
PF20
SPORT0
receive data secondary pin
PF21
SPORT1
transmit frame pin
PF22
SPORT1
transmit data secondary pin
PF23
SPORT1
transmit data primary pin
PF24
SPORT1
receive frame sync pin
PF25
SPORT1
receive data secondary pin
PF26
UART
transmit pin
PF27
UART
receive pin
PF28
SPORT0
receive serial clock pin
PF29
SPORT0
transmit serial clock pin
PF30
SPORT1
receive serial clock pin
PF31
SPORT1
transmit serial clock pin
PF39–32
PPI1
data 15–8
LED13–20
PF47–40
PPI0
data 15–8
LED5–12
PPI Interfaces
The ADSP-BF561 processor employs two independent parallel peripheral
interfaces (PPIs), PPI0 and PPI1. Each PPI interface is a half-duplex,
bi-directional bus consisting of 16 bits of data, a dedicated input clock,
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-5
System Architecture
and synchronization signals. The ADSP-BF561 EZ-KIT Lite board utilizes the PPI interfaces for video input and video output.
The PPI0 interface is configured to input video data from the ADV7183A
video decoder device: bits 7–0 connect to the video decoder’s data outputs.
The PPI1 interface is configured to output video data to the ADV7179
video encoder device: bits 7–0 connect to the video encoder’s data inputs.
Each PPI interface has a dedicated clock input configured independently
by the SW5 switch. The clock source can be one of the following: 27 MHz
crystal oscillator, ADV7183A video decoder’s clock output, or external
clock from the expansion interface. See “PPI Clock Select Switch (SW5)”
on page 2-13 for more information about the switch.
The SW2 switch provides a flexible connection between dedicated synchronization IOs (SYNC1 and SYNC2 of each PPI interface) and the encoder’s
and decoder’s horizontal and vertical synchronization pins. See “Video
Configuration Switch (SW2)” on page 2-10 for more information about
the switch. For a detailed description of the ADSP-BF561 processor’s PPI
interfaces, refer to the ADSP-BF561 Blackfin Processor Hardware Reference.
Table 2-2 describes the PPI pins of the EZ-KIT Lite board.
Table 2-2. PPI Connections
Processor PPI Pin
EZ-KIT Lite Function
PPI0
bits 7–0
ADV7183A data outputs P15–8
PPI1
bits 7–0
ADV7179 data inputs P7–0
PPI0 SYNC1
Timer 8
ADV7179 HSYNC. For more information, see “Video
Configuration Switch (SW2)” on page 2-10.
PPI0 SYNC2
Timer 9
ADV7179 VSYNC. For more information, see “Video
Configuration Switch (SW2)” on page 2-10.
PPI0 clock
2-6
Other Processor
Function
A choice of ADV7183A output clock, a local
27 MHz oscillator, or an external clock from
ADSP-BF533/BF561 Blackfin EZ-Extender®.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
ADSP-BF561 EZ-KIT Lite Hardware Reference
Table 2-2. PPI Connections (Cont’d)
Processor PPI Pin
Other Processor
Function
EZ-KIT Lite Function
PPI1 SYNC1
Timer 10
ADV7183A HSYNC. For more information, see
“Video Configuration Switch (SW2)” on page 2-10.
PPI1 SYNC2
Timer 11
ADV7183A VSYNC. For more information, see
“Video Configuration Switch (SW2)” on page 2-10.
PPI1 clock
A choice of ADV7183A output clock, a local
27 MHz oscillator, or an external clock from
ADSP-BF53x/BF561 Blackfin EZ-Extender.
Video Output (PPI1)
The PPI1 interface is configured as output and connects to the on-board
video encoder device, ADV7179. The ADV7179 encoder generates three
analog video channels on DAC A, DAC B, and DAC C. The PPI1 bits 7–0 connect to P7–0 of the encoder’s pixel inputs. The encoder’s input clock is
fixed and comes from an on-board 27 MHz oscillator.
The encoder’s synchronization signals, HSYNC and VSYNC, can be configured as inputs or outputs. Video blanking control signal is at level 1. The
HSYNC and VSYNC signals can connect to SYNC1 and SYNC2 of the processor’s
PPI1 interface via the SW2 switch, as described in “Video Configuration
Switch (SW2)” on page 2-10.
Video Input (PPI0)
The PPI0 interface is configured as input and connects to the on-board
video decoder device, ADV7183A. The ADV7183A decoder receives three
analog video channels on AIN1, AIN4, and AIN5 input. The decoder’s pixel
data outputs P15–8 drive the PPI0 inputs 8–0. The decoder’s 27 MHz pixel
clock output can be selected to drive any of the PPI clocks as shown in
Table 2-7 on page 2-13.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-7
System Architecture
Synchronization outputs of the decoder, HS/HACTIVE, VS/VACTIVE, and
FIELD can connect to the processor’s PPI0_SYNC1, PPI0_SYNC2, and PF3
flag via the SW2 DIP switch, as described in “Video Configuration Switch
(SW2)” on page 2-10.
UART Port
The processor’s universal asynchronous receiver/transmitter (UART) port
connects to the ADM3202 RS-232 line driver as well as to the expansion
interface. The RS-232 line driver is attached to the DB9 male connector,
providing an interface to a personal computer and other serial devices.
Expansion Interface
The expansion interface consists of the three 90-pin connectors, J1–3.
Table 2-3 shows the interfaces each connector provides. For the exact pinout of the connectors, refer to “ADSP-BF561 EZ-KIT Lite Schematic” on
page B-1. The mechanical dimensions of the connectors can be obtained
from Technical Support.
Table 2-3. Connector Interfaces
Connector Interfaces
2-8
J1
5V, GND, address, data, PPI0 3–0, PF15–6, PF4
J2
3.3V, GND, SPI, NMI, PPI0 SYNC3–1, SPORT0, SPORT1, PF15–0, EBUI control signals
J3
5V, 3.3V, GND, UART, PPI1 15–0, reset, video control signals
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
ADSP-BF561 EZ-KIT Lite Hardware Reference
Limits to the current and to the interface speed must be taken into consideration when using the expansion interface. The maximum current limit is
dependent on the capabilities of the used regulator. Additional circuitry
also can add extra loading to signals, decreasing their maximum effective
speed.
Devices does not support and is not responsible for the
 Analog
effects of additional circuitry.
JTAG Emulation Port
The JTAG emulation port allows an emulator to access internal and external memories of the processor through a 6-pin interface. The JTAG
emulation port of the processor also connects to the USB debugging interface. When an emulator connects to the board at ZP4, the USB debugging
interface is disabled. See “JTAG (ZP4)” on page 2-22 for more information about the JTAG connector.
To learn more about available emulators, go to
http://www.analog.com/processors/tools/blackfin.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-9
Jumper and DIP Switch Settings
Jumper and DIP Switch Settings
This section describes functionality of the jumpers and DIP switches. The
jumper and DIP switch locations are shown in Figure 2-2.
Figure 2-2. DIP Switch Locations
Video Configuration Switch (SW2)
The video configuration switch (SW2) determines how some video signals
from the ADV7183A video decoder and ADV7179 video encoder are
routed to the processor’s PPIs. The switch also determines if the PF2 pin
controls the OE signal of the ADV7183A video decoder outputs. See
Table 2-4.
2-10
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ADSP-BF561 EZ-KIT Lite Hardware Reference
Table 2-4. Video Configuration Switch (SW2)
Switch Position (Default)
Processor Signal
Video Signal
1 (OFF)
PPI1 SYNC1
ADV7179
2 (OFF)
PPI0 SYNC1
ADV7183A
3 (OFF)
PPI1 SYNC2
ADV7183A
4 (OFF)
PPI1 SYNC2
ADV7179
5 (OFF)
PF3 (FIELD)
ADV7183A
6 (ON)
PF2
ADV7183A
Positions 1 thorough 5 of SW2 determine how and if the SYNC1, SYNC2, and
FIELD control signals of the PPI0 and PPI1 interfaces are routed to the processor’s PPIs. In standard configuration of the encoder and decoder, this is
not necessary because the processor is capable of reading the control information embedded in the data stream.
Position 6 of SW2 determines whether PF2 connects to the OE signal of the
ADV7183A device. When the switch is OFF, PF2 can be used for other
operations, and the decoder output enable is held high with a pull-up
resistor.
Boot Mode Switch (SW3)
Positions 1 and 2 of the SW3 switch set the boot mode of the processor, as
described in Table 2-5. Position 3 sets the processor’s PLL on boot—
when the position is ON, the PLL is in bypass.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-11
Jumper and DIP Switch Settings
Table 2-5. Boot Mode Select Switch (SW3)
Position 1 BMODE0
Position 2 BMODE1
Boot Mode
ON
ON
Execute from 16-bit external
memory
(Bypass Boot ROM)
OFF
ON
Boot from 8-bit/16-bit flash
(default)
ON
OFF
Boot from SPI host slave mode
OFF
OFF
Boot from SPI serial EEPROM
(16-, 24-bit address range)
Push Button Enable Switch (SW4)
Positions 1 through 4 of the push button enable switch (SW4) allow to disconnect the drivers associated with the push buttons from the PF pins of
the processor. Positions 5 and 6 connect the transmit and receive frame
syncs and clocks of SPORT0. This is important when the AD1836A audio
codec and the processor are communicating in 2-wire interface (TWI)
mode. Table 2-6 shows which PF is driven when the switch is ON.
Table 2-6. Push Button Enable Switch (SW4)
Switch Position
Default Setting
Pin #
Signal (Side 1)
Pin #
Signal (Side 2)
1
ON
1
SW6
12
PF5
2
ON
2
SW7
11
PF6
3
ON
3
SW8
10
PF7
4
ON
4
SW9
9
PF8
5
OFF
5
TFS0
8
RFS0
6
OFF
6
RSCLK0
7
TSCLK0
2-12
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
ADSP-BF561 EZ-KIT Lite Hardware Reference
PPI Clock Select Switch (SW5)
The SW5 switch controls a clock selection of the PPI interfaces as described
in Table 2-7 and Table 2-8.
Table 2-7. PPICLK1 Clock Source Setup
SW5 Position 1
PPI0_CKSEL0
SW5 Position 2
PPI0_CKSEL1
PPIxCLK1 Source
ON
ON
27 MHz oscillator (default)
OFF
ON
ADV7183 clock out
X
OFF
Expansion interface
Table 2-8. PPICLK2 Clock Source Setup
SW5 Position 3
PPI1_CKSEL0
SW5 Position 4
PPI1_CKSEL1
PPICLK2 Source
ON
ON
27 MHz oscillator (default)
OFF
ON
ADV7183 clock out
X
OFF
Expansion interface
Test DIP Switches (SW10 and SW11)
Two DIP switches (SW10 and SW11) are located on the bottom of the
board. The switches are used only for testing and should remain in the OFF
position.
Audio Enable Switch (SW12)
The audio enable switch (SW12) disconnects the audio signals from the
processor. The default is all positions ON.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-13
Jumper and DIP Switch Settings
SPIS1/SPISS Select (SW13)
The SPIS1/SPISS select switch (SW13) disconnects the SPIS1 and SPISS signals from the board, making them available on the SPI connector (P5).
The default is the ON position.
Video Encoder Clock Select Jumper (JP1)
The video encoder clock select jumper (JP1) determines the source of the
ADV7179 video encoder’s clock. The jumper setting is shown in
Table 2-9.
Table 2-9. Video Encoder Clock Select Jumper (JP1)
JP1 Position
Mode
1 and 2
Input clock for encoder is generated from 27 MHz oscillator (default)
2 and 3
Input clock for encoder is generated from output clock of decoder. This is
used when synchronizing the encoder and decoder clock is required.
VDDINT Select Jumpers (JP2 and JP3)
The processor internal voltage (VDDINT) select jumpers (JP2–3) determine
the source of the processor’s internal voltage. For the core clock set at
533 MHz and higher, select the on-board external regulator for VDDINT.
The jumper settings are shown in Table 2-10.
Table 2-10. Processor Internal Voltage Select Jumpers (JP2 and JP3)
JP2
JP3
VDDINT Source
Not populated
1 and 2 ON
Provided by the on-board external regulator
Populated
2 and 3 ON
Provided by the processor through the VROUT pins
(internal regulator)
2-14
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
ADSP-BF561 EZ-KIT Lite Hardware Reference
UART Loop Jumper (P1)
The UART loop jumper (P1) is for looping the transmit and receive signals. The default is the OFF position.
LEDs and Push Buttons
This section describes functionality of the LEDs and push buttons.
Figure 2-3 shows the locations of the LEDs and push buttons.
Figure 2-3. LED and Push Button Locations
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-15
LEDs and Push Buttons
Reset Push Button (SW1)
The RESET push button resets all of the ICs on the board. One exception is
the USB interface chip (U34). The chip is not being reset when the push
button is pressed after the USB cable has been plugged in and communication with the PC has been initialized correctly. Once communication is
initialized, the only way to reset the USB is by powering down the board.
Programmable Flag Push Buttons (SW6–9)
Four push buttons, SW6–9, are provided for general-purpose user input.
The buttons connect to the programmable flag pins of the processor (PF5–
8). The push buttons are active high and, when pressed, send a high (1) to
the processor. Refer to “LEDs and Push Buttons” on page 1-14 for more
information on how to use PFs when programming the processor. The
push button enable switch (SW4) is capable of disconnecting the push buttons from its associated PF (refer to “Push Button Enable Switch (SW4)”
on page 2-12). The programmable flag pins and corresponding switches
are shown in Table 2-11.
Table 2-11. Programmable Flag Switches
Processor Programmable Flag Pin
Push Button Reference Designator
PF5
SW6
PF6
SW7
PF7
SW8
PF8
SW9
Power LED (LED1)
When LED1 is lit (green), it indicates that power is being supplied to the
board properly.
2-16
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
ADSP-BF561 EZ-KIT Lite Hardware Reference
Reset LED (LED2)
When LED2 is lit, it indicates that the master reset of all major ICs is
active.
USB Monitor LED (ZLED3)
The USB monitor LED (ZLED3) indicates that USB communication has
been initialized successfully and you can connect to the processor using an
EZ-KIT Lite session. This takes approximately 15 seconds. If the LED
does not light, try cycling power on the board and/or reinstalling the USB
driver.
the development software is actively communicating with
 When
the EZ-KIT Lite target board, the LED can flicker, indicating
communications handshake.
User LEDs (LED5–12, LED13–20)
Sixteen LEDs connect to the processor’s programmable flags. Eight LEDs
labeled LED5 through LED12 are controlled by programmable flags PF40
through PF47 (equivalent to PPI0_D15–8). Eight LEDs labeled LED13
through LED20 are controlled by programmable flags PF32 through PF39
(equivalent to PPI1_D15–8). To learn how to use the LEDs, refer to “LEDs
and Push Buttons” on page 1-14.
Table 2-12. User LEDs
LED Reference Designator Flag Port Name
LED Reference Designator Flag Port Name
LED5
PB40
LED13
PB32
LED6
PB41
LED14
PB33
LED7
PB42
LED15
PB34
LED8
PB43
LED16
PB35
LED9
PB44
LED17
PB36
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-17
Connectors
Table 2-12. User LEDs (Cont’d)
LED Reference Designator Flag Port Name
LED Reference Designator Flag Port Name
LED10
PB45
LED18
PB37
LED11
PB46
LED19
PB38
LED12
PB47
LED20
PB39
Connectors
This section describes the connector functionality and provides information about mating connectors. The connector locations are shown in
Figure 2-4.
Figure 2-4. Connector Locations
2-18
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
ADSP-BF561 EZ-KIT Lite Hardware Reference
Expansion Interface (J1–3)
Three board-to-board connector footprints provide signals for most of the
processor’s peripheral interfaces. The connectors are located at the bottom
of the board. For more information about the interface, see “Expansion
Interface” on page 2-8. For the availability and pricing of the J1, J2, and
J3 connectors, contact Samtec.
Part Description
Manufacturer
Part Number
90-position 0.05" spacing, SMT
(J1, J2, J3)
SAMTEC
SFC-145-T2-F-D-A
Mating Connector
90-position 0.05” spacing
(through hole)
SAMTEC
TFM-145-x1 series
90-position 0.05” spacing
(surface mount)
SAMTEC
TFM-145-x2 series
90-position 0.05” spacing
(low cost)
SAMTEC
TFC-145 series
Part Description
Manufacturer
Part Number
2x2 RCA jacks (J4)
SWITCHCRAFT
PJRAS2X2S01X
3x2 RCA jacks (J5)
SWITCHCRAFT
PJRAS3X2S01X
Audio (J4 and J5)
Mating Connector
Two channel RCA interconnect
cable
MONSTER CABLE
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
BI100-1M
2-19
Connectors
Video (J6)
Part Description
Manufacturer
Part Number
3x2 RCA jacks (J6)
SWITCHCRAFT
PJRAS3X2S01X
Power (J7)
The power connector provides all of the power necessary to operate the
EZ-KIT Lite board.
Part Description
Manufacturer
Part Number
2.5 mm power jack (J7)
SWITCHCRAFT
RAPC712X
Mating Power Supply (shipped with EZ-KIT Lite)
7V power supply
CUI INC.
DMS070214-P6P-SZ
The power connector supplies DC power to the EZ-KIT Lite board.
RS-232 (P2)
Part Description
Manufacturer
Part Number
DB9, male, right angle (P2)
TYCO
5747250-4
Mating Assembly
2m female-to-female cable
2-20
DIGI-KEY
AE1016-ND
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
ADSP-BF561 EZ-KIT Lite Hardware Reference
SPORT1 (P3)
The SPORT1 connector is linked to a 20-pin connector. The connector’s
pinout can be found in “ADSP-BF561 EZ-KIT Lite Schematic” on
page B-1.
Part Description
Manufacturer
Part Number
IDC header
FCI
68737-420HLF
Mating Connectors
IDC socket
DIGI-KEY
S4210-ND
SPI (P5)
The SPI connector is linked to a 12-pin connector. The connector’s pinout can be found in “ADSP-BF561 EZ-KIT Lite Schematic” on page B-1.
Part Description
Manufacturer
Part Number
IDC header
SULLINS
GEC06DAAN
Mating Assembly
IDC socket
DIGI-KEY
S4207-ND
USB Debug Agent Connector (ZJ1)
The USB debug agent connector is the connecting point for the JTAG
USB debug agent interface. The JTAG header (ZP4) should not be used
whenever ZJ1 and its mating cable are used to communicate to the processor via CCES or VisualDSP++.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
2-21
Connectors
JTAG (ZP4)
The JTAG header is the connecting point for a JTAG in-circuit emulator
pod. When an emulator connects to the JTAG header, the USB debug
interface is disabled.
3 is missing to provide keying. Pin 3 in the mating connector
 Pin
should have a plug.
using an emulator with the EZ-KIT Lite board, follow the
 When
connection instructions provided with the emulator.
2-22
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
A ADSP-BF561 EZ-KIT LITE BILL
OF MATERIALS
The bill of materials corresponds to “ADSP-BF561 EZ-KIT Lite Schematic” on page B-1.
Ref.
Qty. Description
Reference Designator
Manufacturer
Part Number
1
1
74LVC14A
SOIC14
U47
TI
74LVC14AD
2
2
IDT74FCT3244
APY SSOP20
U13,U30
IDT
IDT74FCT3244APYG
3
1
12.288MHZ
OSC003
U16
EPSON
SG-8002CA MP
4
1
NDS8434A SO-8
U29
FAIRCHILD
NDS8434A
5
2
MT48LC16M16
A2TG-75
TSOP54
U32-33
MICRON
MT48LC16M16A2P-75
6
1
27MHZ OSC003
U17
EPSON
SG-8002CA MP
7
2
IDT2305-1DC
SOIC8
U19-20
INTEGRATED SYS
ICS9112AM-16LFT
8
1
SN74LVC1G32
SOT23-5
U10
TI
SN74LVC1G32DBVR
9
1
30MHZ OSC003
U14
EPSON
SG-8002CA MP
10
1
BF561
M29W640D
"U27"
U27
ST MICRO
M29W640DT 90N6E
11
2
FDC658P
SOT23-6
U28,U49
FAIRCHILD
FDC658P
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
A-1
A-2
Ref.
Qty. Description
Reference Designator
Manufacturer
Part Number
12
1
ADM708SARZ
SOIC8
U46
ANALOG
DEVICES
ADM708SARZ
13
1
ADP3338AKCZ33 SOT-223
VR3
ANALOG
DEVICES
ADP3338AKCZ-3.3-RL
14
1
ADP3339AKCZ5 SOT-223
VR1
ANALOG
DEVICES
ADP3339AKCZ-5-R7
15
1
ADP3336ARMZ
MSOP8
VR2
ANALOG
DEVICES
ADP3336ARMZ-REEL7
16
1
10MA
AD1580BRTZ
SOT23D
D1
ANALOG
DEVICES
AD1580BRTZ-REEL7
17
4
ADG752BRTZ
SOT23-6
U22-23,U25-26
ANALOG
DEVICES
ADG752BRTZ-REEL
18
3
AD8061ARTZ
SOT23-5
U1-3
ANALOG
DEVICES
AD8061ARTZ-R2
19
1
ADM3202ARNZ
SOIC16
U21
ANALOG
DEVICES
ADM3202ARNZ
20
8
AD8606ARZ
SOIC8
U5-7,U9,U11-12,
U18,U24
ANALOG
DEVICES
AD8606ARZ
21
1
AD1836AASZ
MQFP52
U15
ANALOG
DEVICES
AD1836AASZ
22
1
ADSP-BF561SK
BCZ MBGA256
U48
ANALOG
DEVICES
ADSP-BF561SKBCZ-6V
23
1
ADV7179KCPZ
LFCSP40
U8
ANALOG
DEVICES
ADV7179KCPZ
24
1
ADV7183BKSTZ
LQFP80
U4
ANALOG
DEVICES
ADV7183BKSTZ
25
2
ADP1864AUJZ
SOT23-6
VR5-6
ANALOG
DEVICES
ADP1864AUJZ-R7
26
5
RUBBER FOOT
M1-5
MOUSER
517-SJ-5018BK
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
ADSP-BF561 EZ-KIT Lite Bill Of Materials
Ref.
Qty. Description
Reference Designator
Manufacturer
Part Number
27
1
PWR
2.5MM_JACK
CON005
J7
SWITCHCRAFT
RAPC712X
28
1
RCA 2X2
CON013
J4
SWITCHCRAFT
PJRAS2X2S01X
29
5
MOMENTARY
SWT013
SW1,SW6-9
PANASONIC
EVQ-PAD04M
30
3
.05 45X2
CON019
J1-3
SAMTEC
SFC-145-T2-F-D-A
31
3
DIP6 SWT017
SW2,SW4,SW10
CTS
218-6LPST
32
2
RCA 3X2
CON024
J5-6
SWITCHCRAFT
PJRAS3X2S01X
33
4
DIP4 SWT018
SW3,SW5,SW11-12
ITT
TDA04HOSB1
34
1
DIP2 SWT020
SW13
C&K
CKN9064-ND
35
1
IDC 2X1
IDC2X1
P1
FCI
90726-402HLF
36
1
IDC 2X1
IDC2X1
JP2
FCI
90726-402HLF
37
2
IDC 3X1
IDC3X1
JP1,JP3
FCI
90726-403HLF
38
1
IDC 10X2
IDC10X2
P3
BURG-FCI
54102-T08-10LF
39
4
IDC
2PIN_JUMPER_
SHORT
SJ1-4
DIGI-KEY
S9001-ND
40
1
DB9 9PIN
DB9M
P2
TYCO
5747250-4
41
1
IDC 6X2
IDC6X2
P5
FCI
68737-412HLF
42
1
5A RESETABLE
FUS005
F1
MOUSER
650-RGEF500
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
A-3
A-4
Ref.
Qty. Description
Reference Designator
Manufacturer
Part Number
43
14
0 1/4W 5% 1206
R43-44,R55,R71,
R73,R83,R133,
R159,R163,R223225,R247,R257
KOA
0.0ECTRk7372
BTTED
44
16
YELLOW
LED001
LED5-20
PANASONIC
LN1461C
45
12
330PF 50V 5%
0805
C82,C84,C86,
C92-100
AVX
08055A331JAT
46
48
0.01UF 100V
10% 0805
C3,C5,C28,C41,
C49,C69-70,C74-75,
C101,C112-114,
C127,C134,C136138,C140-141,C146,
C149-150,C154,
C156-157,C165-166,
C168,C173-174,
C176,C181-182,
C185-188,C190,
C192-194,C200-203,
C249,C256
AVX
08051C103KAT2A
47
8
0.22UF 25V 10%
0805
C104,C106-108,
C125,C129,C143,
C162
AVX
08053C224KAT2A
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
ADSP-BF561 EZ-KIT Lite Bill Of Materials
Ref.
Qty. Description
Reference Designator
Manufacturer
Part Number
48
69
0.1UF 50V 10%
0805
C1-2,C4,C12,C1920,C22,C27,C29-30,
C35,C37,C48,C5152,C54-60,C65-66,
C71,C73,C83,C85,
C87-91,C102,C109111,C115,C122-124,
C126,C131-132,
C135,C139,C145,
C147-148,C151-152,
C155,C158-159,
C164,C167,C171172,C175,C177-179,
C183-184,C189,
C191,C196,
C198-199
AVX
08055C104KAT
49
10
1000PF 50V 5%
0805
C23,C25,C33,C36,
C38-40,C67-68,
C133
AVX
08055A102JAT2A
50
3
10UF 16V 10%
C
CT17,CT23-24
SPRAGUE
293D106X9016C2TE3
51
43
10K 1/10W 5%
0805
R2,R7,R11-12,R14,
R24,R42,R45-47,
R52,R57,R85,R8788,R98,R131,R143,
R158,R160-162,
R167-170,R174-177,
R181-183,R189-190,
R196,R229,R239,
R246,R248-251
VISHAY
CRCW080510K0
JNEA
52
9
33 1/10W 5%
0805
R39,R41,R59-61,
R165-166,R171-172
VISHAY
CRCW080533R0
JNEA
53
2
4.7K 1/10W 5%
0805
R86,R90
VISHAY
CRCW08054K70
JNEA
54
1
1.5K 1/10W 5%
0805
R1
VISHAY
CRCW08051K50
FKEA
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
A-5
A-6
Ref.
Qty. Description
Reference Designator
Manufacturer
Part Number
55
1
1.2K 1/8W 5%
1206
R23
VISHAY
CRCW12061K20
JNEA
56
6
49.9K 1/8W 1%
1206
R108-113
VISHAY
CRCW120649K9
FKEA
57
12
100PF 100V 5%
1206
C6-11,C26,C34,
C61-63,C72
AVX
12061A101JAT2A
58
6
10UF 16V 10% B
CT1-4,CT15-16
AVX
TAJB106K016R
59
4
100 1/10W 5%
0805
R242-245
VISHAY
CRCW0805100
RJNEA
60
6
220PF 50V 10%
1206
C13-18
AVX
12061A221JAT2A
61
4
600 100MHZ
200MA 0603
FER18-21
DIGI-KEY
490-1014-2-ND
62
1
2A S2A
DO-214AA
D7
VISHAY
S2A-E3
63
12
600 100MHZ
500MA 1206
FER2-4,FER6,FER812,FER14-16
STEWARD
HZ1206B601R-10
64
4
237.0 1/8W 1%
1206
R25-26,R53-54
VISHAY
CRCW1206237
RFKEA
65
4
750.0K 1/8W 1%
1206
R132,R156,R164,
R173
VISHAY
CRCW1206750
KFKEA
66
16
5.76K 1/8W 1%
1206
R8,R15-16,R40,R4950,R58,R62-64,R6970,R121-124
VISHAY
CRCW12065K76
FKEA
67
6
11.0K 1/8W 1%
1206
R144-149
VISHAY
CRCW120611K0
FKEA
68
8
120PF 50V 5%
1206
C103,C105,C128,
C130,C142,C144,
C161,C163
AVX
12065A121JAT2A
69
12
75 1/8W 5%
1206
R4-6,R100-102,
R104-105,R107,
R114,R134-135
VISHAY
CRCW120675R0
JNEA
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
ADSP-BF561 EZ-KIT Lite Bill Of Materials
Ref.
Qty. Description
Reference Designator
Manufacturer
Part Number
70
1
68UF 6.3V
20% D
CT22
AVX
TAJD686K016R
71
6
680PF 50V 1%
0805
C116-121
AVX
08055A681FAT2A
72
5
10UF 25V
+80-20% 1210
C31,C47,C50,C195,
C197
DIGI-KEY
587-1393-2-ND
73
6
2.74K 1/8W 1%
1206
R150-155
VISHAY
CRCW12062K74
FKEA
74
12
5.49K 1/8W 1%
1206
R17-22,R27,R30-31,
R34-35,R38
VISHAY
CRCW12065K49
FKEA
75
6
3.32K 1/8W 1%
1206
R137-142
VISHAY
CRCW12063K32
FKEA
76
6
1.65K 1/8W 1%
1206
R28-29,R32-33,R3637
VISHAY
CRCW12061K65
FKEA
77
10
10UF 16V 20%
CAP002
CT5-14
PANASONIC
EEE1CA100SR
78
1
10UH 20%
IND001
L11
TDK
445-2014-1-ND
79
6
0 1/10W 5%
0805
R66,R99,R103,
R106,R178,R192
VISHAY
CRCW08050000
Z0EA
80
1
190 100MHZ 5A
FER002
FER22
MURATA
DLW5BSN191SQ2
81
4
22 1/10W 5%
0805
R67-68,R187-188
VISHAY
541-22ATR-ND
82
6
0.68UH 10%
0805
L1-4,L6,L8
MURATA
LQM21NNR68K10D
83
1
.082UF 50V 5%
0805
C64
AVX
08055C823JAT2A
84
1
1A ZHCS1000
SOT23-312
D5
ZETEX
ZHCS1000TA pb-free
85
3
2.2UH 10% 0805
L5,L7,L9
DIGI-KEY
490-1119-2-ND
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
A-7
A-8
Ref.
Qty. Description
Reference Designator
Manufacturer
Part Number
86
3
1UF 10V 10%
0805
C21,C24,C32
AVX
0805ZC105KAT2A
87
1
76.8K 1/10W 1%
1206
R48
VISHAY
CRCW120676K8
FKEA
88
1
147.0K 1/10W
1% 1206
R56
VISHAY
CRCW1206147
KFKEA
89
10
10 62.5MW 5%
RNS006
RN1,RN4-12
PANASONIC
EXB-38V100JV
90
2
68PF 50V 5%
0603
C160,C257
AVX
06035A680JAT2A
91
2
470PF 50V 5%
0603
C153,C258
AVX
06033A471JAT2A
92
2
0 1/10W 5%
0603
R74,R254
PHYCOMP
232270296001L
93
2
24.9K 1/10W 1%
0603
R72,R256
DIGI-KEY
311-24.9KHTR-ND
94
2
10UF 16V 10%
1210
C169,C260
AVX
1210YD106KAT2A
95
1
680 1/8W 5%
1206
R119
VISHAY
CRCW1206680RFNEA
96
1
150.0 1/8W 1%
1206
R3
VISHAY
CRCW1206150RFKEA
97
1
GREEN LED001
LED1
PANASONIC
LN1361CTR
98
1
RED LED001
LED2
PANASONIC
LN1261CTR
99
2
1000PF 50V 5%
1206
C43,C46
AVX
12065A102JAT2A
100
6
2200PF 50V 5%
1206
C76-81
AVX
12065A222JAT050
101
6
1K 1/8W 5%
1206
R10,R115-118,R136
VISHAY
CRCW12061K00
FKEA
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
ADSP-BF561 EZ-KIT Lite Bill Of Materials
Ref.
Qty. Description
Reference Designator
Manufacturer
Part Number
102
2
100K 1/8W 5%
1206
R9,R13
VISHAY
CRCW1206100K
FKEA
103
17
270 1/8W 5%
1206
R120,R213-220,
R230-237
VISHAY
CRCW1206270
RJNEA
104
6
604.0 1/8W 1%
1206
R125-130
VISHAY
CRCW1206604R
FKEA
105
4
1UF 20V 20% A
CT25-28
AVX
TAJA105K020R
106
1
255.0K 1/10W
1% 0603
R89
VISHAY
CRCW06032553FK
107
2
80.6K 1/10W 1%
0603
R80,R255
DIGI-KEY
311-80.6KHRCT-ND
108
2
6.8UH 25%
IND009
L10,L12
DIGI-KEY
308-1328-1-ND
109
2
4A SSB43L
DO-214AA
D4,D8
VISHAY
SSB43L
110
2
5A
MBRS540T3G
SMC
D2-3
ON SEMI
MBRS540T3G
111
1
0.027 1/2W 1%
1206
R79
SUSUMU
RL1632T-R027-F-N
112
1
54.9K 1/10W 1%
0603
R252
VISHAY
CRCW060354K9
FKEA
113
1
0.047 1/2W 1%
1206
R253
SUSUMU
RL1632S-R047-F
114
2
100UF 6.3V
20%C
CT19,CT29
SANYO
6TPB100MC
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
A-9
A-10
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
A
B
C
D
1
1
2
2
ADSP-BF561 EZ-KIT Lite
Schematic
3
3
ANALOG
DEVICES
4
Board No.
C
Date
A
B
C
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF561 EZ-KIT LITE
TITLE
Title
Size
20 Cotton Road
Rev
A0185-2003
2.3
Sheet
11-7-2007_15:11
D
1
of
14
A
B
C
D
U48
D0
D[31:0]
1
B16
D1
C15
D2
E12
D3
C16
D4
E14
D5
D15
D6
D16
D7
E15
D8
F13
D9
F15
D10
F12
D11
F16
D12
F14
3.3V
D13
G15
D14
G13
D15
G12
A[25:2]_S
D0
A2
D1
A3
D2
A4
D3
A5
D4
A6
D5
A7
D6
A8
D7
A9
D8
A10
D9
A11
D10
A12
D11
A13
D12
A14
D13
A15
D14
A16
D15
A17
R42
10K
0805
D16
R60
33
0805
U14
1
OE
OUT
3
H12
D17
H15
D18
H13
D19
H16
D20
H14
D21
J15
OSC_30MHZ
30MHZ
OSC003
R51
DNP
0805
EXT_DSP_CLK
D22
J13
D23
J16
D24
K14
D25
K15
D26
K13
D27
L15
3.3V
2
R160
10K
0805
R196
10K
0805
D28
K12
D29
L16
D30
D31
J12
M15
D16
A18
D17
A19
D18
A20
D19
A21
D20
A22
D21
A23
D22
A24
D23
A25
B12
ARDY
F1
3.3V
G1
D27
D28
D29
D30
SDQM0/ ABE0
SDQM1/ ABE1
SDQM2/ ABE2
SDQM3/ ABE3
BR
BGH
ARDY
ARE
RESET
CLKIN
AMS1
XTAL
AMS2
SRAS
SCAS
R170
10K
0805
SWE
SA10
SMS0
3
DSP_BYPASS
BMODE0
G4
M10
BMODE1
N10
BYPASS
SMS1
SMS2
BMODE0
SMS3
BMODE1
SCKE
P11
NMI0
NMI1
R9
A5_S
B14
A6_S
C14
A7_S
A2_S
1
F11
A8_S
A3_S
2
RN4
D7
A9_S
A4_S
3
A6
A10_S
A5_S
4
C6
A11_S
A12_S
E6
A13_S
A5
A14_S
A6_S
1
E5
A15_S
A7_S
2
B4
A16_S
A8_S
3
A17_S
B3
A18_S
A9_S
4
A3
A20_S
F5
A21_S
A10_S
1
B2
A22_S
A11_S
2
D4
A23_S
A12_S
3
C3
A25_S
R2B
R3A
R3B
R4A
R4B
1
BMODE0
2
BMODE1
ON
ON
RESERVED
OFF
ON
8-BIT FLASH
ON
OFF
SPI SROM 8-BIT
OFF
OFF
SPI SROM 16-BIT
A13_S
NMI0
SCLK0
NMI1
SCLK1
6
A4
5
A5
R1A
R1B
R2A
R2B
R3A
R3B
R4A
R4B
8
A6
7
A7
A14_S
1
A15_S
2
A16_S
3
A17_S
4
R1A
R2A
R3A
R4A
4
R1B
R2B
R3B
R4B
8
A14
7
A15
6
A16
5
A17
8
A18
7
A19
6
A20
5
A21
8
A22
7
A23
6
A24
5
A25
E11
ABE0_S
1
B13
ABE1_S
2
A14
ABE2_S
3
A15
ABE3_S
4
A13
6
A8
5
A18_S
1
A19_S
2
A20_S
3
A21_S
4
R1A
R2A
A9
R3A
R4A
R1B
R2B
R3B
R4B
10
RNS006
R1A
R1B
R2A
R2B
R3A
R3B
R4A
R4B
8
A10
7
A11
6
A12
RN8
5
A22_S
1
A23_S
2
A24_S
3
A25_S
4
R1A
R2A
A13
R3A
R4A
R1B
R2B
R3B
R4B
A[25:2]
R1A
R1B
R2A
R2B
R3A
R3B
R4A
R4B
8
C12
7
ABE1
6
ABE2
5
ABE3
BGH
C7
AOE
B8
ARE
A8
AWE
C8
AMS0
B7
AMS1
E7
AMS2
A7
AMS3
RN10
C10
SRAS_S
1
D10
SCAS_S
2
E10
SWE_S
3
D11
SA10_S
4
E9
SMS0_S
B9
SMS1_S
C9
SMS2_S
A10
SMS3_S
1
2
B10
A11
SCKE
3
SCLK0_S
4
A12
R1A
R1B
R2A
R2B
R3A
R3B
R4A
R4B
8
SRAS
7
SCAS
6
SWE
5
SA10
10
RNS006
RN9
SCLK1_S
3
R1A
R1B
R2A
R2B
R3A
R3B
R4A
R4B
8
SMS0
7
SMS1
6
SMS2
5
SMS3
R187
22
0805
SCLK0
3.3V
U20
CLKOUT
CLK1
DEFAULT
CLK2
6
VDD
4
GND
CLK3
CLK4
R68
22
0805
8
3
CLK_OUT_EXP1
2
R67
22
0805
5
CLK_OUT_EXP2
7
R65
22
0805
IDT2305-1DC
SOIC8
SW3
ON
1
3
6
4
5
2
3
ANALOG
DEVICES
8
7
DNP
4
Title
DIP4
SWT018
Size
Date
B
C
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF561 EZ-KIT LITE
DSP - EXT MEM INTERFACE
Board No.
C
A
2
ABE0
10
RNS006
BG
1
REF
2
1
RN6
R176
10K
0805
BOOT MODE
4
RN12
10
RNS006
R188
22
0805
1
A3
RN7
ADSP-BF561SKBCZ
MBGA256
SW3: BOOT MODE/BYPASS Select
(Default = OFF, ON, ON, OFF)
7
10
RNS006
10
RNS006
R169
10K
0805
A2
10
RNS006
A19_S
A24_S
R2A
8
RN5
C4
A2
R1B
10
RNS006
B5
F6
R1A
D31
AMS3
R168
10K
0805
G10
RN11
C42
0.1UF
0805
DNP
R167
10K
0805
A4_S
D26
AMS0
DSPCK_30MHZ
A3_S
B15
10
RNS006
AWE
F3
RESET
G11
D25
AOE
D9
A2_S
D24
BG
BR
D13
Rev
A0185-2003
2.3
Sheet
11-7-2007_15:11
D
2
of
14
A
B
C
D
U48
P15
RSCLK0
R16
RFS0
L12
DR0PRI
P16
DR0SEC
N16
TSCLK0
L13
TFS0
1
RSCLK0/PF28
M16
DT0PRI
RFS0/PF19
PF14
DR0PRI
PF13
DR0SEC/PF20
PF12
TSCLK0/PF29
PF11
TFS0/PF16
PF10
DT0PRI/PF18
N15
DT0SEC
PF15/TMRXCLK
PF9
DT0SEC/PF17
PF8
PF7/SPIS7/TMR7
When designing your JTAG interface please refer to the
P13
RSCLK1
Engineer to Engineer Note EE-68 which can be found at
N13
RFS1
http://www.analog.com
M12
DR1PRI
T14
DR1SEC
R14
TSCLK1
R15
DT1PRI
been omitted from this schematic.
T15
DT1SEC
PF5/SPIS5/TMR5
DR1PRI
PF4/SPIS4/TMR4
DR1SEC/PF25
PF3/SPIS3/TMR3
TSCLK1/PF31
PF2/SPIS2/TMR2
TFS1/PF21
PF1/SPIS1/TMR1
DTIPRI/PF23
PF0/SPISS/TMR0
PF14
N8
PF13
T7
PF12
P7
PF11
PF[15:0]
RN1
R7
PF15
1
PF14
2
PF13
3
PF10
N6
PF9
R1A
R2A
R1B
R2B
R3A
R3B
PF7
R4A
R4B
T5
PF6
10
RNS006
P6
8
AD1836_RESET
7
PROGR. FLAG
VENC_RESET
6
1
VDEC_RESET
AD1836 CODEC RESET
PF14
ADV7179 VIDEO ENCODER RESET
PF13
ADV7183A VIDEO DECODER RESET
PF5
PF12
GENERAL PURPOSE
R5
PF4
PF11
GENERAL PURPOSE
M6
PF3
PF10
GENERAL PURPOSE
T4
PF2
PF8
M7
4
5
PF9
GENERAL PURPOSE
4
PF1
PF8
GENERAL PURPOSE / PUSH BUTTON STATUS INPUT
3
PF0
PF7
GENERAL PURPOSE / PUSH BUTTON STATUS INPUT
PF6
GENERAL PURPOSE / PUSH BUTTON STATUS INPUT/ UART SIGNAL
PF5
GENERAL PURPOSE / PUSH BUTTON STATUS INPUT/ UART SIGNAL
PF4
GENERAL PURPOSE / AD1836 LATCH SIGNAL
PF3
GENERAL PURPOSE / VIDEO DECODER FIELD
PF2
GENERAL PURPOSE / VIDEO DECODER OUTPUT ENABLE
PF1
GENERAL PURPOSE / I2C SERIAL DATA/SPISEL1
PF0
GENERAL PURPOSE / I2C SERIAL CLOCK/SPISS
SW13
N5
SPIS1
1
P4
SPISS
2
DIP2
SWT020
DT1SEC/PF22
3.3V
T13
RX
TX
3.3V
R10
2
1
TDI
DA_EMULATOR_SELECT
3
4
EMULATOR_EMU
5
6
EMULATOR_TMS
7
8
EMULATOR_TCK
9
10
EMULATOR_TRST
11
12
EMULATOR_TDI
13
14
T10
TMS
2
EMULATOR_TDO
DA_EMULATOR_EMU
2
TRST
EMU
R11
EMU
TDI
DA_EMULATOR_TCK
TDO
P5
TDO
DA_EMULATOR_TRST
1
2
3
4
5
6
7
8
9
10
11
12
MOSI
EMU
DA_EMULATOR_TDI
DA_EMULATOR_TDO
DA_GP0
DA_GP1
EMU
R86
4.7K
0805
SPISS
SCK
ADSP-BF561SKBCZ
MBGA256
RESET
DA_GP2
SPIS1
DA_GP3
MISO
SHGND
DA_SOFT_RESET
GND
DA_SOFT_RESET
TDO
DA_EMULATOR_TMS
IDC7X2
RESET
N9
TCK
P10
TRST
TDO
TMS
T9
TCK
R90
4.7K
0805
SCK
3V
ZP4
3.3V
MISO
M11
SCK
SW13: SPIS1/SPISS Select
T11
MOSI
R12
MISO
SLEEP
TX/PF26
N11
MOSI
R239
10K
0805
RX/PF27
R13
FUNCTION
PF15
R6
2
All USB interface circuitry is considered proprietary and has
RFS1/PF24
R8
ON
TFS1
PF6/SPIS6/TMR6
PF15
1
P14
RSCLK1/PF30
P8
IDC6X2
DEBUG_AGENT
DSP JTAG HEADER
SPI
SHGND
DSP_VDD_EXT
DSP_VDD_INT
U48
A1
A16
A4
A9
B11
B6
D12
E16
F2
G16
G3
J6
K16
K6
L10
L5
M14
T1
T12
T16
T3
T6
T8
3
C11
C13
C5
D14
D5
D6
D8
E1
E13
F10
F8
G14
G2
G6
G7
G8
H1
H10
H2
H8
H9
4
VDDEXT1
VDDEXT2
VDDEXT3
VDDEXT4
VDDEXT5
VDDEXT6
VDDEXT7
VDDEXT8
VDDEXT9
VDDEXT10
VDDEXT11
VDDEXT12
VDDEXT13
VDDEXT14
VDDEXT15
VDDEXT16
VDDEXT17
VDDEXT18
VDDEXT19
VDDEXT20
VDDEXT21
VDDEXT22
VDDEXT23
VDDINT1
VDDINT2
VDDINT3
VDDINT4
VDDINT5
VDDINT6
VDDINT7
VDDINT8
VDDINT9
VDDINT10
VDDINT11
VDDINT12
VDDINT13
VDDINT14
R87
10K
0805
VROUT2
GND41
GND40
GND39
GND38
GND37
GND36
GND35
GND34
GND33
GND32
GND31
GND30
GND29
GND28
GND27
GND26
GND25
GND24
GND23
GND22
J1
R85
10K
0805
3
SPORT1
P3
RFS1
RSCLK1
DR1PRI
DR1SEC
VROUT1
NC0
NC1
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
R88
10K
0805
E8
F7
F9
G9
H11
H6
H7
J10
J8
J9
K11
K8
L8
M8
VROUT
J2
M5
M13
P9
P5
P2
P12
N7
N14
N12
M9
M4
L9
L7
L3
L14
L11
K9
K7
K10
J7
J14
J11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
ANALOG
DEVICES
Title
Size
DT1PRI
DT1SEC
Date
C
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF561 EZ-KIT LITE
DSP - PROGR. FLAGS, SPI
Board No.
C
B
TSCLK1
IDC10X2
ADSP-BF561SKBCZ
MBGA256
A
TFS1
Rev
A0185-2003
2.3
Sheet
11-7-2007_15:11
D
3
of
14
A
B
C
D
SW5: PPI CLK Routing Select
(Default: 1 = OFF, 2 = ON, 3 = ON, 4 = ON)
1 or 3
PPIxCLK_SEL0
2 or 4
PPIxCLK_SEL1
PPIxCLK
ON
ON
PPI_27MHZ_CLK
OFF
ON
VDEC_CLKOUT
X
OFF
EXPANSION_CLK
3.3V
3.3V
R166
33
0805
VDEC_27MHZ_CLK
R165
33
0805
1
R162
10K
0805
U22
3
R174
10K
0805
VENC_27MHZ_CLK
3.3V
R175
10K
0805
R182
10K
0805
R181
10K
0805
R171
33
0805
R59
33
0805
U17
1
OE
OUT
3
U23
1
1
R66
0
0805
3
6
1
PPI0_CLK
6
4
EXT_27MHZ_CLK
U19
4
OSC_27M
OSC27M
1
REF
CLKOUT
CLK1
27MHZ
OSC003
CLK2
6
VDD
CLK3
4
GND
CLK4
8
ADG752BRTZ
SOT23-6
3
ADG752BRTZ
SOT23-6
EXP_PPI0_CLK
2
R172
33
0805
5
U26
7
PPI_27MHZ_CLK
3
U25
1
IDT2305-1DC
SOIC8
2
2
6
VDEC_CLKOUT
ON
1
SW5
1
R178
0
0805
3
1
8
PPI1_CLK
6
PPI0CLK_SEL0
4
7
PPI0CLK_SEL1
6
4
5
3
3
4
ADG752BRTZ
SOT23-6
PPI1CLK_SEL0
4
ADG752BRTZ
SOT23-6
PPI1CLK_SEL1
DIP4
SWT018
EXP_PPI1_CLK
U48
2
PPI0_D[15:0]
PPI0_D15
D2
PPI0_D14
G5
PPI0_D13
D1
PPI0_D12
E3
PPI0_D11
E2
PPI0_D10
F4
PPI0_D9
H3
PPI0_D8
K3
PPI0_D7
H4
PPI0_D6
K1
H5
PPI0_D4
K2
PPI0_D3
J4
PPI0_D2
J3
PPI0_D1
J5
PPI0_D0
L1
3
PPI0_D13/PF45
PPI1_D13/PF37
PPI0_D12/PF44
PPI1_D12/PF36
PPI0_D11/PF43
PPI1_D11/PF35
PPI0_D10/PF42
PPI1_D10/PF34
PPI0_D9/PF41
PPI1_D9/PF33
PPI1_D8/PF32
PPI0_D7
PPI1_D7
PPI0_D6
PPI1_D6
PPI0_D5
PPI1_D5
PPI0_D4
PPI1_D4
PPI0_D3
PPI1_D3
PPI0_D2
PPI1_D2
PPI1_D1
PPI1_D0
PPI0_CLK
C1
D3
PPI0_SYNC3
PPI1_D14/PF38
PPI0_D0
E4
PPI0_SYNC2
PPI0_D14/PF46
PPI0_D1
C2
PPI0_SYNC1
PPI1_D15/PF39
PPI0_D8/PF40
PPI0_D5
PPI0_CLK
PPI0_D15/PF47
PPI1_CLK
PPI0_SYN1/TMR8
PPI1_SYN1/TMR10
PPI0_SYN2/TMR9
PPI1_SYN2/TMR11
PPI0_SYN3
PPI1_SYN3
M1
PPI1_D15
K5
PPI1_D14
M2
PPI1_D13
N1
PPI1_D12
L6
PPI1_D11
PPI1_D8
2
N2
PPI1_D10
PPI1_D9
4
M3
PPI1_D9
PPI1_D10
6
P1
PPI1_D8
PPI1_D11
8
R1
PPI1_D7
PPI1_D12
11
R2
PPI1_D6
PPI1_D13
13
PPI1_D14
15
PPI1_D15
17
2
PPI1_D[15:0]
U13
1A1
1A2
1A3
1A4
2A1
2A2
P3
PPI1_D5
T2
PPI1_D4
N3
PPI1_D3
R3
PPI1_D2
1
N4
PPI1_D1
19
R4
PPI1_D0
2A3
2A4
18
1Y1
16
1Y2
14
1Y3
12
1Y4
9
2Y1
7
2Y2
5
2Y3
3
2Y4
OE1
LED20
YELLOW
LED001
OE2
LED19
YELLOW
LED001
LED18
YELLOW
LED001
LED17
YELLOW
LED001
LED16
YELLOW
LED001
LED15
YELLOW
LED001
LED14
YELLOW
LED001
LED13
YELLOW
LED001
IDT74FCT3244APY
SSOP20
B1
PPI1_CLK
K4
R237
270
1206
PPI1_SYNC1
L2
R236
270
1206
R235
270
1206
R234
270
1206
R233
270
1206
R232
270
1206
R231
270
1206
R230
270
1206
PPI1_SYNC2
L4
3
PPI1_SYNC3
ADSP-BF561SKBCZ
MBGA256
U30
PPI0_D8
2
PPI0_D9
4
PPI0_D10
6
PPI0_D11
8
PPI0_D12
11
PPI0_D13
13
PPI0_D14
15
PPI0_D15
17
1
19
18
1A1
1Y1
1A2
1Y2
1A3
1Y3
1A4
1Y4
2A1
2Y1
2A2
2Y2
2A3
2Y3
2A4
2Y4
16
14
12
9
7
5
3
OE1
OE2
LED12
YELLOW
LED001
LED11
YELLOW
LED001
LED10
YELLOW
LED001
LED9
YELLOW
LED001
LED8
YELLOW
LED001
LED7
YELLOW
LED001
LED6
YELLOW
LED001
LED5
YELLOW
LED001
ANALOG
DEVICES
IDT74FCT3244APY
SSOP20
4
R220
270
1206
R219
270
1206
R218
270
1206
R217
270
1206
R216
270
1206
R215
270
1206
R214
270
1206
R213
270
1206
Board No.
C
Date
A
B
C
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF561 EZ-KIT LITE
DSP - PPI0 AND PPI1
Title
Size
20 Cotton Road
Rev
A0185-2003
2.3
Sheet
11-7-2007_15:11
D
4
of
14
A
B
C
FLASH A (8MB)
D
SDRAM 64MB
(256Mb x 2 Chips)
4M x 16
D[31:0]
1
1
U32
A[25:2]
U27
25
ABE3
A2
24
A3
23
A4
22
A5
21
A6
20
A7
19
A8
A9
8
A10
7
A11
6
A12
5
A13
3.3V
2
R190
10K
0805
R177
10K
0805
4
A14
3
A15
2
A16
1
A17
48
A18
17
A19
16
A20
R189
10K
0805
18
9
A21
10
A22
13
26
AMS0
28
AOE
11
AWE
47
FLASH_WP
14
FLASH_RP
12
3.3V
A0
A1
A2
VCC
37
A3
A4
D0
A5
D1
A6
D2
A7
D3
A8
D4
A9
D5
A10
D6
A11
D7
A12
D8
A13
D9
A14
D10
A15
D11
A16
D12
A17
D13
A18
D14
A19
D15
29
D0
31
D1
33
D2
35
D3
38
D4
40
D5
42
D6
44
D7
30
D8
32
D9
34
D10
36
D11
23
A3
24
A4
25
A5
26
A6
29
A7
30
A8
31
A9
32
A10
33
A11
34
SCAS
41
D13
SRAS
43
D14
45
D15
R183
10K
0805
A20
D4
10
D5
11
D6
13
D7
42
D8
44
D9
DQ7
A8
DQ8
A9
DQ9
45
DQ10
47
DQ11
48
DQ12
50
DQ13
51
DQ14
53
DQ15
A10
A11
A12_NC
21
8
DQ6
A7
A19
D3
DQ5
A6
20
D2
7
DQ4
A5
A18
5
DQ3
A4
36
D1
DQ2
A3
A14
D0
4
DQ1
A2
35
2
DQ0
A1
A13
BA0
BA1
16
SWE
3.3V
A0
22
SA10
D12
39
A2
D10
D11
D12
D13
D14
D15
19
CS
37
CKE
38
CLK
WE
17
CAS
18
RAS
SMS0
2
SCKE
SCLK0
15
ABE0
DQML
39
ABE1
DQMH
A21
CE
RDY
15
MT48LC16M16A2TG-75
TSOP54
FLASH_RDY
OE
U33
WE
BYTE
VSS2
WP/VPP
VSS1
46
A2
23
A3
24
A4
25
A5
26
A6
29
A7
30
A8
31
A0
27
RP
M29W640D
TSOP48
A1
34
A7
36
A11
A12_NC
A18
20
A19
21
D21
11
D22
13
D23
42
D24
44
D25
45
DQ10
47
DQ11
48
DQ12
50
DQ13
51
DQ14
53
DQ15
D26
DQ9
A10
A14
D20
10
DQ8
A9
35
8
DQ7
A8
A13
D19
DQ6
22
3
D18
7
DQ5
A6
A11
5
DQ4
A5
33
D17
DQ3
A4
32
4
DQ2
A3
A9
D16
DQ1
A2
A10
2
DQ0
BA0
BA1
3
D27
D28
D29
D30
D31
Memory Map
16
START
0x0000 0000
0x2000 0000
END
0x03FF FFFF
0x207F FFFF
BANK
SDRAM Bank 0
ASYNC Memory Bank 0
19
CS
37
CKE
38
CLK
WE
DEVICE
17
CAS
18
64MB SDRAM
8MB FLASH
RAS
ABE2
ABE3
15
DQML
39
DQMH
MT48LC16M16A2TG-75
TSOP54
ANALOG
DEVICES
4
Title
Size
A
B
C
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF561 EZ-KIT LITE
MEMORY - FLASH & SDRAM
Board No.
C
Date
20 Cotton Road
Rev
A0185-2003
2.3
Sheet
11-7-2007_15:11
D
5
of
14
A
B
C
D
ADC2
ADC1
R61
33
0805
U16
1
OE
1
DAC1
R161
10K
0805
DAC2
DAC3
3.3V
LEFT (WHITE)
OUT
3
AD1836_CLK
RIGHT (RED)
1
12.288MHZ
OSC003
OUT (J4)
R18
5.49K
1206
IN (J5)
R145
11.0K
1206
C7
100PF
1206
R138
3.32K
1206
OUT1R-
C96
330PF
0805
3.3V
U5
6
7
DAC1 RIGHT
5
C117
680PF
0805
R30
5.49K
1206
R57
10K
0805
AD8606ARZ
SOIC8
R29
1.65K
1206
R126
604.0
1206
OUT1R+
AUDIO CODEC
J5
CT8
10UF
CAP002
CON024
DAC1_RIGHT 7
U15
SW12
1
ON
1
DR0PRI
7
48
3
6
44
4
5
43
3
RFS0
4
RSCLK0
47
2
2
DR0SEC
8
8
ASDATA1
OUT1L+
OUT1L+
ASDATA2
9
OUT1L-
OUT1L-
31
ABCLK
OUT1R+
OUT1R+
30
OUT1R45
AD1836_CLK
OUT1R-
6
CLATCH
51
SCK
ADC1 LEFT
R46
10K
0805
R45
10K
0805
ADC1 RIGHT
IN1L+
OUT3L+
OUT3L+
IN1L-
5
OUT3L-
OUT3L-
OUT2R+
32
OUT2R-
4
35
IN1R+
19
IN1R-
2
DAC2 LEFT
AGND
33
OUT2R-
18
IN1R+
OUT2L-
OUT2R+
17
IN1L-
OUT2L+
7
OUT2L-
COUT
16
IN1L+
R47
10K
0805
OUT2L+
CDATA
49
MISO
DAC1 RIGHT
CCLK
2
MOSI
9
R109
49.9K
1206
C77
2200PF
1206
MCLK
50
PF4
C14
220PF
1206
ALRCLK
DIP4
SWT018
2
R151
2.74K
1206
DAC1 LEFT
OUT3R+
OUT3R+
34
IN1R-
OUT3R-
OUT3R-
DAC2 RIGHT
DAC3 LEFT
R17
5.49K
1206
R144
11.0K
1206
DAC3 RIGHT
C6
100PF
1206
R137
3.32K
1206
OUT1L20
IN2L+/CL2/CL2
21
ADC2 LEFT
DSDATA2
NC/IN2L1/IN2L+
DSDATA3
NC/IN2L2/IN2L-
DLRCLK
23
IN2L2
IN2R2
ADC2 RIGHT IN2R1
3
42
TSCLK0
26
IN2R-/CR1/CR1
27
R159
0
1206
3
C116
680PF
0805
R27
5.49K
1206
AD8606ARZ
SOIC8
R28
1.65K
1206
C38
1000PF
0805
C39
1000PF
0805
3
CON024
DAC1_LEFT 8
CT16
10UF
B
C124
0.1UF
0805
CT15
10UF
B
C123
0.1UF
0805
R150
2.74K
1206
C13
220PF
1206
9
3
C133
1000PF
0805
R108
49.9K
1206
C76
2200PF
1206
AD1836AASZ
MQFP52
C40
1000PF
0805
J5
CT7
10UF
CAP002
IN2R+/CR2/CR2
PD/RST
R158
10K
0805
R125
604.0
1206
OUT1L+
3
AD1836_RESET
DAC1 LEFT
13
FILTR
12
FILTD
NC/IN2R1/IN2R+
U5
2
1
TFS0
37
NC/IN2R2/IN2R-
25
C95
330PF
0805
DT0SEC
36
DBCLK
24
DT0PRI
41
IN2L-/CL1/CL1
22
IN2L1
DSDATA1
38
AD8606ARZ
U12
1
AD1836_VREF
AGND
2
SOIC8
R43
0
1206
R55
0
1206
AGND
SOIC8
AD8606ARZ
5
AGND
7
SW10: Audio Loopback
For Test Purposes
Default = All Off
6
ON
11
3
10
4
9
5
8
6
7
3
ADC2_LEFT
4
ADC2_RIGHT
12
2
2
ADC1_RIGHT
1
ADC1_LEFT
4
R44
0
1206
R71
0
1206
SW10
1
U12
ANALOG
DEVICES
DAC1_LEFT
DAC1_RIGHT
Nashua, NH 03063
4
PH: 1-800-ANALOGD
DAC2_LEFT
5
6
ADSP-BF561 EZ-KIT LITE
AUDIO CODEC
Title
DAC2_RIGHT
DAC3_LEFT
AGND
DAC3_RIGHT
Size
DIP6
SWT017
Board No.
C
Date
A
20 Cotton Road
B
C
Rev
A0185-2003
2.3
Sheet
11-7-2007_15:11
D
6
of
14
A
B
C
D
1
1
R19
5.49K
1206
R146
11.0K
1206
C8
100PF
1206
R22
5.49K
1206
R139
3.32K
1206
OUT2R-
R149
11.0K
1206
C97
330PF
0805
2
C100
330PF
0805
3
R31
5.49K
1206
C118
680PF
0805
AD8606ARZ
SOIC8
R32
1.65K
1206
R142
3.32K
1206
OUT3R-
U6
1
DAC2 RIGHT
C11
100PF
1206
6
U7
7
DAC3 RIGHT
R128
604.0
1206
5
CT10
10UF
CAP002
OUT2R+
J5
CON024
DAC2_RIGHT
R38
5.49K
1206
4
C121
680PF
0805
AD8606ARZ
SOIC8
R37
1.65K
1206
R130
604.0
1206
OUT3R+
R152
2.74K
1206
C15
220PF
1206
CT12
10UF
CAP002
J5
CON024
6
AD1836_VREF
DAC3_RIGHT 1
R111
49.9K
1206
C79
2200PF
1206
R155
2.74K
1206
C18
220PF
1206
3
R113
49.9K
1206
C81
2200PF
1206
2
2
AGND
AGND
R20
5.49K
1206
R147
11.0K
1206
C9
100PF
1206
R21
5.49K
1206
R140
3.32K
1206
R148
11.0K
1206
OUT2L-
R141
3.32K
1206
OUT3L-
C98
330PF
0805
6
U6
C99
330PF
0805
7
3
C10
100PF
1206
DAC2 LEFT
2
U7
5
R34
5.49K
1206
C119
680PF
0805
AD8606ARZ
SOIC8
R33
1.65K
1206
R127
604.0
1206
OUT2L+
3
CT9
10UF
CAP002
J5
CON024
DAC2_LEFT 5
R153
2.74K
1206
C16
220PF
1206
3
1
DAC3 LEFT
R35
5.49K
1206
C120
680PF
0805
AD8606ARZ
SOIC8
R36
1.65K
1206
R129
604.0
1206
OUT3L+
CT11
10UF
CAP002
J5
CON024
DAC3_LEFT 2
6
R110
49.9K
1206
C78
2200PF
1206
R154
2.74K
1206
C17
220PF
1206
3
R112
49.9K
1206
C80
2200PF
1206
AGND
AGND
ANALOG
DEVICES
4
Board No.
C
Date
A
B
C
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF561 EZ-KIT LITE
AUDIO OUT
Title
Size
20 Cotton Road
Rev
A0185-2003
2.3
Sheet
11-7-2007_15:11
D
7
of
14
A
1
J4
CON013
B
CT5
10UF
CAP002
FER10
600
1206
2
R121
5.76K
1206
C
1
R49
5.76K
1206
J4
CON013
5
C128
120PF
1206
C62
100PF
1206
2
R123
5.76K
1206
R62
5.76K
1206
ADC2_LEFT
6
C142
120PF
1206
C72
100PF
1206
R53
237.0
1206
U11
AGND
U18
2
1
IN1L-
AGND
AGND
1
AGND
3
C25
1000PF
0805
R50
5.76K
1206
AD8606ARZ
SOIC8
C26
100PF
1206
R58
5.76K
1206
R63
5.76K
1206
ADC1 LEFT
C130
120PF
1206
6
C23
1000PF
0805
R164
750.0K
1206
R54
237.0
1206
U11
U18
6
7
7
IN1L+
5
2
ADC2 LEFT
C144
120PF
1206
AGND
R156
750.0K
1206
IN2L2
3
AD8606ARZ
SOIC8
R40
5.76K
1206
CT13
10UF
CAP002
FER12
600
1206
ADC1_LEFT
3
D
IN2L1
5
AD8606ARZ
SOIC8
2
AD8606ARZ
SOIC8
AGND
AGND
J4
CON013
CT6
10UF
CAP002
FER11
600
1206
1
R122
5.76K
1206
R15
5.76K
1206
J4
CON013
ADC1_RIGHT
4
3
C103
120PF
1206
C63
100PF
1206
2
CT14
10UF
CAP002
FER9
600
1206
R25
237.0
1206
U9
R69
5.76K
1206
ADC2_RIGHT
6
AGND
R124
5.76K
1206
C161
120PF
1206
C61
100PF
1206
2
1
1
IN1R-
AGND
AGND
3
R8
5.76K
1206
AD8606ARZ
SOIC8
C36
1000PF
0805
R16
5.76K
1206
C34
100PF
1206
R64
5.76K
1206
AGND
ADC1 RIGHT
6
R173
750.0K
1206
R26
237.0
1206
U9
6
7
ADC2 RIGHT
C163
120PF
1206
C33
1000PF
0805
3
R70
5.76K
1206
C105
120PF
1206
R132
750.0K
1206
IN2R2
3
AD8606ARZ
SOIC8
3
U24
AGND
U24
7
IN1R+
5
IN2R1
5
AD8606ARZ
SOIC8
AD8606ARZ
SOIC8
AGND
AGND
AD1836_VREF
ANALOG
DEVICES
4
Board No.
C
Date
A
B
C
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF561 EZ-KIT LITE
AUDIO IN
Title
Size
20 Cotton Road
Rev
A0185-2003
2.3
Sheet
11-7-2007_15:11
D
8
of
14
A
B
C
D
SW11
1
7
3
6
4
5
3
VIDEO_AVIN5
8
2
2
VIDEO_AVIN4
ON
1
VIDEO_AVIN1
VIDEO_DAC_A
VIDEO_DAC_C
VIDEO_DAC_B
4
DIP4
SWT018
1
SW11: Video Loopback
For Test Purposes
Default = All Off
R136
1K
1206
DAC A
DAC B
DAC C
Composite Video
CVSB
CVSB
C
Component Video
G
B
R
Differential Component Video
Y
U
V
S Video
Y
1
C
A3V
VIDEO_DAC_A
U3
L1
0.68UH
0805
L5
2.2UH
0805
J6
R104
75
1206
5
4
L4
0.68UH
0805
1
3
C92
330PF
0805
C86
330PF
0805
R6
75
1206
8
DAC A
AD8061ARTZ
SOT23-5
2
R114
75
1206
CON024
9
R10
1K
1206
AGND2
VIDEO ENCODER
3V_B
R116
1K
1206
2
2
U8
VAA1
VAA2
VAA3
VAA4
VAA5
PPI1_D[15:0]
SJ1
SHORTING
JUMPER
DEFAULT=1&2
JP1
PPI1_D7
5
PPI1_D6
4
PPI1_D5
3
PPI1_D4
39
PPI1_D3
38
PPI1_D2
37
PPI1_D1
36
PPI1_D0
35
1
VENC_27MHZ_CLK
2
P7
DAC_A
P6
DAC_B
P5
DAC_C
P3
COMP
P2
VREF
P1
RSET
IDC3X1
CLOCK
FIELD/VSYNC
BLANK
20
VENC_RESET
3
16
PF[15:0]
PF1
22
PF0
21
GND1
GND2
SDATA
GND3
SCLOCK
GND5
GND6
34
33
R14
10K
0805
25
C115
0.1UF
0805
C12
0.1UF
0805
R23
1.2K
1206
U1
GND7
SCRESET/RTC
GND8
TTX
GND9
TTXREQ
GND10
L8
0.68UH
0805
29
L9
2.2UH
0805
R107
75
1206
5
4
L2
0.68UH
0805
28
3
DAC B
5
AD8061ARTZ
SOT23-5
2
24
23
R135
75
1206
30
6
C94
330PF
0805
C82
330PF
0805
R4
75
1206
R115
1K
1206
31
13
VENC_HS
14
VENC_VS
15
R118
1K
1206
6
3
7
8
A3V
1
9
R3
150.0
1206
11
12
D1
AD1580BRTZ
SOT23D
VIDEO_DAC_C
2
U2
J6
17
4
19
L6
0.68UH
0805
26
L7
2.2UH
0805
2
R134
75
1206
C93
330PF
0805
C84
330PF
0805
R5
75
1206
2
DAC C
AD8061ARTZ
SOT23-5
3
R117
1K
1206
AGND2
ANALOG
DEVICES
4
Title
AGND2
Size
Date
C
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF561 EZ-KIT LITE
VIDEO ENCODER (VIDEO OUT)
Board No.
C
B
CON024
1
40
R9
100K
1206
R105
75
1206
5
L3
0.68UH
0805
3
R133
0
1206
A
CON024
1
ADV7179KCPZ
LFCSP40
R143
10K
0805
J6
27
AGND2
ALSB
3V_B
32
VIDEO_DAC_B
18
RESET
GND4
R13
100K
1206
10
P0
HSYNC
1
A3V
P4
3
VDEC_CLKOUT
2
Rev
A0185-2003
2.3
Sheet
11-7-2007_16:46
D
9
of
14
C
DAC_D
B
DAC_B
DAC_C
A
3.3V
(WHITE) OUT
1
D
VIDEO DECODER
R12
10K
0805
(RED) IN
R11
10K
0805
R131
10K
0805
R2
10K
0805
Note: Signal Names in brackets refer to ADV7183KST
1
XTAL1
P15
P14
P13
Composite Video
CVBS
CVBS
CVBS
Differential Component Video
Y
S Video
Y
PF[15:0]
V
PF1
67
PF0
68
ALSB
P12
SDA
P11
SCLK
P10
U
P9
C
64
VDEC_RESET
36
J6
CON024
R99
0
0805
7
AVIN1
P8
PWRDN
P7
P6
R7
10K
0805
C60
0.1UF
0805
RESET
65
NC[ISO]
P4
VIDEO_AVIN1
42
41
AIN1
P3
AIN7
P2
9
P1
TP1
44
43
J6
CON024
2
R103
0
0805
4
AVIN4
P5
C66
0.1UF
0805
P0
46
45
AIN3
LLC2
AIN9
NC[LLCREF]
6
ELPF
58
57
J6
CON024
R106
0
0805
1
AVIN5
C65
0.1UF
0805
60
59
AIN10
AIN5
AIN11
3
R100
75
1206
R102
75
1206
HS
62
61
CT3
10UF
B
C58
0.1UF
0805
CT1
10UF
B
FIELD
NC[VREF]
NC[HREF]
TP3
R101
75
1206
C2
0.1UF
0805
AGND2
52
49
AGND2
CT4
10UF
B
C59
0.1UF
0805
C68
1000PF
0805
AIN12
REFOUT
CML
CAPY1
CAPY2
54
NC[CLKIN]
SFL[HFF]
NC[AEF]
NC[RD]
OE
CAPC1
NC[GPO3]
CAPC2
NC[GPO2]
3
NC[GPO1]
NC[GPO0]
C4
0.1UF
0805
CT2
10UF
B
C57
0.1UF
0805
C67
1000PF
0805
50
AVDD
DVDD1
DVDD2
DVDD3
AGND2
A3V
A5V
AGND2
38
C54
0.1UF
0805
C1
0.1UF
0805
PVDD
DVDDIO1
DVDDIO2
39
FER13
600
1206
DNP
40
47
53
AGND2
5
PPI0_D3
6
PPI0_D2
7
PPI0_D1
8
PPI0_D0
19
R39
33
0805
20
AGND2
56
FER14
600
1206
63
21
4
22
SN74LVC1G32
SOT23-5
23
24
PVDD_ADV7183
32
33
27
C5
0.01UF
0805
26
25
2
C64
.082UF
0805
R1
1.5K
0805
37
2
VDEC_HS
1
VDEC_VS
80
VDEC_FIELD
69
VDEC_VREF
70
VDEC_HREF
16
SW2
11
12 ON
VENC_HS
12
11
R24
10K
0805
13
78
10
9
VENC_VS
77
8
79
7
C55
0.1UF
0805
34
DVDD_ADV7183
1.8V
35
FER15
600
1206
30
10
72
FER17
600
1206
DNP
4
3
4
5
PF3
6
PF2
PPI1_SYNC1
PPI0_SYNC1
PPI0_SYNC2
PPI1_SYNC2
PF[15:0]
3.3V
3
SW2: Video Sync Signals and Encoder Enable Select
Defalut = OFF, OFF, OFF, OFF, OFF, ON
Position
Function
1-5
Connect video sync signals to DSP
ON = PF2 Used to enable or disable
6
the encoder digital interface
OFF = Encoder digital interface always disabled
15
AGND1
AGND2
DGND1
AGND3
DGND2
AGND4
DGND3
AGND5
DGND4
NC[AGND6]
DGND5
3
9
14
31
71
C3
0.01UF
0805
C73
0.1UF
0805
ANALOG
DEVICES
C74
0.01UF
0805
Size
AGND2
Date
C
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF561 EZ-KIT LITE
VIDEO DECODER (VIDEO IN)
Board No.
C
B
2
18
Title
A
1
17
A1.8V
4
VDEC_CLKOUT
2
ADV7183BKSTZ
LQFP80
PVDD_ADV7183
FER1
600
1206
DNP
FER2
600
1206
R41
33
0805
U10
1
DIP6
SWT017
55
C56
0.1UF
0805
PPI0_D4
AIN6
NC[DV]
48
76
3.3V
NC[AFF]
51
PPI0_D5
AIN4
VS
VIDEO_AVIN5
75
PPI0_D[15:0]
AIN8
LLC1
TP2
VIDEO_AVIN4
AIN2
PPI0_D6
1
AVIN5
74
2
AVIN4
PPI0_D7
3
66
AVIN1
73
4
28
XTAL
5
29
VDEC_27MHZ_CLK
6
AVIN1
AVIN4
AVIN5
U4
Rev
A0185-2003
2.3
Sheet
11-7-2007_15:11
D
10
of
14
A
B
C
D
3.3V
3.3V
3.3V
R248
10K
0805
PF5
R242
100
0805
3
1
R247
0
1206
U47
R98
10K
0805
SW6
SWT013
MOMENTARY
4
74LVC14A
SOIC14
R246
10K
0805
U47
1
CT25
1UF
A
U47
2
74LVC14A
SOIC14
13
1
12
5V
74LVC14A
SOIC14
3.3V
RESET
LED2
RED
LED001
POWER
LED1
GREEN
LED001
3.3V
R119
680
1206
R120
270
1206
3.3V
R249
10K
0805
PF6
R243
100
0805
R223
0
1206
U47
11
RESET
74LVC14A
SOIC14
U46
CT26
1UF
A
2
R229
10K
0805
10
SW7
SWT013
MOMENTARY
1
MR
SW1
SWT013
MOMENTARY
4
PFI
8
RESET
7
RESET
5
PFO
2
RESET
ADM708SARZ
SOIC8
3.3V
DA_SOFT_RESET
R250
10K
0805
PF7
R244
100
0805
R224
0
1206
U47
9
SW8
SWT013
MOMENTARY
8
74LVC14A
SOIC14
3.3V
SJ2
CT27
1UF
A
SHORTING
JUMPER
DEFAULT=NOT INSTALLED
C158
0.1UF
0805
C159
0.1UF
0805
PF[15:0]
11
T1IN
PF5
PF5
2
11
PF6
10
PF7
4
9
PF8
5
8
6
7
4
6
TFS0
5
74LVC14A
SOIC14
3
3
5
2
R225
0
1206
U47
RSCLK0
6
CT28
1UF
A
ON 12
R191
0
0805
DNP
P2
FER19
600
0603
14
T1OUT
1
7
T2OUT
FER20
600
0603
13
R1OUT
R1IN
9
8
R2OUT
R2IN
ADM3202ARNZ
SOIC16
R192
0
0805
FER21
600
0603
6
V-
12
RX
1
1
R245
100
0805
SW9
SWT013
MOMENTARY
T2IN
SW4
R251
10K
0805
PF8
10
3
2
V+
TX
2
IDC2X1
4
C2+
5
C2-
3.3V
P1
1
C147
0.1UF
0805
1
C1+
3
C1-
3
R184
0
0805
DNP
U21
6
2
7
C148
0.1UF
0805
FER18
600
0603
UART
3
8
4
PF6
9
RFS0
5
TSCLK0
DIP6
SWT017
DB9M
NOTE: Remove R192 when populating R191 and R184
SW4 PB Enable Switch
Default = ON, ON, ON, ON, OFF, OFF
Position
Function
Connects the push buttons to the Programmable Flags of the DSP
1-4
Useful if using the PFs for another purpose.
OFF, OFF = AD1836A -> TDM Mode
5,6
ON, ON = AD1836A -> I2S Mode
4
ANALOG
DEVICES
Title
Size
A
B
C
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF561 EZ-KIT LITE
RESET, PUSH-BUTTON SWITCHES, UART
Board No.
C
Date
20 Cotton Road
Rev
A0185-2003
2.3
Sheet
11-7-2007_16:46
D
11
of
14
A
B
C
D
EXPANSION INTERFACE (TYPE B)
5V
3.3V
D[31:0]
A[25:2]
J1
2
1
4
3
5V
1
A3
6
5
8
7
10
9
A4
A7
12
11
A6
A9
14
13
A8
16
15
MOSI
MISO
A10
A13
18
17
A12
A15
20
19
A14
A17
22
21
A16
PF5
A19
A21
24
23
26
25
28
27
A22
30
29
A24
PPI0_SYNC2
PF0
2
32
31
DT1SEC
34
33
DT1PRI
35
TFS1
38
37
TSCLK1
40
39
D0
DT0SEC
D3
42
41
D2
DT0PRI
D5
44
43
D4
TFS0
D7
46
45
D6
TSCLK0
D9
48
47
D8
D11
50
49
D10
D13
52
51
D12
D15
54
53
D14
D17
56
55
D16
D19
58
57
D18
60
59
62
61
D22
D25
64
63
D24
ABE3
D26
ABE2
PPI0_D[15:0]
D29
68
67
D28
ABE1
D31
70
69
D30
ABE0
PPI0_D0
72
71
PPI0_D2
74
73
PF14
PF[15:0]
3
65
76
75
AOE
EXP_PPI0_CLK
PPI0_D1
AWE
PPI0_D3
SMS2
SMS0
PF12
78
77
PF15
PF10
80
79
PF13
PF8
82
81
PF11
PF6
84
83
PF9
PF4
86
85
7
10
9
12
11
14
13
16
15
18
17
20
19
SCK
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
NMI0
4
3
6
5
8
7
PPI1_D2
10
9
PPI1_D3
PPI1_D4
12
11
PPI1_D5
14
13
PPI1_D7
PPI1_D8
16
15
PPI1_D9
PPI0_SYNC1
PPI1_D10
18
17
PPI1_D11
DR1SEC
PPI1_D12
20
19
PPI1_D13
DR1PRI
PPI1_D14
22
21
PPI1_D15
RFS1
24
23
RSCLK1
26
25
28
27
DR0PRI
30
29
RFS0
32
31
34
33
36
35
38
37
40
39
42
41
44
43
46
45
48
47
RESET
VDEC_HS
RSCLK0
44
43
PPI0_D4
46
45
PPI0_D6
VDEC_HREF
PPI0_D9
48
47
PPI0_D8
DSP_VDD_EXT
PPI0_D11
50
49
PPI0_D10
PPI1_SYNC2
54
53
PPI0_D14
PF2
56
55
PF3
SRAS
PF7
88
87
SA10
90
89
SWE
CON019
60
59
62
61
64
63
66
65
68
67
70
69
72
71
74
73
76
75
78
77
80
79
82
81
84
83
86
85
88
87
90
89
EXP_PPI1_CLK
CLK_OUT_EXP1
2
EXT_DSP_CLK
VDEC_VS
VDEC_VREF
PPI1_SYNC3
PPI1_SYNC1
PPI0_D12
PPI0_D15
57
RX
PPI1_D6
PPI0_D7
58
PPI1_D1
PPI0_SYNC3
DR0SEC
41
51
1
TX
PPI0_D5
52
1
J3
2
PPI1_D0
D20
D23
66
8
3.3V
PPI1_D[15:0]
VDEC_FIELD
PF0
D27
5
42
PPI0_D13
D21
3
6
A20
A25
D1
4
A18
A23
36
1
A2
A5
A11
J2
2
PF1
50
49
AMS3
52
51
AMS2
54
53
AMS1
56
55
AMS0
58
57
ARDY
60
59
ARE
62
61
SMS3
64
63
SMS1
66
65
68
67
70
69
72
71
SCKE
74
73
SCAS
76
75
CLK_OUT_EXP2
78
77
80
79
82
81
84
83
86
85
88
87
90
89
CON019
EXT_27MHZ_CLK
3
BR
BG
BGH
CON019
ANALOG
DEVICES
4
Title
Size
A
B
C
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF561 EZ-KIT LITE
EXTENDER CARD CONNECTORS
Board No.
C
Date
20 Cotton Road
Rev
A0185-2003
2.3
Sheet
11-7-2007_15:11
D
12
of
14
A
B
C
D
UNREG_IN
F1
5A
FUS005
D3
MBRS540T3G
5A
SMC
FER22
190
FER002
4
3
1
2
C169
10UF
1210
UNREG_IN
J7
1
D2
MBRS540T3G
5A
SMC
C46
1000PF
1206
2
C180
470PF
1206
DNP
PGND
R72
24.9K
0603
3
7_0V_POWER
CON005
5
IN
1
COMP
C153
470PF
0603
1
TP12
4
1
L10
6.8UH
IND009
2
3
FB
6
PGATE
R74
0
0603
1
5
ADP1864AUJZ
SOT23-6
R80
80.6K
0603
3.3V
U28
4
CS
C160
68PF
0603
GND
2
C43
1000PF
1206
Current 2A
R79
0.027
1206
VR5
3
6
D4
SSB43L
DO-214AA
FDC658P
SOT23-6
CT19
100UF
C
C170
1UF
0603
DNP
W1
COPPER
R89
255.0K
0603
3A
SHGND
PGND
Current 500mA
PGND
PGND
UNREG_IN
3.3V
3.3V
1.8V
A1.8V
C260
10UF
1210
FER4
600
1206
VR2
7
1
IN1
R52
10K
0805
OUT1
8
2
IN2
OUT2
PGND
R48
76.8K
1206
3
OUT3
6
SD
2
5
FB
GND
4 ADP3336ARMZ
MSOP8
R256
24.9K
0603
C24
1UF
0805
5
C258
470PF
0603
U49
2A
4
CS
C257
68PF
0603
2
1
L12
6.8UH
IND009
2
3
FB
R56
147.0K
1206
6
PGATE
GND
2
R255
80.6K
0603
W2
COPPER
TP13
IN
1
COMP
4
C21
1UF
0805
Current 1.5A
R253
0.047
1206
VR6
R254
0
0603
PGND
5
ADP1864AUJZ
SOT23-6
3
6
D8
SSB43L
DO-214AA
FDC658P
SOT23-6
CT29
100UF
C
C259
1UF
0603
DNP
R252
54.9K
0603
PGND
Current 1.5A
PGND
3.3V
5V
UNREG_IN
R163
0
1206
VR1
3
INPUT
OUTPUT1
OUTPUT2
CT23
10UF
C
3
C122
0.1UF
0805
A5V
R83
0
1206
FER6
600
1206
DSP_VDD_INT
DSP_VDD_EXT
2
JP3
4
1
U29
GND
1 ADP3339AKCZ-5
SOT-223
R257
0
1206
L11
10UH
IND001
SJ3
CT24
10UF
C
SHORTING
JUMPER
DEFAULT=INSTALLED
C29
0.1UF
0805
JP2
1
VROUT
2
1
5
2
6
3
7
4
8
2
3
3
IDC3X1
D5
ZHCS1000
SOT23-312
1A
IDC2X1
CT22
68UF
D
SJ4
SHORTING
JUMPER
DEFAULT=1&2
DSP_VDD_EXT
NDS8434A
SO-8
C48
0.1UF
0805
MH2
MH1
MH3
MH4
D7
2A
DO-214AA
MH5
Current 1A
UNREG_IN
A3V
3V_B
M1
FER3
600
1206
VR3
3
INPUT
2
OUTPUT1
R73
0
1206
FER16
600
1206
4
OUTPUT2
GND
1
ADP3338AKCZ-33
SOT-223
C32
1UF
0805
M2
M3
M4
M5
DSP_VDD_INT
RUBBER FOOTRUBBER FOOTRUBBER FOOTRUBBER FOOTRUBBER FOOT
MSC009
MSC009
MSC009
MSC009
MSC009
SHGND
CT17
10UF
C
C35
0.1UF
0805
TP8
MH6
MH7
TP5
TP11
TP10
TP6
TP4
TP9
FER8
600
1206
MH8
4
ANALOG
DEVICES
SHGND
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF561 EZ-KIT LITE
POWER
Title
SHGND
Size
Board No.
C
Date
A
B
C
Rev
A0185-2003
2.3
Sheet
11-7-2007_16:46
D
13
of
14
A
B
C
D
DSP_VDD_EXT
DSP_VDD_INT
C137
0.01UF
0805
C140
0.01UF
0805
C49
0.01UF
0805
C174
0.01UF
0805
C30
0.1UF
0805
C151
0.1UF
0805
C179
0.1UF
0805
C155
0.1UF
0805
C175
0.1UF
0805
C51
0.1UF
0805
C31
10UF
1210
C50
10UF
1210
C47
10UF
1210
C173
0.01UF
0805
C154
0.01UF
0805
C145
0.1UF
0805
C172
0.1UF
0805
C178
0.1UF
0805
C152
0.1UF
0805
C176
0.01UF
0805
C138
0.01UF
0805
C52
0.1UF
0805
C164
0.1UF
0805
C139
0.1UF
0805
C171
0.1UF
0805
C177
0.1UF
0805
C167
0.1UF
0805
C146
0.01UF
0805
C41
0.01UF
0805
1
1
ADSP-DM203
U48
5V
3.3V
3.3V
C126
0.1UF
0805
C135
0.1UF
0805
3.3V
3.3V
C136
0.01UF
0805
C168
0.01UF
0805
3.3V
C157
0.01UF
0805
C195
10UF
1210
C156
0.01UF
0805
C196
0.1UF
0805
C197
10UF
1210
C198
0.1UF
0805
C199
0.1UF
0805
Expansion Interface
27MHZ OSC
U17
3.3V
5V
C134
0.01UF
0805
A5V
C19
0.1UF
0805
C37
0.1UF
0805
3
C256
0.01UF
0805
C22
0.1UF
0805
A5V
Expansion Interface
C108
0.22UF
0805
A5V
C107
0.22UF
0805
A5V
C162
0.22UF
0805
A5V
C143
0.22UF
0805
A5V
C129
0.22UF
0805
3.3V
C104
0.22UF
0805
AGND
AGND
AGND
AGND
AGND
AGND
AGND
U15
AD8606
U7
AD8606
U6
AD8606
U24
AD8606
U18
AD8606
U11
AD8606
U9
3V_B
A3V
C20
0.1UF
0805
C71
0.1UF
0805
SN74AHC1G08
U10
3.3V
A3V
C75
0.01UF
0805
C85
0.1UF
0805
C70
0.01UF
0805
AGND
AGND
AD8606
U5
C83
0.1UF
0805
AGND2
AGND2
AD8061
U2
AD8061
U1
3.3V
3.3V
2
3.3V
AGND2
3.3V
C106
0.22UF
0805
AD8606
U12
A3V
AD8061
U3
3.3V
A5V
C125
0.22UF
0805
74LVC14A
U47
A5V
C131
0.1UF
0805
AD1836
U15
U15
C28
0.01UF
0805
M29W640D
U27
IDT2305
U19
2
C27
0.1UF
0805
A5V
C69
0.01UF
0805
3.3V
3.3V
C149
0.01UF
0805
C150
0.01UF
0805
ADG752
U22
ADG752
U23
3.3V
3.3V
3
DVDD_ADV7183
C101
0.01UF
0805
C114
0.01UF
0805
C91
0.1UF
0805
C89
0.1UF
0805
C102
0.1UF
0805
C90
0.1UF
0805
C109
0.1UF
0805
C110
0.1UF
0805
C113
0.01UF
0805
C192
0.01UF
0805
ADV7179
U8
C112
0.01UF
0805
4
C191
0.1UF
0805
C194
0.01UF
0805
C87
0.1UF
0805
C111
0.1UF
0805
C202
0.01UF
0805
C88
0.1UF
0805
C249
0.01UF
0805
C141
0.01UF
0805
ADM708SAR
U46
ADV7183
U4
3.3V
C189
0.1UF
0805
C193
0.01UF
0805
ADM3202
U21
C181
0.01UF
0805
IDT74FCT3244APY
U30
C127
0.01UF
0805
IDT74FCT3244APY
U13
ADG752
U25
C166
0.01UF
0805
C132
0.1UF
0805
ADG752
U26
30MHZ OSC
U14
3.3V
C203
0.01UF
0805
C190
0.01UF
0805
C187
0.01UF
0805
C188
0.01UF
0805
C183
0.1UF
0805
C184
0.1UF
0805
C185
0.01UF
0805
C186
0.01UF
0805
C201
0.01UF
0805
C200
0.01UF
0805
ANALOG
DEVICES
C182
0.01UF
0805
SDRAM
U33
Size
SDRAM
U32
B
Board No.
C
Date
C
20 Cotton Road
Nashua, NH 03063
4
PH: 1-800-ANALOGD
ADSP-BF561 EZ-KIT LITE
DECOUPLING CAPS
Title
A
C165
0.01UF
0805
Rev
A0185-2003
2.3
Sheet
11-7-2007_15:11
D
14
of
14
I
INDEX
Numerics
2-wire interface (TWI) mode, 1-15, 1-17,
2-12
A
A25-2 address bus pins, 2-3
AD1836A audio codecs, 1-15, 2-3, 2-4,
2-12
ADV7179 video encoders
video interface, 1-16
clock select jumper (JP1), 2-14
configuration switch (SW2), 2-10
PPI1 interface, 2-6, 2-7
programmable flags, 2-4
reset, 1-16
ADV7183A video decoders
video interface, 1-16
clock select switch (SW5), 2-13
configuration switch (SW2), 2-10
PPI0 interface, 2-6, 2-7
programmable flags, 2-4
reset, 1-16
AIN1/4/5 analog video channels, 2-7
AMS0 memory select pins, 1-12
analog
audio interface, See SPORT0
video interface, See video interface
architecture, of this EZ-KIT Lite, 2-2
ASYNC (asynchronous memory control)
banks, 1-11
audio
codecs, See AD1836A
connectors (J4-5), 2-19
enable switch (SW12), 2-13
interface, See SPORT
B
bill of materials, A-1
BMODE1-0 (boot mode select) pins, 2-12
board design database, 1-17
board schematic (ADSP-BF561), B-1
boot mode select switch (SW3), 2-11
C
clock select switch, of PPIs (SW5), 2-13
codecs, See AD1836A
configuration, of this EZ-KIT Lite, 1-3
connectors
diagram of locations, 2-18
DB9 (UART), xii, 2-8
J1-3 (expansion), 2-8, 2-19
J4-5 (audio), 2-19
J6 (video), 2-20
J7 (power), 2-20
P2 (RS-232), xi, 2-20
P3 (SPORT1), 2-3, 2-21
P5 (SPI), 2-3, 2-14, 2-21
P9 (SPORT0), 2-21
ZJ1 (USB), 1-5, 2-21
ZP4 (JTAG), 2-22
contents, of this EZ-KIT Lite package, 1-2
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
I-1
Index
F
core
clock rate, 2-2, 2-14
frequency, 1-14
voltage, 2-2
D
DAC A/B/C analog audio channels, 2-7
DB9 (UART) connector, xii, 2-8, 2-20
default configuration, of this EZ-KIT Lite,
1-3
DIP switches
diagram of locations, 1-3, 2-10
SW10-11 (test), 2-13
SW2 (video config), 1-16, 2-8
SW4 (push button enable), 1-15, 2-12,
2-16
features, of this EZ-KIT Lite, xi
FIELD (ADV7183A) control signal, 2-4,
2-8, 2-11
FIO0_FLAG_D registers, 1-15
FIO2_DIR register, 1-14
FIO2_FLAG_C/D/S/T registers, 1-14
flag pins, See programmable flags (PFs)
flash
memory, 2-3
ports (PB47-32), 2-17
frequency, 1-13, 1-14
G
general-purpose IO pins, 1-14, 2-4, 2-12,
2-16
GND signals, 2-8
E
EBIU
address bus (A25-2) pins, 2-3
control signals, 2-3, 2-8
EBIU_SDBCTL register, 1-13, 1-14
EBIU_SDGCTL register, 1-13, 1-14
EBIU_SDRRC register, 1-13, 1-14
evaluation license
CCES, 1-10
example programs, 1-18
expansion interface, 2-3, 2-8, 2-19
external bus interface unit, See EBIU
external memory
See also flash memory, SDRAM
memory map, 1-11
via JTAG, 2-9
EZ-KIT Extender boards, 2-6
I-2
H
HSYNC signals, 2-6, 2-7
I
input clocks, 1-16, 2-2, 2-5, 2-7
installation, of this EZ-KIT Lite, 1-8
CCES, 1-4
interfaces, See video, SPORT0, SPI,
expansion
internal memory
See also SRAM
map of the processor, 1-12
internal voltage (VDDINT), 2-14
IO voltage, 2-2
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Index
J
JTAG
connector (ZP4), 2-9, 2-22
emulation port, 2-9
jumpers
JP1 (ADV7179 clock select), 2-14
JP2-3 (VDDINT source select), 2-14
P1 (UART loop), 2-15
L
LEDs
diagram of locations, 1-3, 2-15
LED13-20 (PF39-32), 1-14, 2-5, 2-17
LED1 (power), 2-16
LED2 (chip reset), 2-17
LED5-12 (PF47-40), 1-14, 2-5, 2-17
ZLED3 (USB monitor), 1-8, 2-17
M
Media Instruction Set Computing (MISC),
ix
memory
map, of this EZ-KIT Lite, 1-11
select pins, See AMS2-0, SMS0
Micro Signal Architecture (MSA), ix
N
notation conventions, xviii
O
OE (ADV7183A) signal, 2-4, 2-10
oscillators, 2-6, 2-7, 2-13
P
P3 (SPORT0) connector, 2-3
package contents, 1-2
parallel peripheral interfaces (PPIs), 1-17,
2-5, 2-10, 2-19
See also PPI0, PPI1
PB47-32 flash ports, 2-17
power
connector (J7), 2-20
LED (LED1), 2-16
PPI0_D15-8 bits, 1-14, 2-5
PPI0 interface
to ADV7183A decoder, 1-16, 2-7
clock select pin, 2-6, 2-7
D15-8 bits, 2-17
D7-0 bits, 2-6
SYNC2-1 signals, 2-6, 2-8, 2-11
PPI0_SYNC2-1 synchronization signals,
2-8, 2-11
PPI1_D15-8 bits, 1-14, 2-5
PPI1 interface
to ADV7179 video encoder, 1-16, 2-7
clock select pin, 2-7
D15-8 bits, 2-17
D7-0 bits, 2-6, 2-7
HSYNC signals, 2-7
SYNC2-1 signals, 2-7, 2-11
PPI clock select switch (SW5), 1-16, 2-13
PPIxCLK signals, 2-13
product information, xvi
programmable flags (PFs)
connections, 2-4
PF0 (video serial clock), 1-17, 2-4
PF1 (video serial data), 1-17, 2-4
PF2 (DV7183A enable), 1-17, 2-4, 2-10,
2-11
PF3 (ADV7183A field pin), 2-4, 2-8,
2-11
PF4 (AD1836A SPI select), 1-15, 2-3,
2-4
PF13 (ADV7183A reset), 1-16, 2-4
PF14 (ADV7179 reset), 1-16, 2-5
PF15 (AD1836A reset), 1-16, 2-5
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
I-3
Index
programmable flags (PFs)
(continued)
PF16-20 (SPORT0), 2-5
PF21-25 (SPORT1), 2-5
PF26-27 (UART), 2-5
PF28-29 (SPORT0 serial clock), 2-5
PF30-31 (SPORT1 serial clock), 2-5
PF39-32 (LED13-20), 2-5
PF47-40 (LED5-12), 1-14, 2-5
PF5-8 (general-purpose IO), 1-14, 2-4,
2-12, 2-16
pull-down resistors, 1-16
pull-up resistors, 2-11
push buttons
See also switches by name (SWx), 1-14
diagram of locations, 2-15
enable switch (SW4), 2-12
R
RCA jacks, xi, 2-19
Reduced Instruction Set Computing
(RISC), ix
related documents, xviii
reset
audio codec, 1-16
LED (LED2), 2-17
processor, 1-13
push buttons switch (SW1), 2-16
USB interface, 2-16
video encoder/decoder, 1-16, 2-4
RFS0 signal, 1-15, 2-12
RS-232 connector (P2), xi, 2-8
RSCLK0 signal, 1-15, 2-12
S
schematic, of ADSP-BF561 EZ-KIT Lite,
B-1
SDRAM memory
connections, 2-3
control registers, 1-12
I-4
SDRAM memory
(continued)
core MMRs, 1-12
data bank B SRAM, 1-12
data banks A, B SRAM, 1-12
default settings, 1-13
instruction SRAM, 1-12
instruction SRAM/CACHE, 1-12
optimum settings, 1-14
reserved, 1-12
scratch pad SRAM, 1-12
system MMRs, 1-12
serial
clock pin (SCL), 1-17, 2-4
data pin (SDAT), 1-17
video data, 2-4
serial peripheral interface (SPI), 2-3, 2-4,
2-14
setup, of this EZ-KIT Lite, 1-4
SMS0 memory select pins, 1-12
SPIS1/SPISS signals, 2-14
SPORT
audio interface, 2-3
SPORT0
audio interface, xii, 1-15
connector (P3), 2-21
receive data secondary pin (PF20), 2-5
receive frame sync pin (PF19), 2-5
receive serial clock pin (PF28), 2-5
transmit data primary pin (PF18), 2-5
transmit data secondary pin (PF17), 2-5
transmit frame sync pin (PF16), 2-5
transmit serial clock pin (PF29), 2-5
SPORT1
receive data secondary pin (PF25), 2-5
receive frame sync pin (PF24), 2-5
receive serial clock pin (PF29), 2-5
transmit data primary pin (PF23), 2-5
transmit data secondary pin (PF22), 2-5
transmit frame pin (PF21), 2-5
transmit serial clock pin (PF31), 2-5
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Index
SRAM data bank A, 1-12
startup, of this EZ-KIT Lite, 1-8
CCES, 1-4
SW10-11 (test) DIP switches, 2-13
SW12 (audio enable) switch, 2-13
SW13 (SPIS1/SPISS select) switch, 2-14
SW1 (reset) push button, 2-16
SW2 (video config) DIP switch, 1-16, 2-6,
2-7, 2-8, 2-11
SW3 (boot mode) switch, 2-11
SW4 (push button enable) DIP switch,
1-15, 2-12, 2-16
SW5 (PPI clock select) switch, 1-16, 2-6,
2-13
SW6-9 (general input) push buttons, 1-14,
2-4, 2-12, 2-16
synchronous dynamic random access
memory, See SDRAM
system
architecture, of EZ-KIT Lite, 2-2
clock (SCLK), 1-13
T
technical support, xv
test DIP switches (SW10-11), 2-13
TFS0 signal, 1-15, 2-12
time-division multiplexed (TDM) mode,
1-15
timers11-8, 2-6
timers7-0, 2-4
TSCLK0 signal, 1-15, 2-12
USB
cable, 1-2
connector (ZJ1, 1-5
debug agent connector (ZJ1), 2-21
interface, 2-9, 2-16, 2-22
monitor LED (ZLED3), 2-17
user LEDs (LED5-12, LED13-20), 2-17
V
VDDINT signal, 2-14
very-long instruction word (VLIW), ix
video
channels, 2-7
configuration switch (SW2), 2-10
connector (J6), 2-20
control signals, 2-7, 2-8
decoders, See ADV7183A
encoders, See ADV7179
input (PPI0), 2-7
interface, 1-16
output (PPI1), 2-7
VisualDSP++
environment, 1-8
VROUT pins, 2-14
VSYNC signals, 2-6, 2-7
U
UART
loop jumper (P1), 2-15
port, xii, 2-8
transmit/receive pins (PF26-27), 2-5
universal asynchronous
receiver/transmitter, See UART port
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
I-5
Index
I-6
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
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