ADSP-BF561 EZ-KIT Lite® Evaluation System Manual Revision 1.2, July 2004 Part Number 82-000811-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information © 2003 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Limited Warranty The EZ-KIT Lite evaluation system is warranted against defects in materials and workmanship for a period of one year from the date of purchase from Analog Devices or from an authorized dealer. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc. Trademark and Service Mark Notice The Analog Devices logo, Blackfin, and EZ-KIT Lite are registered trademarks of Analog Devices, Inc. VisualDSP++ is a trademark of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. Regulatory Compliance The ADSP-BF561 EZ-KIT Lite evaluation system has been certified to comply with the essential requirements of the European EMC directive 89/336/EEC (inclusive 93/68/EEC) and, therefore, carries the “CE” mark. The ADSP-BF561 EZ-KIT Lite evaluation system had been appended to the Technical Construction File referenced “DSPTOOLS1” dated December 21, 1997 and was awarded CE Certification by an appointed European Competent Body as listed below. Technical Certificate No: Z600ANA1.016 Issued by: Technology International (Europe) Limited 41 Shrivenham Hundred Business Park Shrivenham, Swindon, SN6 8TZ, UK The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused EZ-KIT Lite boards in the protective shipping package. iv ADSP-BF561 EZ-KIT Lite Evaluation System Manual CONTENTS PREFACE Purpose of This Manual ................................................................. xii Intended Audience ......................................................................... xii Manual Contents .......................................................................... xiii What’s New in This Manual ........................................................... xiv Technical or Customer Support ...................................................... xiv Supported Processors ...................................................................... xiv Product Information ....................................................................... xv MyAnalog.com .......................................................................... xv DSP Product Information .......................................................... xv Related Documents .................................................................. xvi Online Documentation ........................................................... xvii Printed Manuals ..................................................................... xviii VisualDSP++ Documentation Set ....................................... xviii Hardware Manuals ............................................................. xviii Data Sheets ........................................................................ xviii Contacting DSP Publications .................................................... xix Notation Conventions .................................................................... xix ADSP-BF561 EZ-KIT Lite Evaluation System Manual v CONTENTS GETTING STARTED Contents of EZ-KIT Lite Package ................................................. 1-1 PC Configuration ......................................................................... 1-3 Installation Tasks .......................................................................... 1-3 Installing VisualDSP++ and EZ-KIT Lite Software .................. 1-4 Installing and Registering VisualDSP++ License ....................... 1-5 Setting Up EZ-KIT Lite Hardware .......................................... 1-5 Installing EZ-KIT Lite USB Driver ......................................... 1-7 Windows 98 USB Driver .................................................... 1-8 Windows 2000 USB Driver .............................................. 1-12 Windows XP USB Driver ................................................. 1-13 Verifying Driver Installation .................................................. 1-15 Starting VisualDSP++ ........................................................... 1-16 USING EZ-KIT LITE EZ-KIT Lite License Restrictions .................................................. 2-2 Using External Memory ................................................................ 2-2 Using LEDs and Push Buttons ...................................................... 2-5 Using Audio ................................................................................. 2-6 Using Video ................................................................................. 2-7 Example Programs ........................................................................ 2-8 Using Background Telemetry Channel .......................................... 2-8 Using EZ-KIT Lite VisualDSP++ Interface .................................... 2-9 Target Options ........................................................................ 2-9 vi ADSP-BF561 EZ-KIT Lite Evaluation System Manual CONTENTS Reset Options ..................................................................... 2-9 On Emulator Exit ............................................................. 2-10 XML File .......................................................................... 2-10 Other Options .................................................................. 2-11 Restricted Software Breakpoints ............................................. 2-12 EZ-KIT LITE HARDWARE REFERENCE System Architecture ...................................................................... 3-2 External Bus Interface Unit ...................................................... 3-3 SPORT0 Audio Interface ......................................................... 3-3 SPI Interface ........................................................................... 3-3 Programmable Flags ................................................................. 3-4 PPI Interfaces .......................................................................... 3-6 Video Output (PPI1) .......................................................... 3-7 Video Input (PPI0) ............................................................. 3-8 UART Port .............................................................................. 3-8 Expansion Interface ................................................................. 3-8 JTAG Emulation Port .............................................................. 3-9 Jumper and DIP Switch Settings .................................................. 3-10 Video Configuration Switch (SW2) ....................................... 3-10 Boot Mode Switch (SW3) ...................................................... 3-11 Push Button Enable Switch (SW4) ......................................... 3-12 PPI Clock Select Switch (SW5) .............................................. 3-13 Test DIP Switches (SW10, SW11) ......................................... 3-13 LEDs and Push Buttons .............................................................. 3-14 ADSP-BF561 EZ-KIT Lite Evaluation System Manual vii CONTENTS Reset Push Button (SW1) ...................................................... 3-14 Programmable Flag Push Buttons (SW9–6) ............................ 3-15 Power LED (J7) .................................................................... 3-15 Reset LEDs (LED2, LED3) ................................................... 3-15 USB Monitor LED (LED4) ................................................... 3-16 User LEDs (LED12–5, LED20–13) ...................................... 3-16 Connectors ................................................................................. 3-17 Expansion Interface (J1, J2, J3) ............................................. 3-17 Audio (J4, J5) ....................................................................... 3-18 Video (J6) ............................................................................. 3-18 Power (J7) ............................................................................ 3-18 USB (J8) .............................................................................. 3-19 RS232 (P2) ........................................................................... 3-20 SPORT0 (P3) ....................................................................... 3-20 JTAG (P4) ............................................................................ 3-20 BILL OF MATERIALS INDEX viii ADSP-BF561 EZ-KIT Lite Evaluation System Manual PREFACE Thank you for purchasing the ADSP-BF561 EZ-KIT Lite®, Analog Devices (ADI) evaluation system for Blackfin® embedded media processors. The Blackfin processors are embedded processors that support a Media Instruction Set Computing (MISC) architecture. This architecture is the natural merging of RISC, media functions, and digital signal processing (DSP) characteristics towards delivering signal processing performance in a microprocessor-like environment. The evaluation board is designed to be used in conjunction with the VisualDSP++™ development environment to test the capabilities of the ADSP-BF561 Blackfin processors. The VisualDSP++ development environment gives you the ability to perform advanced application code development and debug, such as: • Create, compile, assemble, and link application programs written in C++, C and ADSP-BF561 assembly • Load, run, step, halt, and set breakpoints in application program • Read and write data and program memory • Read and write core and peripheral registers • Plot memory Access to the ADSP-BF561 processor from a personal computer (PC) is achieved through a USB port or an optional JTAG emulator. The USB interface gives unrestricted access to the ADSP-BF561 processor and the ADSP-BF561 EZ-KIT Lite Evaluation System Manual ix evaluation board peripherals. Analog Devices JTAG emulators offer faster communication between the host PC and target hardware. Analog Devices carries a wide range of in-circuit emulation products. To learn more about Analog Devices emulators and DSP development tools, go to http://www.analog.com/dsp/tools/. ADSP-BF561 EZ-KIT Lite provides example programs to demonstrate the capabilities of the evaluation board. VisualDSP++ license provided with this EZ-KIT Lite evaluaL The tion system limits the size of a user program to 41 KB of internal memory. The board features: • Analog Devices ADSP-BF561 processor D D 256-pin Mini-BGA package 30 MHz CLKIN oscillator • Synchronous Dynamic Random Access Memory (SDRAM) D 64 MB (16M x 16 bits x 2 chips) • Flash Memory D 8 MB (4M x 16 bits) • Analog Audio Interface D D D AD1836 A – Analog Devices 96 kHz audio codec 4 input RCA phono jacks (2 Stereo Channels) 6 output RCA phono jacks (3 Stereo Channels) • Analog Video Interface D D x ADV7183A video decoder w/ 3 input RCA phono jacks ADV7179 video encoder w/ 3 output RCA phono jacks ADSP-BF561 EZ-KIT Lite Evaluation System Manual Preface • Universal Asynchronous Receiver/Transmitter (UART) D D ADM3202 RS-232 line driver/receiver DB9 male connector • LEDs D 20 LEDs: 1 power (green), 1 board reset (red), 1 USB (red), 16 general purpose (amber), and 1 USB monitor (amber) • Push Buttons D 5 push buttons with debounce logic: 1 reset, 4 programmable flags • Expansion Interface D PPI0, PPI1, SPI, EBIU, Timers11-0, UART, Programmable Flags, SPORT0, SPORT1 • Other Features D JTAG ICE 14-pin header The EZ-KIT Lite board holds 8 MB of Flash memory, which can be used to store user-specific boot code, allowing the board to run as a stand-alone unit. The board also holds 512-Mb SDRAM, which can be used at runtime. For more information see “Using External Memory” on page 2-2. interfaces with the AD1836A audio codec, allowing you to create audio signal processing applications. SPORT0 also attaches to an off-board connector to allow communication with other serial devices. For information about SPORT0, see “SPORT0 Audio Interface” on page 3-3. SPORT0 The Parallel Peripheral Interfaces (PPIs) of the DSP connect to both a video encoder and video decoder, allowing you to create video signal processing applications. For information on how the board utilizes the processor’s PPIs, see “PPI Interfaces” on page 3-6. ADSP-BF561 EZ-KIT Lite Evaluation System Manual xi Purpose of This Manual The UART of the DSP connects to an RS232 Line Driver and a DB9 male connector, allowing you to interface with a PC or other serial device. For information about the UART, see “UART Port” on page 3-8. Additionally, the EZ-KIT Lite board provides access to most of the processor’s peripheral ports. Access is provided in the form of a three-connector expansion interface. For information about the expansion interface, see “Expansion Interface” on page 3-8. Purpose of This Manual The ADSP-BF561 EZ-KIT Lite Evaluation System Manual provides instructions for using the hardware and installing the software on your PC. This manual provides guidelines for running your own code on the ADSP-BF561 EZ-KIT Lite. The manual also describes the operation and configuration of the evaluation board’s components. Finally, a schematic and a bill of materials are provided as a reference for future ADSP-BF561 board designs. Intended Audience This manual is a user’s guide and reference to the ADSP-BF561 EZ-KIT Lite evaluation system. Programmers who are familiar with the Analog Devices Blackfin processor architecture, operation, and programming are the primary audience for this manual. Programmers who are unfamiliar with Analog Devices Blackfin processors can use this manual in conjunction with the ADSP-BF561 Blackfin Processor Hardware Reference and the Blackfin Processor Instruction Set Reference, which describe the processor’s architecture and instruction set. Programmers who are unfamiliar with VisualDSP++ should refer to the xii ADSP-BF561 EZ-KIT Lite Evaluation System Manual Preface VisualDSP++ online Help and the VisualDSP++ user’s or getting started guides. For the locations of these documents, refer to “Related Documents”. Manual Contents The manual consists of: • Chapter 1, “Getting Started” on page 1-1 Provides software and hardware installation procedures, PC system requirements, and basic board information. • Chapter 2, “Getting Started” on page 1-1 Provides information on the EZ-KIT Lite from a programmer’s perspective and provides an easy-to-access memory map. • Chapter 3, “EZ-KIT Lite Hardware Reference” on page 3-1 Provides information on the hardware aspects of the evaluation system. • Appendix A, “Bill Of Materials” on page A-1 Provides a list of components used to manufacture the EZ-KIT Lite board. • Appendix B, “Schematics” on page B-1 Provides the resources to allow EZ-KIT Lite board-level debugging or to use as a reference design. This appendix is not part of the online Help. The online Help viewers should go the PDF version of the ADSP-BF561 EZ-KIT Lite Evaluation System Manual located in the Docs\EZ-KIT Lite Manuals folder on the installation CD to see the schematics. ADSP-BF561 EZ-KIT Lite Evaluation System Manual xiii What’s New in This Manual What’s New in This Manual This is the first edition of the ADSP-BF561 EZ-KIT Lite Evaluation System Manual. The manual documents the tools support for ADSP-BF561 Blackfin processors. Technical or Customer Support You can reach DSP Tools Support in the following ways. • Visit the DSP Development Tools website at www.analog.com/technology/dsp/developmentTools/index.html • Email questions to [email protected] • Phone questions to 1-800-ANALOGD • Contact your ADI local sales office or authorized distributor • Send questions by mail to Analog Devices, Inc. One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 USA Supported Processors The ADSP-BF561 EZ-KIT Lite evaluation system supports ADSP-BF561 Blackfin Analog Devices embedded processors. xiv ADSP-BF561 EZ-KIT Lite Evaluation System Manual Preface Product Information You can obtain product information from the Analog Devices website, from the product CD-ROM, or from the printed publications (manuals). Analog Devices is online at www.analog.com. Our website provides information about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors. MyAnalog.com MyAnalog.com is a free feature of the Analog Devices website that allows customization of a webpage to display only the latest information on products you are interested in. You can also choose to receive weekly email notification containing updates to the webpages that meet your interests. MyAnalog.com provides access to books, application notes, data sheets, code examples, and more. Registration: Visit www.myanalog.com to sign up. Click Register to use MyAnalog.com. Registration takes about five minutes and serves as means for you to select the information you want to receive. If you are already a registered user, just log on. Your user name is your email address. DSP Product Information For information on digital signal processors, visit our website at www.analog.com/dsp, which provides access to technical publications, data sheets, application notes, product overviews, and product announcements. ADSP-BF561 EZ-KIT Lite Evaluation System Manual xv Product Information You may also obtain additional information about Analog Devices and its products in any of the following ways. • Email questions or requests for information to [email protected] • Fax questions or requests for information to 1-781-461-3010 (North America) or +49 (0) 89 76903-157 (Europe) Related Documents For information on product related development software, see the following publications. Table 1. Related DSP Publications Title Description ADSP-BF561 Blackfin Embedded Symmetric Multi-Processor data sheet General functional description, pinout, and timing. ADSP-BF561 Blackfin Processor Hardware Reference Description of internal processor architecture and all register functions. Blackfin Processor Instruction Set Reference Description of all allowed processor assembly instructions. Table 2. Related VisualDSP++ Publications Title Description VisualDSP++ 3.5 User’s Guide for 16-Bit Proces- Detailed description of VisualDSP++ 3.5 feasors tures and usage. xvi VisualDSP++ 3.5 Assembler and Preprocessor Manual for Blackfin Processors Description of the assembler function and commands for Blackfin processors. VisualDSP++ 3.5 C/C++ Complier and Library Manual for Blackfin Processors Description of the complier function and commands for Blackfin processors ADSP-BF561 EZ-KIT Lite Evaluation System Manual Preface Table 2. Related VisualDSP++ Publications (Cont’d) Title Description VisualDSP++ 3.5 Linker & Utilities Manual for 16-Bit Processors Description of the linker function and commands for 16-bit processors. VisualDSP++ 3.5 Loader Manual for 16-Bit Processors Description of the loader/splitter function and commands for 16-bit processors. The listed documents can be found through online Help or in the Docs folder of your VisualDSP++ installation. Most documents are available in printed form. you plan to use the EZ-KIT Lite board in conjunction with a L IfJTAG emulator, refer to the documentation that accompanies the emulator. Online Documentation Your software installation kit includes online Help as part of the Windows® interface. These help files provide information about VisualDSP++ and the ADSP-BF561 EZ-KIT Lite evaluation system. To view VisualDSP++ Help, click on the Help menu item or go to the Windows task bar and select Start -->Programs -->Analog Devices -->VisualDSP++ 3.5 for 16-bit Processors --> VisualDSP++ Documentation. To view ADSP-BF561 EZ-KIT Lite Help, which now is a part of the VisualDSP++ Help system, go the Contents tab of the Help window and select Manuals --> ADSP-BF561 EZ-KIT Lite. For more documentation, please go to http://www.analog.com/technology/dsp/library.html. ADSP-BF561 EZ-KIT Lite Evaluation System Manual xvii Product Information Printed Manuals For general questions regarding literature ordering, call the Literature Center at 1-800-ANALOGD (1-800-262-5643) and follow the prompts. VisualDSP++ Documentation Set Printed copies of VisualDSP++ manuals may be purchased through Analog Devices Customer Service at 1-781-329-4700; ask for a Customer Service representative. The manuals can be purchased only as a kit. For additional information, call 1-603-883-2430. If you do not have an account with Analog Devices, you will be referred to Analog Devices distributors. To get information on our distributors, log onto www.analog.com/salesdir/continent.asp. Hardware Manuals Printed copies of hardware reference and instruction set reference manuals can be ordered through the Literature Center or downloaded from the Analog Devices website. The phone number is 1-800-ANALOGD (1-800-262-5643). The manuals can be ordered by a title or by product number located on the back cover of each manual. Data Sheets All data sheets can be downloaded from the Analog Devices website. As a general rule, printed copies of data sheets with a letter suffix (L, M, N, S) can be obtained from the Literature Center at 1-800-ANALOGD (1-800-262-5643) or downloaded from the website. Data sheets without the suffix can be downloaded from the website only—no hard copies are available. You can ask for the data sheet by part name or by product number. xviii ADSP-BF561 EZ-KIT Lite Evaluation System Manual Preface If you want to have a data sheet faxed to you, the phone number for that service is 1-800-446-6212. Follow the prompts and a list of data sheet code numbers will be faxed to you. Call the Literature Center first to find out if requested data sheets are available. Contacting DSP Publications Please send your comments and recommendations on how to improve our manuals and online Help. You can contact us at [email protected]. Notation Conventions The following table identifies and describes text conventions used in this manual. conventions, which apply only to specific chapters, may L Additional appear throughout this document. Example Description Close command (File menu) or OK Text in bold style indicates the location of an item within the VisualDSP++ environment’s and boards’ menu system and user interface items. {this | that} Alternative required items in syntax descriptions appear within curly brackets separated by vertical bars; read the example as this or that. [this | that] Optional items in syntax descriptions appear within brackets and separated by vertical bars; read the example as an optional this or that. [this,…] Optional item lists in syntax descriptions appear within brackets delimited by commas and terminated with an ellipsis; read the example as an optional comma-separated list of this. PF9–0 Registers, connectors, pins, commands, directives, keywords, code examples, and feature names are in text with letter gothic font. filename Non-keyword placeholders appear in text with italic style format. ADSP-BF561 EZ-KIT Lite Evaluation System Manual xix Notation Conventions Example [ xx Description Note: A note providing information of special interest or identifying a related topic. In the online version of this book, the word Note appears instead of this symbol. Caution: A caution providing information about critical design or programming issues that influence operation of a product. In the online version of this book, the word Caution appears instead of this symbol. ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1 GETTING STARTED This chapter provides the information you need to begin using ADSP-BF561 EZ-KIT Lite evaluation system. For correct operation, install the software and hardware in the order presented in “Installation Tasks” on page 1-3. The chapter includes the following sections. • “Contents of EZ-KIT Lite Package” on page 1-1 Provides a list of the components shipped with this EZ-KIT Lite evaluation system. • “PC Configuration” on page 1-3 Describes the minimum requirements for the PC to work with the EZ-KIT Lite evaluation system. • “Installation Tasks” on page 1-3 Describes the step-by-step procedures for setting up the hardware and software. Contents of EZ-KIT Lite Package Your ADSP-BF561 EZ-KIT Lite evaluation system package contains the following items. • ADSP-BF561 EZ-KIT Lite board • EZ-KIT Lite Quick Start Guide • VisualDSP++ 3.5 Installation Quick Reference Card ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-1 Contents of EZ-KIT Lite Package • CD containing VisualDSP++ 3.5 for 16-bit processors with a limited license • CD containing: D ADSP-BF561 EZ-KIT Lite debug software D USB driver files D Example programs D ADSP-BF561 EZ-KIT Lite Evaluation System Manual (this document) • Universal 7.5V DC power supply • USB 2.0 type cable • Registration card (please fill out and return) If any item is missing, contact the vendor where you purchased your EZ-KIT Lite or contact Analog Devices, Inc. The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused EZ-KIT Lite boards in the protective shipping package. 1-2 ADSP-BF561 EZ-KIT Lite Evaluation System Manual Getting Started PC Configuration For correct operation of the VisualDSP++ software and the EZ-KIT Lite, your computer must have the minimum configuration: Windows 98, Windows 2000, Windows XP Intel (or comparable) 166 MHz processor VGA Monitor and color video card 2-button mouse 50 MB free on hard drive 32 MB RAM Full-speed USB port CD-ROM Drive [ EZ-KIT Lite does not run under Windows 95 or Windows NT. Installation Tasks The following task list is provided for the safe and effective use of the ADSP-BF561 EZ-KIT Lite. Follow the instructions in the presented order to ensure correct operation of your software and hardware. 1. VisualDSP++ and EZ-KIT Lite software installation 2. VisualDSP++ license installation and registration 3. EZ-KIT Lite hardware setup 4. EZ-KIT Lite USB driver installation 5. USB driver installation verification 6. VisualDSP++ startup ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-3 Installation Tasks Installing VisualDSP++ and EZ-KIT Lite Software The ADSP-BF561 EZ-KIT Lite Update CD installs all of the files necessary to use the EZ-KIT Lite. The ADSP-BF561 EZ-KIT Lite requires the VisualDSP++ 3.5 for 16-bit processors software (included in the package) pre-installed on your PC. To install the ADSP-BF561 EZ-KIT Lite software: 1. If VisualDSP++ 3.5 for 16-bit processors is installed already on your system, go to step 2. If VisualDSP++ 3.5 for 16-bit processors is not installed on your system, install the software prior to installing the ADSP-BF561 EZ-KIT Lite evaluation system. Refer to the VisualDSP++ 3.5 Installation Quick Reference Card for instructions. 2. Insert the ADSP-BF561 EZ-KIT Lite installation CD into the CD-ROM drive. 3. If Autoplay is enabled on your PC, you see the Install Shield Wizard Welcome screen. Otherwise, choose Run from the Start menu, and enter D:\Update.exe in the Open field, where D is the name of your local CD-ROM drive. 4. Follow the on-screen instructions to continue installing the software. 5. When the EZ-KIT Lite installs, the Wizard Completed screen appears. Click Finish. 1-4 ADSP-BF561 EZ-KIT Lite Evaluation System Manual Getting Started Installing and Registering VisualDSP++ License VisualDSP++ and EZ-KIT Lites are licensed products. You may run only one copy of the software for each license purchased. Once a new copy of the VisualDSP++ or EZ-KIT Lite software is installed on your PC, you must install, register, and validate your licence. The VisualDSP++ 3.5 Installation Quick Reference Card included in your package will guide you through the licence installation and registration process (refer to Tasks 1, 2, and 3). Setting Up EZ-KIT Lite Hardware The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused EZ-KIT Lite boards in the protective shipping package. The ADSP-BF561 EZ-KIT Lite board is designed to run outside your personal computer as a stand-alone unit. You do not have to open your computer case. To connect the EZ-KIT Lite board: 1. Remove the EZ-KIT Lite board from the package. Be careful when handling the board to avoid the discharge of static electricity, which may damage some components. 2. Figure 1-1 shows the default jumper settings, DIP switch, connector locations, and LEDs used in installation. Confirm that your board is set up in the default configuration before continuing. ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-5 Installation Tasks Figure 1-1. EZ-KIT Lite Hardware Setup 3. Plug the provided power supply into J4 on the EZ-KIT Lite board. Visually verify that the green power LED (J7) is on. Also verify that the two red reset LEDs (LED2 and LED3) go on for a moment and then go off. 4. Connect one end of the USB cable to an available full speed USB port on your PC and the other end to J5 on the ADSP-BF561 EZ-KIT Lite board. 1-6 ADSP-BF561 EZ-KIT Lite Evaluation System Manual Getting Started Installing EZ-KIT Lite USB Driver The EZ-KIT Lite evaluation system installed on the following platforms requires one full-speed USB port. • “Windows 98 USB Driver” on page 1-8 describes the installation on Windows 98. • “Windows 2000 USB Driver” on page 1-12 describes the installation on Windows 2000. • “Windows XP USB Driver” on page 1-13 describes the installation on Windows XP. The USB driver used by the debug agent is not Microsoft certified because it is intended for a development or laboratory environment, not a commercial environment. ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-7 Installation Tasks Windows 98 USB Driver Before using the ADSP-BF561 EZ-KIT Lite for the first time, the Windows 98 USB driver must first be installed. To install the USB driver: 1. Insert the CD into the CD-ROM drive. The connection of the device to the USB port activates the Windows 98 Add New Hardware Wizard, as shown in Figure 1-2. Figure 1-2. Windows 98 – Add New Hardware Wizard 2. Click Next. 1-8 ADSP-BF561 EZ-KIT Lite Evaluation System Manual Getting Started 3. Select Search for the best driver for your device, as shown in Figure 1-3. Figure 1-3. Windows 98 – Searching for Driver 4. Click Next. 5. Select CD-ROM drive, as shown in Figure 1-4. Figure 1-4. Windows 98 – Searching for CD-ROM ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-9 Installation Tasks 6. Click Next. Windows 98 locates the WmUSBEz.inf file on the installation CD, as shown in Figure 1-5. Figure 1-5. Windows 98 – Locating Driver 7. Click Next. The Coping Files dialog box appears (Figure 1-6). Figure 1-6. Windows 98 – Searching for .SYS File 1-10 ADSP-BF561 EZ-KIT Lite Evaluation System Manual Getting Started 8. Click Browse. The Open dialog box, shown in Figure 1-7, appears on the screen. Figure 1-7. Windows 98 – Opening .SYS File 9. In Drives, select your CD-ROM drive. 10. Click OK. The Copying Files dialog box (Figure 1-8) appears. Figure 1-8. Windows 98 – Copying .SYS File ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-11 Installation Tasks 11. Click OK. The driver installation is now complete, as shown in Figure 1-9. Figure 1-9. Windows 98 – Completing Software Installation 12. Click Finish to exit the wizard. Verify the installation by following the instructions in “Verifying Driver Installation” on page 1-15. Windows 2000 USB Driver VisualDSP++ 3.5 installation software pre-installs the necessary drivers for the EZ-KIT Lite. The install also upgrades an older driver if such is detected in the system. to running the VisualDSP++ 3.5 installer, ensure there are no [ Prior other Hardware Wizard windows running in the background. If there are any wizard windows running, close them before starting the installer. 1-12 ADSP-BF561 EZ-KIT Lite Evaluation System Manual Getting Started To install the USB driver: 1. If VisualDSP++ 3.5 is already installed on your system, go to step 2. Otherwise, run VisualDSP++ 3.5 installation. Refer to the VisualDSP++ 3.5 Installation Quick Reference Card for a detailed installation description. 2. Connect the EZ-KIT Lite device to your PC’s USB port. Windows 2000 automatically detects an EZ-KIT device and automatically installs the appropriate driver for the device. 3. Verify the installation by following the instructions in “Verifying Driver Installation” on page 1-15. Windows XP USB Driver VisualDSP++ 3.5 installation software pre-installs the necessary drivers for the EZ-KIT Lite. The install also upgrades an older driver if such is detected in the system. to running the VisualDSP++ 3.5 installer, ensure there are no [ Prior other Hardware Wizard windows running in the background. If there are any wizard windows running, close them before starting the installer. To install the USB driver: 1. If VisualDSP++ 3.5 is already installed on your system, go to step 2. Otherwise, run VisualDSP++ 3.5 installation. Refer to the VisualDSP++ 3.5 Installation Quick Reference Card for a detailed installation description. ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-13 Installation Tasks 2. Connect the EZ-KIT Lite device to your PC’s USB port. By connecting the device to the USB port you activate the Windows XP Found New Hardware Wizard, shown in Figure 1-10. Figure 1-10. Windows XP – Found New Hardware Wizard 3. Select Install the software automatically (Recommended) and click Next. When Windows XP completes the driver installation for the device, a window shown in Figure 1-11 appears on the screen. Figure 1-11. Windows XP – Completing Driver Installation 1-14 ADSP-BF561 EZ-KIT Lite Evaluation System Manual Getting Started 4. Verify the installation by following the instructions in “Verifying Driver Installation”. Verifying Driver Installation Before you use the EZ-KIT Lite evaluation system, verify that the USB driver software is installed properly: 1. Ensure that the USB cable is connected to the evaluation board and the PC. 2. Verify that the yellow USB monitor LED (LED4) is lit. This signifies that the board is communicating properly with the host PC and is ready to run VisualDSP++. 3. Verify that the USB driver software is installed properly. Open Windows Device Manager and verify that ADSP-BF561 EZ-KIT Lite shows under ADI Development Tools with no exclamation point, as in Figure 1-12. Figure 1-12. Device Manager Window ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-15 Installation Tasks Lite on Windows 98, disconnect the USB [ Ifcableusingfroman theEZ-KIT board before booting the PC. When Windows 98 is booted and you are logged on, re-connect the USB cable to the board. The operation should continue normally from this point. Starting VisualDSP++ First, verify that the yellow USB monitor LED (LED4, located near the USB connector) is lit. This signifies that the board is communicating properly with the host PC and is ready to run VisualDSP++. If you do not have an existing EZ-KIT Lite session, create one based on the existing EZ-KIT Lite platform template: 1. From the Start menu, choose Programs-->Analog Devices-->VisualDSP++ 3.5 for 16-bit Processors-->VisualDSP++ Configurator. The VisualDSP++ Configurator dialog box appears on the screen. 2. Double click the ADSP-BF561 EZ-KIT Lite in the list of available Platform Templates. The Platform Properties dialog box for the chosen platform appears on the screen. 3. Click OK to close the Platform Properties dialog box. 4. Click OK to close the VisualDSP++ Configurator dialog box. Your new EZ-KIT Lite session is set. Lastly, open your new or existing EZ-KIT Lite session: 1. From the Start menu, choose Programs–>Analog Devices–>VisualDSP++ 3.5 for 16-bit Processors–>VisualDSP++ Environment. If you running VisualDSP++ for the first time, press the Ctrl key to bring up the Session List dialog box. Otherwise, the last opened session appears on the screen (skip the rest of the procedure). 2. Click the New Session button. 1-16 ADSP-BF561 EZ-KIT Lite Evaluation System Manual Getting Started 3. In Debug Target, select Blackfin Emulators/EZ-KITs. In Platform, select the platform you created in VisualDSP++ Configurator. In Multiprocessor System (the ADSP-BF561 EZ-KIT Lite is an example of a multiprocessor system), select a core for your session. 4. Click OK to return to the Session List. 5. From the Session List dialog box, highlight the session and click Activate. ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-17 Installation Tasks 1-18 ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2 USING EZ-KIT LITE This chapter provides specific information to assist you with developing programs for the ADSP-BF561 EZ-KIT Lite evaluation system. This information appears in the following sections. • “EZ-KIT Lite License Restrictions” on page 2-2 Describes the restrictions of the VisualDSP++ license shipped with the EZ-KIT Lite. • “Using External Memory” on page 2-2 Defines the ADSP-BF561 EZ-KIT Lite’s external memory map. • “Using LEDs and Push Buttons” on page 2-5· Describes the board’s LEDs and push buttons. • “Using Audio” on page 2-6 Describes the board’s audio interface. • “Using Video” on page 2-7 Describes the board’s video interface. • “Example Programs” on page 2-8 Provides information about the example programs included in the ADSP-BF561 EZ-KIT Lite evaluation system. • “Using Background Telemetry Channel” on page 2-8 Highlights the advantages of the Background Telemetry Channel feature of VisualDSP++. • “Using EZ-KIT Lite VisualDSP++ Interface” on page 2-9 Describes the target options facilities of the EZ-KIT Lite system. ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-1 EZ-KIT Lite License Restrictions For more detailed information about programming the ADSP-BF561 Blackfin processor, see the documents referred to as “Related Documents”. EZ-KIT Lite License Restrictions The license shipped with the EZ-KIT Lite imposes the following restrictions. • The size of a user program is limited to 41 KB of the ADSP-BF561 processor’s internal memory space. • No connections to a simulator or emulator session are allowed. • The EZ-KIT Lite hardware must be connected and powered up in order to use VisualDSP++ with a kit license. Using External Memory EZ-KIT Lite board includes two types of external memory, 64-MB SDRAM and 8-MB Flash. Table 2-1 shows the memory map of these devices. The complete configuration of the ADSP-BF561 processor internal SRAM is detailed in Figure 2-1. Table 2-1. EZ-KIT Lite External Memory Map Start Address End Address Description 0x00000000 0x3FFFFFF SDRAM Bank 0; see “Using External Memory” on page 2-2 0x20000000 0x207FFFFF ASYNC Memory Bank 0; see “Using External Memory” on page 2-2. All other locations 2-2 Not used ADSP-BF561 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite CORE A MEMORY MAP CORE B MEMORY MAP 0XFFFF FFFF CORE MMR REGISTERS 0XFFE0 0000 0XFFB0 1000 0XFFB0 0000 0XFFA1 4000 0XFFA1 0000 0XFFA0 4000 0XFFA0 0000 0XFF90 8000 0XFF90 4000 0XFF90 0000 0XFF80 8000 0XFF80 4000 0XFF80 0000 RESERVED L1 SCRATCHPAD SRAM (4K) RESERVED L1 INSTRUCTION SRAM/CACHE (16K) RESERVED L1 INSTRUCTION SRAM (16K) L1 DATA BANK B SRAM (16K) RESERVED L1 DATA BANK A SRAM/CACHE (16K) L1 DATA BANK A SRAM (16K) RESERVED L1 SCRATCHPAD SRAM (4K) 0XFF70 0000 RESERVED 0XFF61 4000 L1 INSTRUCTION SRAM/CACHE (16K) 0XFF61 0000 RESERVED 0XFF60 4000 0XFF50 8000 0XFF50 4000 0XFF50 0000 0XFF40 8000 0XFF40 4000 0XFF40 0000 0XFEB2 0000 0XFEB0 0000 0XEF00 0800 RESERVED RESERVED L1 DATA BANK B SRAM/CACHE (16K) 0XFF70 1000 0XFF60 0000 CORE MMR REGISTERS SYSTEM MMR REGISTERS 0XFFC0 0000 RESERVED L1 INSTRUCTION SRAM (16K) RESERVED L1 DATA BANK B SRAM/CACHE (16K) L1 DATA BANK B SRAM (16K) RESERVED L1 DATA BANK A SRAM/CACHE (16K) L1 DATA BANK A SRAM (16K) RESERVED L2 SRAM (128K) RESERVED Figure 2-1. ADSP-BF561 Processor Internal Memory Map The 8 MB of Flash memory is organized as 4M x 16 bit and mapped into a ADSP-BF561 processor’s ASYNC Memory Bank 0 (~AMS0, memory select signal connects to the Flash memory’s output enable pin). The 64 MB of SDRAM is organized as 16M x 32 bits wide. The processor’s memory select pin ~SMS0 is configured for the SDRAM. Three SDRAM control registers must be initialized in order to access the SDRAM memory. When in a VisualDSP++ EZ-KIT Lite session, you can automatically configure the SDRAM registers by selecting the Use XML reset values box on the Target Options dialog box, which is accessible through the Settings ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-3 Using External Memory pull-down menu. The values for the EBIU_SDGCTL, EBIU_SDBCTL, and EBIU_SDRRC registers have been set in the ADSP-BF561.xml file found in your VisualDSP\system folder under the RegReset tag. These values can be changed to be more optimal depending on the SCLK frequency. The values in Table 2-2 are programmed by default whenever Bank 0 is accessed through the debugger (for example, when viewing memory windows or loading a program). The numbers are derived for maximum flexibility and work for a system clock frequency between 60 MHz and 133 MHz. Table 2-2. EZ-KIT Lite Session SDRAM Default Settings Register Value Function EBIU_SDGCTL 0x0091998D Calculated with SCLK = 133 MHz1s EBIU_SDBCTL 0x00000013 EBIU_SDRRC 0x000001CF Calculated with SCLK = 120 MHz The EBIU_SDGCTL register can only be written once after the processor comes out of reset. Therefore, the user code should not reinitialize this register. Clearing the Use XML reset values checkbox allows manual configuration of the EBIU registers. For more information, see “Target Options” on page 2-9. Automatic configuration of the SDRAM is not optimized for a specific SCLK frequency. Table 2-3 shows the optimized configuration for the SDRAM registers using a 120 MHz SCLK. The frequency of 120 MHz is the maximum SCLK frequency when using a 600 MHz core frequency, the maximum frequency for the EZ-KIT Lite. Only the SDRRC register needs to be modified in the user code to achieve maximum performance. Table 2-3. SDRAM Optimum Settings1 2-4 Register Value EBIU_SDGCTL 0x0091998D ADSP-BF561 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite Table 2-3. SDRAM Optimum Settings1 (Cont’d) Register Value EBIU_SDBCTL 0x00000013 EBIU_SDRRC 0x000003A0 1 SCLK = 120 MHz For more information about the memory connection on the EZ-KIT Lite, see “External Bus Interface Unit” on page 3-3. An example program is included in the EZ-KIT installation directory to demonstrate how to set up the SDRAM interface. Using LEDs and Push Buttons The EZ-KIT Lite provides four push buttons and sixteen LEDs for general-purpose IO. Sixteen LEDs labeled LED5 through LED20 are controlled by the processor’s programmable flags PF32 through PF47 (equivalent to PPI0 D15–8 and PPI1 D15-8). These LEDs are accessed through the Flag 2 registers. First, the direction must be set to output by setting the bits of the FIO2_DIR register to “1”. Then the value of the LEDs can be modified using one the FIO2_FLAG_D, FIO2_FLAG_C, FIO2_FLAG_S, or FIO2_FLAG_T registers. The four general-purpose push buttons are labeled SW6 through SW9. These are connected to the programmable flags, PF8–5. A status of each individual button can be read through the FIO0_FLAG_D register. When the corresponding bit of the register reads “1”, a switch is being pressed-on. When the switch is released, the bit reads “0”. A connection between the push button and PF input is established through the SW4 DIP switch. For information on how to disconnect the switch from the programmable flag and use the flag for something else, see “Push Button Enable Switch (SW4)”. ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-5 Using Audio An example program is included in the EZ-KIT installation directory to demonstrate the functionality of the LEDs and push buttons. Using Audio The AD1836A audio codec provides three channels of stereo audio output and two channels of multichannel 96 kHz input. The SPORT0 interface of the processor links with the stereo audio data input and output pins of the AD1836A codec. The processor is capable of transferring data to the audio codec in time-division multiplexed (TDM) or I2S mode. The I2S mode allows the codec to operate with a 96 kHz sample rate but only allows you to use two channels of output. TDM mode can operate at a maximum of 48 kHz sample rate but allows simultaneous use of all input and output channels. When using I2S mode, the TSCLK0 and RSCLK0 pins, as well as the TFS0 and RFS0 pins of the processor, must be tied together externally to the processor. This is accomplished with the SW4 DIP switch. See “Push Button Enable Switch (SW4)” on page 3-12 for more information. The AD1836A audio codec’s internal configuration registers are configured using the processor’s PF4 programmable flag pin is used as the select for this device. For more information on how to configure the multichannel codec, download the datasheet from Analog Devices website, www.analog.com. The AD1836A codec reset is controlled by the processor’s programmable flag PF15. When PF15 is “0”, the reset is asserted. When PF15 is “1”, the reset is de-asserted. Note, when PF15 is not driven (configured as input), the AD1836A reset is asserted due to the pull-down resistor. See “Programmable Flags” on page 3-4 for more information. Example programs are included in the EZ-KIT installation directory to demonstrate the AD1836A codec operation. 2-6 ADSP-BF561 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite Using Video The board supports video input and output applications. The ADV7179 video encoder provides up to three output channels of analog video, while the ADV7183A video decoder provides up to three input channels of analog video. The video encoder connects to the Parallel Peripheral Interface 1 (PPI1), while the video decoder connects to the Parallel Peripheral Interface 0, (PPI0). Each PPI interface has an individual clock that is configured by the SW5 switch’s settings. See “PPI Clock Select Switch (SW5)” on page 3-13 for more information. Both the encoder and the decoder connect to the Parallel Peripheral Interfaces (PPI input clock) of the ADSP-BF561 processor. For additional information on the video interface hardware, refer to “PPI Interfaces” on page 3-6. For the video interface to be operational, the following basic steps must be performed. 1. Configure the SW2 DIP switch as required by the application. Refer to “Video Configuration Switch (SW2)” on page 3-10 for details. 2. De-assert the video device’s reset by setting a corresponding programmable flag “High”. Note that PF14 controls the ADV7179 encoder’s reset, while PF13 controls the ADV7183A decoder’s reset. 3. If using the decoder: D D Enable device by driving programmable flag output PF2 to “0”. Select PPI0 clock; for details, refer to “PPI Clock Select Switch (SW5)” on page 3-13. 4. Program internal registers of the video device in use. Both video encoder and decoder use a 2-wire serial interface to access internal registers. The PF0 programmable flag functions as a serial clock ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-7 Example Programs (SCL), and PF1 functions as a serial data (SDAT). 5. Program the ADSP-BF561 processor’s PPI interfaces (configuration registers, DMA, and so on). Example programs are included in the EZ-KIT installation directory to demonstrate the capabilities of the video interface. Example Programs Example programs are provided with the ADSP-BF561 EZ-KIT Lite to demonstrate various capabilities of the evaluation board. These programs are installed with the EZ-KIT Lite software and can be found in \…\VisualDSP\Blackfin\EZ-KITs\ADSP-BF561\Examples. Please refer to the readme file provided with each example for more information. Using Background Telemetry Channel The ADSP-BF561 USB debug agent supports the Background Telemetry Channel (BTC), which facilitates data exchange between VisualDSP++ and the processor without interrupting DSP execution. The BTC allows to view a variable as it is updated or changed, all while the processor continues to execute. For increased performance of the BTC, including faster reading and writing, please check out our latest line of DSP emulators at www.analog.com/Analog_Root/productPage/productHome/0,2121,EMULATORS,00.html. For more information about the Background Telemetry Channel, see the VisualDSP++ 3.5 User’s Guide for 16-Bit Processors or online Help. 2-8 ADSP-BF561 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite Using EZ-KIT Lite VisualDSP++ Interface This section provides information on the following parts of the VisualDSP++ graphical user interface: • “Target Options” on page 2-9 • “Restricted Software Breakpoints” on page 2-12 Target Options Choosing Target Options from the Settings menu opens the Target Options dialog box (Figure 2-2). Use target options to control certain aspects of the processor on the ADSP-BF561 EZ-KIT Lite evaluation system. Figure 2-2. Target Options Dialog Box Reset Options Reset options control how the processor behaves when a reset occurs. The reset options are described in Table 2-4. ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-9 Using EZ-KIT Lite VisualDSP++ Interface Table 2-4. Reset Options Option Description Core reset Resets the core when the debugger executes a reset. System reset Resets the peripherals when the debugger executes a reset. On Emulator Exit This target option controls processor behavior when VisualDSP++ relinquishes DSP control (for example, when exiting VisualDSP++). The option is described in Table 2-5. Table 2-5. On Emulator Exit Target Options Option Description On Emulator Exit Determines the state the DSP is left in when the board relinquishes control of the DSP: Reset DSP and Run causes the DSP to reset and begin execution from its reset vector location. Run from current PC causes the DSP to begin running from its current location. Stall the DSP resets the DSP and then writes a JUMP 0 to the first location in internal memory so the DSP is stuck in a tight loop after exiting. XML File These read-only fields show the version information for the processor-specific XML file, \…\VisualDSP\system\ADSP-BF561.xml, as well as the parser program (Table 2-6). Table 2-6. XML File Information Option Description XML File Version The version of the processor’s XML file. XML Parser Version The version of the program that parses the XML file. 2-10 ADSP-BF561 EZ-KIT Lite Evaluation System Manual Using EZ-KIT Lite Other Options Table 2-7 describes other available target options. Table 2-7. Miscellaneous Target Options Option Description Reset before loading executable Resets registers before loading a DSP executable. Clear this option when DSP registers must not change to their reset values when a file load occurs. Verify all writes to target memory Validates all memory writes to the DSP. After each write, a read is performed and the values are checked for a matching condition. Enable this option during initial program development to locate and fix initial build problems (such as attempting to load data into non-existent memory). Clear this option to increase performance while loading executable files, since VisualDSP++ does not perform the extra reads that are required to verify each write. Reset cycle counters on run Resets the cycle count registers to zero before a Run command is issued. Select this option to count the number of cycles executed between breakpoints in a program. Use opcode scan method Enables the debugger to use a highly optimized JTAG scan method. This provides extremely fast communication between the EZ-KIT Lite and the processor. In certain circumstances, this causes JTAG scan failures. Typically, JTAG scan failures occur when using this method combined with debugging situations that hold off or stall the core (such as debugging, loading, or viewing external memory). Clearing this option uses a less optimized JTAG scan method. Use XML reset values Uses a section in the processor-specific XML file located in the folder. The file defines registers that are to be reset to certain values when a reset is done through VisualDSP++. VisualDSP/system ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-11 Using EZ-KIT Lite VisualDSP++ Interface Restricted Software Breakpoints The EZ-KIT Lite development system restricts breakpoint placement when certain conditions are met. That is, under some conditions, breakpoints cannot be placed effectively. Such conditions depend on bus architecture, pipeline depth, and ordering of the EZ-KIT Lite and its target processor. 2-12 ADSP-BF561 EZ-KIT Lite Evaluation System Manual 3 EZ-KIT LITE HARDWARE REFERENCE This chapter describes the hardware design of the ADSP-BF561 EZ-KIT Lite board. The following topics are covered. • “System Architecture” on page 3-2 Describes the configuration of the ADSP-BF561EZ-KIT Lite and explains how the board components interface with the processor. • “Jumper and DIP Switch Settings” on page 3-10 Shows the location and describes the function of the configuration jumpers and DIP switches. • “LEDs and Push Buttons” on page 3-14 Shows the location and describes the function of the LEDs and push buttons. • “Connectors” on page 3-17 Shows the location and gives the part number for all of the connectors on the board. Also, the manufacturer and part number information is given for the mating parts. ADSP-BF561 EZ-KIT Lite Evaluation System Manual 3-1 System Architecture System Architecture This section describes the processor’s configuration on the EZ-KIT Lite board. Figure 3-1. System Architecture The EZ-KIT Lite has been designed to demonstrate the capabilities of the ADSP-BF561 Blackfin processor. The processor has IO voltage of 3.3V. The core voltage and the core clock rate can be set on the fly by the processor. The input clock is 30 MHz. 3-2 ADSP-BF561 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference External Bus Interface Unit The External Bus Interface Unit (EBIU) connects an external memory to the ADSP-BF561 processor. It includes a 32-bit wide data bus, an address bus (A25–A2), and a control bus. All 8-bit, 16-bit, and 32-bit accesses are supported. On the EZ-KIT Lite board, the EBI unit is connected to SDRAM and Flash memory. For more information on using the external memory see “Using External Memory” on page 2-2. All of the address, data, and control signals are available externally via the extender connectors (J3–J1). The pinout of these connectors can be found in Appendix B, “Schematics” on page B-1. SPORT0 Audio Interface The SPORT0 interface connects to the AD1836A audio codec, the SPORT connector (P3), and the expansion interface. The AD1836A codec uses both the primary and secondary data transmit and receive pins to input and output data from the audio input and outputs. The pinout of the SPORT connector and the expansion interface connectors can be found in Appendix B, “Schematics” on page B-1. SPI Interface The processor’s Serial Peripheral Interconnect (SPI) interface connects to the AD1836A audio codec and the expansion interface. The SPI connection to the AD1836A is used to access the control registers of the device. The PF4 flag of the processor acts as the devices select for the SPI port. The SPI signals are available on the expansion interface. The pinout for the expansion interface can be found in Appendix B, “Schematics” on page B-1. ADSP-BF561 EZ-KIT Lite Evaluation System Manual 3-3 System Architecture Programmable Flags The processor has 48 programmable flag pins (PFs). Many of the flags have a multiple functionality, depending on the processor’s setup. Table 3-1 shows how the programmable flag pins are used on the EZ-KIT Lite. Table 3-1. Programmable Flag Connections DSP PF Pin DSP Function 3-4 EZ-KIT Function PF0 SPI Select S, Timer 0 Serial clock for programming ADV7179 video encoder and ADV7183A video decoder. PF1 SPI Select 1, Timer 1 Serial data for programming ADV7179 video encoder and ADV7183A video decoder. PF2 SPI Select 2, Timer 2 ADV7183A video decoder’s ~OE. PF3 SPI Select 3, Timer 3 ADV7183A Field pin. See “Video Configuration Switch (SW2)” on page 3-10. PF4 SPI Select 4, Timer 4 AD1836A audio codec’s SPI Select. PF5 SPI Select 5, Timer 5 Push Button ( SW6). See “Using LEDs and Push Buttons” on page 2-5 and “Push Button Enable Switch (SW4)” on page 3-12 for information on how to disable the push button. PF6 SPI Select 6, Timer 6 Push Button ( SW7). See “Using LEDs and Push Buttons” on page 2-5 and “Push Button Enable Switch (SW4)” on page 3-12 for information on how to disable the push button. PF7 SPI Select 7, Timer 7 Push Button ( SW8). See “Using LEDs and Push Buttons” on page 2-5 and “Push Button Enable Switch (SW4)” on page 3-12 for information on how to disable the push button. PF8 Push Button (SW9). See “Using LEDs and Push Buttons” on page 2-5 and “Push Button Enable Switch (SW4)” on page 3-12 for information on how to disable the push button. PF9–PF12 Not used ADSP-BF561 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference Table 3-1. Programmable Flag Connections (Cont’d) DSP PF Pin DSP Function EZ-KIT Function PF13 ADV7183A video decoder’s reset PF14 ADV7179 video encoder’s reset PF15 AD1836 codec’s reset PF16 Sport 0 Transmit Frame Sync PF17 Sport 0 Transmit Data Secondary PF18 Sport 0 Transmit Data Primary PF19 Sport 0 Receive Frame Sync PF20 Sport 0 Receive Data Secondary PF21 Sport 1 Transmit Frame PF22 Sport 1 Transmit Data Secondary PF23 Sport 1 Transmit Data Primary PF24 Sport 1 Receive Frame Sync PF25 Sport 1 Receive Data Secondary PF26 UART Transmit PF27 UART Receive PF28 Sport 0 Receive Serial Clock PF29 Sport 0 Transmit Serial Clock PF30 Sport 1 Receive Serial Clock PF31 Sport 1 Transmit Serial Clock PF39–32 PPI1 data 15–8 LED20–13 PF47–40 PPI0 data 15–8 LED12–5 ADSP-BF561 EZ-KIT Lite Evaluation System Manual 3-5 System Architecture PPI Interfaces The ADSP-BF561 processor employs two independent Parallel Peripheral Interfaces (PPIs), PPI0 and PPI1. Each PPI interface is a half-duplex, bi-directional bus consisting of 16 bits of data, a dedicated input clock, and synchronization signals. The ADSP-BF561 EZ-KIT Lite board utilizes the PPI interfaces for video input and video output. The PPI0 interface is configured to input video data from the ADV7183A video decoder device: bits 7–0 connect to the video decoder’s data outputs. The PPI1 interface is configured to output video data to the ADV7179 video encoder device: bits 7–0 connect to the video encoder’s data inputs. Each PPI interface has a dedicated clock input configured independently by the SW5 switch. The clock source can be one of the following: 27 MHz crystal oscillator, ADV7183A video decoder’s clock output, or external clock from the expansion interface. See “PPI Clock Select Switch (SW5)” on page 3-13 for more information about the switch. The SW2 switch allows flexible connectivity between dedicated synchronization IOs (SYNC1 and SYNC2 of each PPI interface) and the encoder’s and decoder’s horizontal and vertical synchronization pins. See “Video Configuration Switch (SW2)” on page 3-10 for more information about the switch. For a detailed description of the ADSP-BF561 processor’s PPI interfaces, refer to the ADSP-BF561 Blackfin Processor Hardware Reference. Table 3-2 describes the PPI pins and their use on the EZ-KIT Lite board. Table 3-2. PPI Connections DSP PPI Pin EZ-KIT Function PPI0 bits 7–0 ADV7183A data outputs P15–8 PPI1 bits 7–0 ADV7179 data inputs P7–0 PPI0 SYNC1 3-6 Other DSP Function Timer 8 ADV7179 HSYNC. For more information, see “Video Configuration Switch (SW2)” on page 3-10. ADSP-BF561 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference Table 3-2. PPI Connections (Cont’d) DSP PPI Pin Other DSP Function EZ-KIT Function PPI0 SYNC2 Timer 9 ADV7179 VSYNC. For more information, see “Video Configuration Switch (SW2)” on page 3-10. PPI0 Clock A choice of ADV7183A output clock, a local 27 MHz oscillator, or an external clock from ADSP-BF533/BF561 EZ-KIT Extender 1 board. PPI1 SYNC1 Timer 10 ADV7183A HSYNC. For more information, see “Video Configuration Switch (SW2)” on page 3-10. PPI1 SYNC2 Timer 11 ADV7183A VSYNC. For more information, see “Video Configuration Switch (SW2)” on page 3-10. PPI1 Clock A choice of ADV7183A output clock, a local 27 MHz oscillator, or an external clock from ADSP-BF53x/BF561 EZ-Extender 1. Video Output (PPI1) The PPI1 interface is configured as output and connects to the on-board video encoder device, ADV7179. The ADV7179 encoder generates three analog video channels on DAC A, DAC B, and DAC C. The PPI1 bits 7–0 connect to P7–0 of the encoder’s pixel inputs. The encoder’s input clock is fixed and comes from an on-board 27 MHz oscillator. The encoder’s synchronization signals, HSYNC and VSYNC, can be configured as inputs or outputs. Video Blanking control signal is at level “1”. The HSYNC and VSYNC signals can connect to the ADSP-BF561 processor’s PPI1 interface SYNC1 and SYNC2 via the SW2 switch, as described in “Video Configuration Switch (SW2)” on page 3-10. ADSP-BF561 EZ-KIT Lite Evaluation System Manual 3-7 System Architecture Video Input (PPI0) The PPI0 interface is configured as input and connect to the on-board video decoder device, ADV7183A. The ADV7183A decoder receives three analog video channels on AIN1, AIN4, and AIN5 input. The decoder’s pixel data outputs P15–8 drive the PPI0 inputs 8–0. The decoder’s 27 MHz pixel clock output can be selected to drive any of the PPI clocks, as shown in Table 3-7 on page 3-13. Synchronization outputs of the decoder, HS/HACTIVE, VS/VACTIVE, and FIELD can connect to the processor’s PPI1 SYNC1, SYNC2, and PF3 flag via the SW2 DIP switch, as described in “Video Configuration Switch (SW2)” on page 3-10. UART Port The processor’s Universal Asynchronous Receiver/Transmitter (UART) port connects to the ADM3202 RS232 line driver as well as to the expansion interface. The RS232 line driver is attached to the DB9 male connector, allowing you to interface with a PC or other serial device. Expansion Interface The expansion interface consists of the three 90-pin connectors, J3–1. Table 3-3 shows the interfaces each connector provides. For the exact pinout of these connectors, refer to Appendix B, “Schematics” on page B-1. The mechanical dimensions of the connectors can be obtained from Technical or Customer Support. 3-8 ADSP-BF561 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference Table 3-3. Connector Interfaces Connector Interfaces J1 5V, G ND, Address, Data, PPI0 3–0, PF15–6, PF4 J2 3.3V, GND, SPI, NMI, PPI0 SYNC3–1, SPORT0, SPORT1, PF15–0, EBUI control signals J3 5V, 3.3V, GND, UART, PPI1 15–0, Reset, Video control signals Limits to the current and to the interface speed must be taken into consideration when you use the expansion interface. The maximum current limit is dependent on the capabilities of the used regulator. Additional circuitry can also add extra loading to signals, decreasing their maximum effective speed. Devices does not support and is not responsible for the [ Analog effects of additional circuitry. JTAG Emulation Port The JTAG emulation port allows an emulator to access the processor’s internal and external memory through a 6-pin interface. The JTAG emulation port of the processor also connects to the USB debugging interface. When an emulator connects to the board at P4, the USB debugging interface is disabled. See “JTAG (P4)” on page 3-20 for more information about the JTAG connector. To learn more about available emulators, contact Analog Devices (see “Product Information”). ADSP-BF561 EZ-KIT Lite Evaluation System Manual 3-9 Jumper and DIP Switch Settings Jumper and DIP Switch Settings This section describes the operation of the jumpers and DIP switches. The jumper and DIP switch locations are shown in Figure 3-2. Figure 3-2. DIP Switch Locations Video Configuration Switch (SW2) The video configuration switch (SW2) controls how some video signals from the ADV7183A video decoder and ADV7179 video encoder are routed to the processor’s PPIs. The switch also determines if the PF2 pin controls the ~OE signal of the ADV7183A video decoder outputs. Table 3-4 shows which processor’s signals are connected to the encoder and decoder when in the “ON” position. 3-10 ADSP-BF561 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference Table 3-4. Video Configuration Switch (SW2) Switch Position (Default) Processor Signal Video Signal 1 (OFF) PPI1 SYNC1 ADV7179 2 (OFF) PPI0 SYNC1 ADV7183A 3 (OFF) PPI1 SYNC2 ADV7183A 4 (OFF) PPI1 SYNC2 ADV7179 5 (OFF) PF3 (FIELD) ADV7183A 6 (ON) PF2 ADV7183A Positions 1 thorough 5 of SW2 determine how and if the SYNC1, SYNC2, and FIELD control signals of the PPI0 and PPI1 interfaces are routed to the processor’s PPIs. In standard configuration of the encoder and decoder, this is not necessary because the processor is capable of reading the embedded control information, which is in the data stream. Position 6 of SW2 determines whether PF2 connects to the ~OE signal of the ADV7183A. When the switch is “OFF”, PF2 can be used for other operations, and the decoder output enable is held “HIGH” with a pull-up resistor. Boot Mode Switch (SW3) The SW3 switch positions 1 and 2 set the ADSP-BF561 processor’s boot mode as described in Table 3-5. Position 3 sets the processor’s PLL on boot. When SW3 position 3 is “ON”, the PLL is in bypass. Table 3-5. Boot Mode Select Switch (SW3) Position 1 BMODE0 Position 2 BMODE1 Boot Mode ON ON Reserved ON OFF Flash memory ADSP-BF561 EZ-KIT Lite Evaluation System Manual 3-11 Jumper and DIP Switch Settings Table 3-5. Boot Mode Select Switch (SW3) (Cont’d) Position 1 BMODE0 Position 2 BMODE1 Boot Mode OFF ON 8-bit SPI PROM OFF OFF 16-bit SPI PROM Push Button Enable Switch (SW4) The push button enable switch (SW4) positions 1 through 4 allow to disconnect the drivers associated with the push buttons from the PF pins of the processor. Positions 5 and 6 connect the transmit and receive frame syncs and clocks of SPORT0. This is important when the AD1836A video decoder and the processor are communicating in I2S mode. Table 3-6 shows which PF is driven when the switch is in the “ON” position. Table 3-6. Push Button Enable Switch (SW4) Switch Position Default Setting Pin # Signal (Side 1) Pin # Signal (Side 2) 1 ON 1 SW6 12 PF5 2 ON 2 SW7 11 PF6 3 ON 3 SW8 10 PF7 4 ON 4 SW9 9 PF8 5 OFF 5 TFS0 8 RFS0 6 OFF 6 RSCLK0 7 TSCLK0 3-12 ADSP-BF561 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference PPI Clock Select Switch (SW5) The SW5 switch controls a clock selection of PPI interfaces, as described in Table 3-7 and Table 3-8. Table 3-7. PPICLK1 Clock Source Setup SW5 Position 1 PPI0_CKSEL0 SW5 Position 2 PPI0_CKSEL1 PPICLK1 Source ON ON 27 MHz Oscillator (default) OFF ON ADV7183 Clock Out X OFF Expansion Interface Table 3-8. PPICLK2 Clock Source Setup SW5 Position 3 PPI1_CKSEL0 SW5 Position 4 PPI1_CKSEL1 PPICLK2 Source ON ON 27 MHz Oscillator (default) OFF ON ADV7183 Clock Out X OFF Expansion Interface Test DIP Switches (SW10, SW11) Two DIP switches (SW10 and SW11) are located on the bottom of the board. The switches are used only for testing and should be in the “OFF” position. ADSP-BF561 EZ-KIT Lite Evaluation System Manual 3-13 LEDs and Push Buttons LEDs and Push Buttons This section describes the functionality of the LEDs and push buttons. Figure 3-3 shows the locations of the LEDs and push buttons on the board. Figure 3-3. LED and Push Button Locations Reset Push Button (SW1) The RESET push button resets all of the ICs on the board. One exception is the USB interface chip (U34). The chip is not being reset when the push button is pressed after the USB cable has been plugged in and communication with the PC has been initialized correctly. Once communication is initialized, the only way to reset the USB is by powering down the board. 3-14 ADSP-BF561 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference Programmable Flag Push Buttons (SW9–6) Four push buttons, SW9–6, are provided for general-purpose user input. The buttons connect to the processor’s programmable flag pins PF8–5. The push buttons are active “HIGH” and, when pressed, send a High (1) to the processor. Refer to “Using LEDs and Push Buttons” on page 2-5 for more information on how to use the PFs when programming the processor. The push button enable switch (SW4) is capable of disconnecting the push buttons from the PF (refer to “Push Button Enable Switch (SW4)” on page 3-12). The programmable flag signals and their corresponding switches are shown in Table 3-9. Table 3-9. Programmable Flag Switches DSP Programmable Flag Pin Push Button Reference Designator PF5 SW6 PF6 SW7 PF7 SW8 PF8 SW9 Power LED (J7) When J7 is lit (green), it indicates that power is being properly supplied to the board. Reset LEDs (LED2, LED3) When LED2 is lit, it indicates that the master reset of all the major ICs is active. When LED3 is lit, the USB interface chip (U34) is being reset. The USB chips only reset on power-up, or if USB communication has not been initialized. ADSP-BF561 EZ-KIT Lite Evaluation System Manual 3-15 LEDs and Push Buttons USB Monitor LED (LED4) The USB monitor LED (LED4) indicates that USB communication has been initialized successfully and you may connect to the processor using a VisualDSP++ EZ-KIT Lite session. This should take approximately 15 seconds. If the LED does not light, try cycling power on the board and/or reinstalling the USB driver (see “Installing EZ-KIT Lite USB Driver” on page 1-7). User LEDs (LED12–5, LED20–13) Sixteen LEDs are connected to the ADSP-BF561 processor’s programmable flags. Eight LEDs labeled LED5 through LED12 are controlled by programmable flags PF40 through PF47 (equivalent to PPI0 D15–8). Eight LEDs labeled LED13 through LED20 are controlled by programmable flags PF32 through PF39 (equivalent to PPI1 D15–8). To learn how to use the Flash memory when programming the LEDs, refer to “Using LEDs and Push Buttons” on page 2-5. Table 3-10. User LEDs LED Reference Designator Flash Port Name LED Reference Designator Flash Port Name LED5 PB40 LED13 PB32 LED6 PB41 LED14 PB33 LED7 PB42 LED15 PB34 LED8 PB43 LED16 PB35 LED9 PB44 LED17 PB36 LED10 PB45 LED18 PB37 LED11 PB46 LED19 PB38 LED12 PB47 LED20 PB39 3-16 ADSP-BF561 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference Connectors This section describes the connector functionality and provides information about mating connectors. The locations of the connectors are shown in Figure 3-4. Figure 3-4. Connector Locations Expansion Interface (J1, J2, J3) Three board-to-board connector footprints provide signals for most of the processor’s peripheral interfaces. The connectors are located at the bottom of the board. For more information about the expansion interface, see on page 3-8. For the availability and pricing of the J1, J2, and J3 connectors, contact Samtec. ADSP-BF561 EZ-KIT Lite Evaluation System Manual 3-17 Connectors Part Description Manufacturer Part Number 90 Position 0.05" Spacing, SMT (J1, J2, J3) Samtec SFC-145-T2-F-D-A Mating Connector 90 Position 0.05” Spacing (Through Hole) Samtec TFM-145-x1 Series 90 Position 0.05” Spacing (Surface Mount) Samtec TFM-145-x2 Series 90 Position 0.05” Spacing (Low Cost) Samtec TFC-145 Series Audio (J4, J5) Part Description Manufacturer Part Number 2x2 RCA Jacks (J4) SWITCHCRAFT PJRAS2X2S01 3x2 RCA Jacks (J5) SWITCHCRAFT PJRAS3X2S01 Mating Connector Two channel RCA interconnect cable Monster Cable BI100-1M Video (J6) Part Description Manufacturer Part Number 3x2 RCA Jacks (J6) SWITCHCRAFT PJRAS3X2S01 Power (J7) The power connector provides all of the power necessary to operate the EZ-KIT Lite board. The power connector supplies DC power to the board. The following table shows the power connector pinout. 3-18 ADSP-BF561 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference Part Description Manufacturer Part Number 2.5 mm Power Jack (J7) SWITCHCRAFT RAPC712 Digi-Key SC1152-ND Mating Power Supply (shipped with EZ-KIT Lite) 7.5V Power Supply GlobTek TR9CC2000LCP-Y The power connector supplies DC power to the EZ-KIT Lite board. Table 3-11 shows the power supply specifications. Table 3-11. Power Supply Specification Terminal Connection Center pin +7.5 VDC@3Amps Outer Ring GND USB (J8) The USB connector is a standard Type B USB receptacle. Part Description Manufacturer Part Number Type B USB receptacle (J8) Mill-Max 897-30-004-90-000 Digi-Key ED90003-ND Mating Assembly USB cable (provided with kit) Assmann AK672-5 Digi-Key AK672-5ND ADSP-BF561 EZ-KIT Lite Evaluation System Manual 3-19 Connectors RS232 (P2) The RS232-compatible connector is described in Table 3-12. Table 3-12. RS232 Connector Part Description Manufacturer Part Number DB9, Male, Right Angle (P2) Digi-Key A2096-ND Mating Assembly 2m Female to Female cable Digi-Key AE1016-ND SPORT0 (P3) The SPORT0 connector is linked to a 20-pin connector. The connector’s pinout can be found in “Schematics” on page B-1. For pricing and availability of the connectors, contact AMP. Part Description Manufacturer Part Number 20-position AMPMODU system 50 receptacle (P3) AMP 104069-1 Mating Connectors 20-position ribbon cable connector AMP 111196-4 20-position AMPMODU system 20 connector AMP 2-487937-0 20-position AMPMODU system 20 connector (w/o lock) AMP 2-487938-0 Flexible film contacts (20 per connector) AMP 487547-1 JTAG (P4) The JTAG header is the connecting point for a JTAG in-circuit emulator 3-20 ADSP-BF561 EZ-KIT Lite Evaluation System Manual EZ-KIT Lite Hardware Reference pod. When an emulator is connected to the JTAG header, the USB debug interface is disabled. 3 is missing to provide keying. Pin 3 in the mating connector L Pin should have a plug. using an emulator with the EZ-KIT Lite board, follow the L When connection instructions provided with the emulator. ADSP-BF561 EZ-KIT Lite Evaluation System Manual 3-21 Connectors 3-22 ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1 10MHZ SMT OSC003 3V 2 U35 Part Number Manufacturer Reference Design Description Reference A BILL OF MATERIALS RALTRON C04310-10.00 74LVC14A SOIC14 U47 HEX-INVER-SCHMITT-TRI GGER TI 74LVC14AD 3 IDT74FCT3244APY SSOP20 U13,U30 3.3V-OCTAL-BUFFER IDT IDT74FCT3244APY 4 CY7C64603-128 PQFP128 USB-TX/RX MICROCONTROLLER CYPRESS CY7C64603-128NC 5 MMBT4401 SOT-23 Q1 NPN TRANSISTOR 200MA FAIRCHILD MMBT4401 6 ADP3331ART SOT23-6 ADJ 200MA REGULATOR VR7 ANALOG DEVICES ADP3331ART 7 CY7C1019BV33-15VC SOJ32 128K X 8 SRAM U38 CYPRESS CY7C1019BV33-12VC 8 12.0MHZ THR OSC006 CRYSTAL Y1 DIG01 300-6027-ND 9 DSM2150F5V TQFP80 FLASH-ICP U44 ST MICRO DSM2150F5V U45 ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-1 Part Number Manufacturer Reference Design Description Reference 10 SN74AHC1G00 SOT23-5 SINGLE-2-INPUT-NAND U28,U34,U39,U42 TI SN74AHC1G00DBVR 11 12.288MHZ SMT OSC003 TS201/21262 U16 DIG01 SG-8002CA-PCC-ND 12 LT1765 SO-8 ADJUSTABLE-3A-SWITCH-REG VR5 LINEAR TECH LT1765ES8 13 GS74116 TSOP44 256Kx16 SRAM U40,U43 GSI TECHNOLOGY GS74116ATP-10 14 NDS8434A SO-8 P-MOSFET U29 FAIRCHILD SEMI NDS8434A 15 MT48LC16M16A2TG-75 TSOP54 256MB-SDRAM U32-33 MICRON MT48LC16M16A2TG75 16 27MHZ SMT OSC003 U17 EPSON SG-8002CA MP 17 XC2S150E FT256 U41 XILINX-SPARTANIIE-FPGA XILINX XC2S150E-7FT256C 18 IDT2305-1DC SOIC8 1 TO 5 ZERO DELAY CLK BUF 19 SN74LVC1G32 SOT23-5 U10 SINGLE-2 INPUT OR GATE TI SN74LVC1G32DBVR 20 M29W64OD TSOP48 64MBIT 8/16-BIT FLASH MEM ST MICRO M29W640DT 90N1 A-2 U19-20 U27 INTEICS9112AM-16 GRATED SYS ADSP-BF561 EZ-KIT Lite Evaluation System Manual Part Number Manufacturer Reference Design Description Reference Bill Of Materials 21 30.0000MHZ SMT OSC003 U14 OSCILLATOR EPSON 22 BF561 24LC32 “U31” SEE 1000220 U31 MICROCHIP 24LC32A-I/SN “U31” 23 1000pF 50V 5% 1206 CERM C153,C160 AVX 12065A102JAT2A 24 2200pF 50V 5% 1206 NPO C46,C76-81 AVX 12065A222JAT050 25 ADM708SAR SOIC8 VOLTAGE-SUPERVISOR U46 ANALOG DEVICES ADM708SAR 26 ADP3338AKC-33 SOT-223 VR3 3.3V-1.0AMP REGULATOR ANALOG DEVICES ADP3338AKC-3.3 27 ADP3339AKC-5 SOT-223 5V-1.5A REGULATOR VR1 ANALOG DEVICES ADP3339AKC-5-REEL 28 ADP3339AKC-33 SOT-223 3.3V 1.5A REGULATOR VR6 ANALOG DEVICES ADP3339AKC-3.3-RL 29 ADP3336ARM MSOP8 ADJ 500MA REGULATOR VR2,VR4 ANALOG DEVICES ADP3336ARM-REEL 30 10MA AD1580BRT SOT23D D1 1.2V-SHUNT-REF ANALOG DEVICES AD1580BRT 31 ADG752BRT SOT23-6 CMOS-SPDT-SWITCH U22-23,U25-26 ANALOG DEVICES ADG752BRT 32 AD8061ART SOT23-5 300MHZ-AMP U1-3 ANALOG DEVICES AD8061ART-REEL ADSP-BF561 EZ-KIT Lite Evaluation System Manual SG-8002CA30.000M A-3 Part Number Manufacturer Reference Design Description Reference 33 ADM3202ARN SOIC16 RS232-TXRX U21 ANALOG DEVICES ADM3202ARN 34 AD8606AR SOIC8 OPAMP U5-7,U9,U11-12,U1, U24 ANALOG DEVICES AD8606AR 35 AD1836AAS MQFP52 MULTI-CHANNEL-96KHZ-CODEC U15 ANALOG DEVICES AD1836AAS 36 ADSP-BF561SKBC-600 256 U48 DUEL BLACKFIN DSP ANALOG DEVICES ADSP-BF561SKBC-600 37 ADV7179 LFCSP40 VIDEO ENCODER U8 ANALOG DEVICES ADV7179KCP 38 ADV7183AKST LQFP80 U4 ANALOG DEVICES ADV7183AKST 39 RUBBER FEET BLACK MH1-5 MOUSER 517-SJ-5018BK 40 PWR 2.5MM_JACK CON005 RA J7 SWITCHCRAFT SC1152-ND12 41 USB 4PIN CON009 USB J8 MILL-MAX 897-30-004-90-000000 42 RCA 2X2 CON013 J4 SWITCHCRAFT PJRAS2X2S01 43 .05 10X2 CON014 P3 AMP 104069-1 44 SPST-MOMENTARY SWT013 6MM SW1,SW6-9 PANASONIC EVQ-PAD04M 45 DIP12 SWT014 J7 DIGI-KEY CKN3063-ND A-4 RA ADSP-BF561 EZ-KIT Lite Evaluation System Manual Part Number Manufacturer Reference Design Description Reference Bill Of Materials 46 0.05 45X2 CON019 SMT SOCKET J1-3 SAMTEC SFC-145-T2-F-D-A 47 DIP6 SWT017 SW2,SW4,SW10 DIG01 CKN1364-ND 48 RCA 3X2 CON024 RA J5-6 SWITCHCRAFT PJRAS3X2S01 49 DIP4 SWT018 4PIN-SMT-SWT SW3,SW5,SW11 DIG01 CKN1363-ND 50 0.00 1/8W 5% 1206 R43-44, R55, R71-73, YAGEO R80, R90, R133, R159, R163, R223-225, R228, R247 0.0ECT-ND 51 AMBER-SMT LED001 GULL-WING LED4-20 LN1461C-TR 52 330pF 50V 5% 805 NPO C82,C84,C86,C92-100 AVX 08055A331JAT 53 0.01uF 100V 10% 805 CERM C3, C5, C28, C41, AVX C49, C69-70, C74-75, C101,C112-114,C127, C134,C136-138, C140-141, C146, C149-150, C154, C156-157, C165-166, C168, C173-174, C176, C180-182, C185-188, C190, C200-203, C249, C256 08051C103KAT2A 54 0.22uF 25V 10% 805 CERM C104, C106-108, C125, C129, C143, C162 08053C224FAT PANASONIC AVX ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-5 Part Number Manufacturer Reference Design Description Reference 55 0.1uF 50V 10% 805 CERM C1-2, C4, C12, AVX C19-20, C22, C27, C29-30, C35, C37, C48, C51-60, C65-66, C71, C73, C83, C85, C87-91, C102, C109-111, C115, C122-124, C126, C131-132, C135, C139, C145, C147-148, C151-152, C155, C158-159, C164,C167,C171-172, C175, C177-179, C183-184, C189, C191, C233, C236, C241 08055C104KAT 56 0.001uF 50V 5% 805 NPO C23,C25,C33,C36, C38-40,C67-68, AVX 08055A102JAT2A 57 10uF 16V 10% C TANT CT17-18,CT20-21, CT23-24 SPRAGUE 293D106X9016C2T 58 10K 100MW 5% 805 R2, R7, R11-12, R14, AVX R24, R42, R45-47, R52, R57, R78, R85, R91, R96-98, R131, R143, R158, R160-162, R167-170, R174-177, R179, R181-183, R185, R189-190, R196, R198-203, R205-206, R208, R212, R221-222, R229, R239-241, R246, R248-251 A-6 CR21-103J-T ADSP-BF561 EZ-KIT Lite Evaluation System Manual Part Number Manufacturer Reference Design Description Reference Bill Of Materials 59 33 100MW 5% 805 R39,R41,R59-61, R165-166,R172 AVX CR21-330JTR 60 4.7K 100MW 5% 805 R86 AVX CR21-4701F-T 61 1M 100MW 5% 805 R76,R209 AVX CR21-1004F-T 62 1.5K 100MW 5% 805 R1,R94 AVX CR21-1501F-T 63 1.2K 1/8W 5% 1206 R23 DALE CRCW1206-122JRT1 64 49.9K 1/8W 1% 1206 R108-113 AVX CR32-4992F-T 65 2.21K 1/8W 1% 1206 R88-89 AVX CR32-2211F-T 66 100pF 100V 5% 1206 NPO C6-11,C26,C34, C61-63,C72 AVX 12061A101JAT2A 67 10uF 16V 10% B TANT CT1-4,CT15-16 AVX TAJB106K016R 68 100 100MW 5% 805 R242-245 AVX CR21-101J-T 69 220pf 50V 10% 1206 NPO C13-18 AVX 12061A221JAT2A 70 600 100MHZ 200MA 603 0.50 BEAD FER18-21 MURATA BLM11A601SPT 71 2A S2A_RECT DO-214AA SILICON RECTIFIER D2-3,D7 GENERALSEMI S2A 72 600 100MHZ 500MA 1206 0.70 BEAD FER2-4,FER6-12,FER1 DIGI-KEY 4-16 240-1019-1-ND 73 237 1/8W 1% 1206 R25-26,R53-54 CR32-2370F-T 74 750K 1/8W 1% 1206 R132,R156,R164,R173 DALE/VISHAY CRCW12067503FRT1 AVX ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-7 Part Number Manufacturer Reference Design Description Reference 75 5.76K 1/8W 1% 1206 R8,R15-16,R40, R49-50,R58, PHYCOMP 9C12063A5761FKHFT 76 11.0K 1/8W 1% 1206 R144-149 DALE CRCW12061102FRT1 77 120PF 50V 5% 1206 NPO C103,C105,C128, C130,C142,C144, C161,C163 PHILLIPS 1206CG121J9B200 78 75 1/8W 5% 1206 R4-6,R100-102,R104-1 PHILIPS 05,R107,R114, R134-135 9C12063A75R0JLHFT 79 30PF 100V 5% 1206 C221-222 AVX 12061A300JAT2A 80 68UF 6.3V 20% D TANT CT22 PANASONIC ECS-TOJD686R 81 340K 1/8W 1% 805 R211 DALE CRCW0805-3403FT 82 698K 1/8W 1% 805 R210 DALE CRCW0805-6983FT 83 680PF 50V 1% 805 NPO C116-121 AVX 08055A681FAT2A 84 10UF 25V +80-20% 1210 Y5V C31,C47,C50 MURATA GRM235Y.5V106Z025 85 2.74K 1/8W 1% 1206 R150-155 DALE CRCW12062741FRT1 86 5.49K 1/8W 1% 1206 R17-22,R27,R30-31, R34-35,R38 PANASONIC ERJ-8ENF5491V 87 3.32K 1/8W 1% 1206 R137-142 DALE CRCW12063321FRT1 88 1.65K 1/8W 1% 1206 R28-29,R32-33,R36-37 PANASONIC A-8 ERJ-8ENF1651V ADSP-BF561 EZ-KIT Lite Evaluation System Manual Part Number Manufacturer Reference Design Description Reference Bill Of Materials 89 10UF 16V 20% CAP002 ELEC CT5-14 DIG01 PCE3062TR-ND 90 2A SL22 DO-214AA SCHOTTKY D6 GENERAL SEMI SL22 91 53.6K 1/10W 1% 805 R75 PHILIPS 9C08052A5362FKRT/R 92 332K 1/10W 1% 805 R207 PHILIPS 9C08052A3323FKRT/R 93 10UH 47 +/-20 IND001 L11 DIG01 445-1202-2-ND 94 10K 31MW 5% RNET8 RN3 CTS 746X101103J 95 10K 50MW 5% BGA36 RN2 CTS RT130B7 96 0.00 100MW 5% 805 R66,R74,R77,R79,R81, VISHAY R83-84,R87,R99, R103,R106,R178, R192, R252 CRCW0805 0.0 RT1 97 190 100MHZ 5A FER002 FER5 MURATA DLW5BSN191SQ2 98 3.32K 100MW 1% 805 R194-195, R227 DIG01 P3.32KCCTR-ND 99 22 1/10W 5% 805 R67-68,R187-188, R204,R226 VISHAY/DALE CRCW0805220JRT1 100 0.68UH 0.72 10% 805 L1-4,L6,L8 MURATA LQG21NR68K10T1 101 82NF 50V 5% 805 X7R C64 AVX 08055C823JAT2A 102 1A ZHCS1000 SOT23D SCHOTTKY D5 ZETEX ZHCS1000 ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-9 Part Number Manufacturer Reference Design Description Reference 103 2.2UH 0.63 10% 805 L5,L7,L9 MURATA LQG21N2R2K10 104 0.47UF 16V 10% 805 C218,C230 AVX 0805YC474KAT2A 105 1UF 10V 10% 805 C21,C24,C32,C44-45 AVX 0805ZC105KAT2A 106 10UF 6.3V 10% 805 C208,C217,C219, C243,C255 AVX 080560106KAT2A 107 4.7UF 6.3V 10% 805 C169 AVX 08056D475KAT2A 108 0.1UF 10V 10% 402 C192-199,C206, AVX C209-213,C215, C220,C224-226, C234-235, C237-238,C242, C244-245,C248, C250,C253, C258-259 0402ZD104KAT2A 109 0.01UF 16V 10% 402 C204-205,C207,C214, AVX C216,C223,C227-229, C231-232,C239-240, C246-247,C251-252,C 254,C257 0402YC103KAT2A 110 1.5UH 45MOHM 20% IND003 2.8A L10 TYCO DS6630-1R5M 111 100MA CMDSH-3 SOD-323 D4 SUPERMINI SCHOTTKY CENTRAL SEMI CMDSH-3 112 0.18uF 25V 10% 805 CERM C170 AVX 08053C184KAT2A 113 100uF 10V 10% C TANT-LOW-ESR CT19 AVX TPSC107K010R0075 A-10 ADSP-BF561 EZ-KIT Lite Evaluation System Manual Part Number Manufacturer Reference Design Description Reference Bill Of Materials 114 2.2uF 10V 10% 805 CERM C43 AVX 0805ZD225KAT2A 115 76.8K 100MW 1% 1206 R48 DALE CRCW1206-7682FRT1 116 147K 100MW 1% 1206 R56 DALE CRCW1206-1473FRT1 117 10 62.5MW/R 5% RA8/38V RN1,RN4-12 RESISTOR ARRAY PANASONIC EXB-38V100JV 118 17.4K 1/10W 1% 805 PANASONIC ERJ-6ENF1742V R180 119 ADSP-BF561-EZLITE PCB ANALOD DEVICES 120 DB9 9PIN DB9M RIGHT ANGLE MALE P2 3M 787203-2 121 1K 1/8W 5% 1206 R10,R95,R115-118, R136 AVX CR32-102J-T 122 100K 1/8W 5% 1206 R9,R13,R157 DALE CR1206-1003FRT1 123 22 1/8W 5% 1206 R92-93 DALE CRCW1206220JRT1 124 270 1/8W 5% 1206 R120,R193,R197, R213-220, R230-237 AVX CR32-271J-T 125 680 1/8W 5% 1206 R119 AVX CR32-681J-T 126 10.0K 1/8W 1% 1206 R186 DALE CRCW1206-1002FRT1 127 150 1/8W 1% 1206 R3 PANASONIC ERJ-8ENF1500V 128 RED-SMT LED001 GULL-WING LED2-3 PANASONIC LN1261C ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-11 Part Number Manufacturer Reference Design Description Reference 129 GREEN-SMT LED001 GULL-WING LED1 PANASONIC LN1361C 130 604 1/8W 1% 1206 R125-130 DALE CRCW12066040FRT1 131 1uF 25V 20% A TANT -55+125 CT25-28 PANASONIC ECS-T1EY105R 132 ADG774A QSOP16 QUICKSWITCH-257 U36-37 ANALOG DEVICES ADG774ABRQ 133 IDC 2X1 IDC2X1 GOLD P1 134 IDC 7X2 IDC7X2 HEADER P4 BERG 54102-T08-07 135 2.5A RESETABLE FUS001 F1 RAYCHEM CORP. SMD250-2 A-12 ADSP-BF561 EZ-KIT Lite Evaluation System Manual A B C D 1 1 2 2 ADSP-BF561 EZ-KIT Lite Schematic 3 3 ANALOG DEVICES 4 Title ADSP-BF561 EZ-KIT LITE: Size Board No. C Date A B 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD TITLE Rev A0185-2003 1.2B Sheet 12-16-2003_15:28 D 1 of 15 A B C D U48 D0 D[31:0] 1 B16 D1 C15 D2 E12 D3 C16 D4 E14 D5 D15 D6 D16 D7 E15 D8 D9 D10 F13 F15 F12 D11 F16 D12 F14 3.3V D13 G15 D14 G13 D15 G12 A[25:2]_S D0 A2 D1 A3 D2 A4 D3 A5 D4 A6 D5 A7 D6 A8 D7 A9 D8 A10 D9 A11 D10 A12 D11 A13 D12 A14 D13 A15 D14 A16 D15 A17 R42 10K 805 R60 33 805 U14 1 OE OUT 3 D16 H12 D17 H15 D18 H13 D19 H16 D20 H14 D21 J15 D22 J13 OSC_30MHZ 30.0000MHZ OSC003 R51 DNP 805 EXT_DSP_CLK D23 J16 D24 K14 D25 K15 D26 K13 D27 L15 3.3V 2 R160 10K 805 R196 10K 805 D28 K12 D29 L16 D30 D31 J12 M15 D16 A18 D17 A19 D18 A20 D19 A21 D20 A22 D21 A23 D22 A24 D23 A25 B12 ARDY D27 F1 3.3V G1 D28 D29 D30 SDQM0/ ABE0 SDQM1/ ABE1 SDQM2/ ABE2 SDQM3/ ABE3 BR BGH ARDY ARE RESET CLKIN AMS1 XTAL AMS2 AMS3 R168 10K 805 SRAS SCAS R170 10K 805 SWE SA10 SMS0 3 DSP_BYPASS BMODE0 G4 M10 BMODE1 N10 BYPASS SMS1 SMS2 BMODE0 SMS3 BMODE1 SCKE P11 NMI0 NMI1 R9 G10 A5_S B14 A6_S C14 A7_S A2_S 1 F11 A8_S A3_S 2 D7 A9_S A4_S 3 A6 A10_S A5_S 4 C6 A11_S B5 A12_S E6 A13_S A5 A14_S A6_S 1 E5 A15_S A7_S 2 B4 A16_S A8_S 3 F6 A17_S A9_S 4 B3 A18_S C4 A19_S A3 A20_S F5 A21_S A10_S 1 B2 A22_S A11_S 2 D4 A23_S A12_S 3 A2 A24_S A13_S 4 C3 A25_S A[25:2] RN4 RN12 R1A R1B R2A R2B R3A R3B R4A R4B 1 BMODE0 2 BMODE1 ON ON RESERVED OFF ON FLASH ON OFF SPI SROM 8-BIT OFF NMI0 SCLK0 NMI1 SCLK1 A15_S A4 A16_S 5 A5 A17_S R1B R2B R3B R4B 8 A14 7 A15 6 A16 5 A17 8 A18 7 A19 6 A20 5 A21 8 A22 7 A23 6 A24 5 A25 R1A R1B R2A R2B R3A R3B R4A R4B 8 A6 A18_S 7 A7 A19_S 6 A8 A20_S 5 A9 A21_S 1 R1A 2 R2A 3 R3A 4 R4A R1B R2B R3B R4B 10 RA8/38V RN7 RN8 R1A R1B R2A R2B R3A R3B R4A R4B 8 A10 A22_S 7 A11 A23_S 6 A12 A24_S 5 A13 A25_S 10 RA8/38V E11 ABE0_S 1 B13 ABE1_S 2 A14 ABE2_S 3 A15 ABE3_S 4 A13 1 R1A 2 R2A 3 R3A 4 R4A R1B R2B R3B R4B 10 RA8/38V 2 R1A R1B R2A R2B R3A R3B R4A R4B 8 ABE0 7 ABE1 6 ABE2 5 ABE3 10 RA8/38V BG C12 BGH C7 AOE B8 ARE A8 AWE C8 AMS0 B7 AMS1 E7 AMS2 A7 AMS3 RN10 C10 SRAS_S 1 D10 SCAS_S 2 E10 SWE_S 3 D11 SA10_S 4 E9 SMS0_S B9 SMS1_S C9 SMS2_S A10 SMS3_S 2 B10 A11 SCKE 3 SCLK0_S 4 A12 R1A R1B R2A R2B R3A R3B R4A R4B 8 SRAS 7 SCAS 6 SWE 5 SA10 10 RA8/38V RN9 1 SCLK1_S 3 R1A R1B R2A R2B R3A R3B R4A R4B 8 SMS0 7 SMS1 6 SMS2 5 SMS3 R187 22 805 SCLK0 3.3V U20 SCLK1 1 REF CLKOUT CLK1 DEFAULT 6 SPI SROM 16-BIT 4 VDD CLK3 GND CLK4 IDT2305-1DC SOIC8 SW3 8 R68 22 805 3 2 5 CLK_OUT_EXP1 R67 22 805 CLK_OUT_EXP2 7 R65 22 805 ON 1 7 3 6 4 5 2 3 ANALOG DEVICES 8 2 1 10 RA8/38V R176 10K 805 BOOT MODE 4 A3 6 10 RA8/38V R188 22 805 1 7 1 R1A 2 R2A 3 R3A 4 R4A RN6 CLK2 OFF A14_S RN5 ADSP-BF561 MBGA256 SW3: BOOT MODE/BYPASS Select (Default = OFF, ON, ON, OFF) A2 10 RA8/38V 10 RA8/38V R169 10K 805 8 D31 C42 0.1UF 805 DNP R167 10K 805 A4_S RN11 AMS0 DSPCK_30MHZ A3_S B15 D26 AWE F3 RESET G11 D25 AOE D9 A2_S D24 BG BR D13 DNP 4 Title ADSP-BF561 EZ-KIT LITE: SWT018 DIP4 Size Board No. C Date A B 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD DSP - EXT MEM INTERFACE Rev A0185-2003 1.2B Sheet 12-16-2003_16:27 D 2 of 15 A B C D U48 P15 RSCLK0 1 R16 RFS0 L12 DR0PRI P16 DR0SEC N16 TSCLK0 L13 TFS0 M16 DT0PRI N15 DT0SEC RSCLK0/PF28 PF15/TMRXCLK RFS0/PF19 PF14 DR0PRI PF13 DR0SEC/PF20 PF12 TSCLK0/PF29 PF11 TFS0/PF16 PF10 DT0PRI/PF18 PF9 DT0SEC/PF17 PF8 PF7/SPIS7/TMR7 P13 RSCLK1 N13 RFS1 M12 DR1PRI T14 DR1SEC R14 TSCLK1 P14 TFS1 R15 DT1PRI T15 DT1SEC RSCLK1/PF30 PF6/SPIS6/TMR6 RFS1/PF24 PF5/SPIS5/TMR5 DR1PRI PF4/SPIS4/TMR4 DR1SEC/PF25 PF3/SPIS3/TMR3 TSCLK1/PF31 PF2/SPIS2/TMR2 TFS1/PF21 PF1/SPIS1/TMR1 DTIPRI/PF23 PF0/SPISS/TMR0 P8 PF15 R8 PF14 N8 PF13 T7 PF12 P7 PF11 PF[15:0] 1 RN1 R7 N6 R6 PF15 1 PF14 2 PF13 3 PF10 PF9 PF8 4 R1A R2A R1B R2B R3A R3B R4B M7 PF7 R4A T5 PF6 10 RA8/38V P6 PF5 R5 PF4 M6 PF3 T4 PF2 N5 PF1 P4 PF0 8 7 6 AD1836_RESET VENC_RESET VDEC_RESET 5 DT1SEC/PF22 PROGR. FLAG T13 RX R13 TX N11 MOSI 2 R12 MISO 3.3V M11 SCK R10 T10 T9 R85 10K 805 R200 10K 805 R179 10K 805 P10 RX/PF27 SLEEP TX/PF26 MOSI MISO SCK TDI TDO N9 TDO TMS TCK TRST EMU FUNCTION T11 R11 EMU PF15 AD1836 CODEC RESET PF14 ADV7179 VIDEO ENCODER RESET PF13 ADV7183A VIDEO DECODER RESET PF12 GENERAL PURPOSE PF11 GENERAL PURPOSE PF10 GENERAL PURPOSE PF9 GENERAL PURPOSE PF8 GENERAL PURPOSE / PUSH BUTTON STATUS INPUT PF7 GENERAL PURPOSE / PUSH BUTTON STATUS INPUT PF6 GENERAL PURPOSE / PUSH BUTTON STATUS INPUT/ UART SIGNAL PF5 GENERAL PURPOSE / PUSH BUTTON STATUS INPUT/ UART SIGNAL 2 PF4 GENERAL PURPOSE / AD1836 LATCH SIGNAL TDI PF3 GENERAL PURPOSE / VIDEO DECODER FIELD TMS PF2 GENERAL PURPOSE / VIDEO DECODER OUTPUT ENABLE PF1 GENERAL PURPOSE / I2C SERIAL DATA PF0 GENERAL PURPOSE / I2C SERIAL CLOCK TCK ADSP-BF561 MBGA256 TRST R86 4.7K 805 DSP_VDD_EXT DSP_VDD_INT U48 A1 A16 A4 A9 B11 B6 D12 E16 F2 G16 G3 J6 K16 K6 L10 L5 M14 T1 T12 T16 T3 T6 T8 3 C11 C13 C5 D14 D5 D6 D8 E1 E13 F10 F8 G14 G2 G6 G7 G8 H1 H10 H2 H8 H9 4 VDDEXT1 VDDEXT2 VDDEXT3 VDDEXT4 VDDEXT5 VDDEXT6 VDDEXT7 VDDEXT8 VDDEXT9 VDDEXT10 VDDEXT11 VDDEXT12 VDDEXT13 VDDEXT14 VDDEXT15 VDDEXT16 VDDEXT17 VDDEXT18 VDDEXT19 VDDEXT20 VDDEXT21 VDDEXT22 VDDEXT23 VDDINT1 VDDINT2 VDDINT3 VDDINT4 VDDINT5 VDDINT6 VDDINT7 VDDINT8 VDDINT9 VDDINT10 VDDINT11 VDDINT12 VDDINT13 VDDINT14 VROUT1 VROUT2 NC0 NC1 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND41 GND40 GND39 GND38 GND37 GND36 GND35 GND34 GND33 GND32 GND31 GND30 GND29 GND28 GND27 GND26 GND25 GND24 GND23 GND22 ADSP-BF561 MBGA256 E8 F7 F9 G9 H11 H6 H7 J10 J8 J9 K11 K8 L8 M8 J1 3 VROUT J2 M5 M13 P9 P5 P2 P12 N7 N14 N12 M9 M4 L9 L7 L3 L14 L11 K9 K7 K10 J7 J14 J11 ANALOG DEVICES Title ADSP-BF561 EZ-KIT LITE: Size Board No. C Date A B 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD DSP - PROGR. FLAGS, SPI Rev A0185-2003 1.2B Sheet 12-10-2003_18:18 D 3 of 18 A B C D SW5: PPI CLK Routing Select (Default: 1 = OFF, 2 = ON, 3 = ON, 4 = ON) 1 or 3 PPIxCLK_SEL0 2 or 4 PPIxCLK_SEL1 3.3V R166 33 805 PPIxCLK ON ON PPI_27MHZ_CLK OFF ON ADV7183_CLKOUT X OFF EXPANSION_CLK 3.3V VDEC_27MHZ_CLK R165 33 805 R162 10K 805 1 U22 3 U23 R174 10K 805 VENC_27MHZ_CLK 3.3V R175 10K 805 R182 10K 805 R181 10K 805 R171 33 805 R59 33 805 U17 1 OE OUT 3 1 6 1 REF CLKOUT 27MHZ OSC003 6 VDD 4 GND 1 4 ADG752BRT SOT23-6 8 3 CLK1 2 CLK2 5 CLK3 7 CLK4 PPI0_CLK 4 EXT_27MHZ_CLK DNP OSC27M 1 6 U19 OSC_27M R66 0.00 805 3 ADG752BRT SOT23-6 EXP_PPI0_CLK R172 33 805 U26 PPI_27MHZ_CLK 3 U25 1 IDT2305-1DC SOIC8 6 VDEC_CLKOUT SW5 PPI0CLK_SEL0 2 7 PPI0CLK_SEL1 3 6 PPI1CLK_SEL0 4 5 PPI1CLK_SEL1 ON 8 1 1 R178 0.00 805 3 1 PPI1_CLK 6 4 2 4 3 4 SWT018 DIP4 ADG752BRT SOT23-6 ADG752BRT SOT23-6 EXP_PPI1_CLK U48 2 PPI0_D[15:0] PPI0_D15 L1 PPI0_D14 J5 PPI0_D13 J3 PPI0_D12 J4 PPI0_D11 K2 PPI0_D10 H5 PPI0_D9 K1 PPI0_D8 H4 PPI0_D7 K3 PPI0_D6 H3 PPI0_D5 PPI0_D4 E2 PPI0_D3 E3 PPI0_D2 D1 PPI0_D1 G5 PPI0_D0 D2 C2 PPI0_CLK E4 PPI0_SYNC1 C1 PPI0_SYNC2 3 F4 D3 PPI0_SYNC3 PPI0_D15/PF47 PPI1_D15/PF39 PPI0_D14/PF46 PPI1_D14/PF38 PPI0_D13/PF45 PPI1_D13/PF37 PPI0_D12/PF44 PPI1_D12/PF36 PPI0_D11/PF43 PPI1_D11/PF35 PPI0_D10/PF42 PPI1_D10/PF34 PPI0_D9/PF41 PPI1_D9/PF33 PPI0_D8/PF40 PPI1_D8/PF32 PPI0_D7 PPI1_D7 PPI0_D6 PPI1_D6 PPI0_D5 PPI1_D5 PPI0_D4 PPI1_D4 PPI0_D3 PPI1_D3 PPI0_D2 PPI1_D2 PPI0_D1 PPI1_D1 PPI0_D0 PPI1_D0 PPI0_CLK PPI1_CLK PPI0_SYN1/TMR8 PPI1_SYN1/TMR10 PPI0_SYN2/TMR9 PPI1_SYN2/TMR11 PPI0_SYN3 PPI1_SYN3 R4 PPI1_D15 N4 PPI1_D14 R3 PPI1_D13 N3 PPI1_D12 T2 PPI1_D11 PPI1_D8 P3 PPI1_D10 PPI1_D9 R2 PPI1_D9 PPI1_D10 R1 PPI1_D8 PPI1_D11 P1 PPI1_D7 M3 PPI1_D6 N2 U13 2 1A1 4 1A2 6 1A3 8 1A4 PPI1_D12 11 PPI1_D13 13 PPI1_D14 15 PPI1_D15 17 2A1 2A2 PPI1_D5 L6 2 PPI1_D[15:0] 2A3 PPI1_D4 N1 PPI1_D3 2A4 M2 PPI1_D2 K5 PPI1_D1 1 OE1 19 OE2 M1 PPI1_D0 18 1Y1 16 1Y2 14 1Y3 12 1Y4 9 2Y1 7 2Y2 5 2Y3 3 2Y4 LED20 AMBER-SMT LED001 LED19 AMBER-SMT LED001 LED18 AMBER-SMT LED001 LED17 AMBER-SMT LED001 LED16 AMBER-SMT LED001 LED15 AMBER-SMT LED001 LED14 AMBER-SMT LED001 LED13 AMBER-SMT LED001 IDT74FCT3244APY SSOP20 B1 PPI1_CLK K4 R237 270 1206 PPI1_SYNC1 L2 R236 270 1206 R235 270 1206 R234 270 1206 R233 270 1206 R232 270 1206 R231 270 1206 R230 270 1206 PPI1_SYNC2 L4 3 PPI1_SYNC3 ADSP-BF561 MBGA256 U30 PPI0_D8 2 PPI0_D9 4 PPI0_D10 6 PPI0_D11 8 PPI0_D12 11 PPI0_D13 13 PPI0_D14 15 PPI0_D15 17 1 19 1A1 1Y1 1A2 1Y2 1A3 1Y3 1A4 1Y4 2A1 2Y1 2A2 2Y2 2A3 2Y3 2A4 2Y4 18 16 14 12 9 7 5 3 OE1 OE2 LED12 AMBER-SMT LED001 LED11 AMBER-SMT LED001 LED10 AMBER-SMT LED001 LED9 AMBER-SMT LED001 LED8 AMBER-SMT LED001 LED7 AMBER-SMT LED001 LED6 AMBER-SMT LED001 LED5 AMBER-SMT LED001 ANALOG DEVICES IDT74FCT3244APY SSOP20 4 R220 270 1206 R219 270 1206 R218 270 1206 R217 270 1206 R216 270 1206 R215 270 1206 R214 270 1206 R213 270 1206 Title ADSP-BF561 EZ-KIT LITE: Size Board No. C Date A B 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD DSP - PPI0 AND PPI1 Rev A0185-2003 1.2B Sheet 12-16-2003_15:56 D 4 of 15 A B C FLASH A (8MB) D SDRAM 64MB (256Mb x 2 Chips) 4M x 16 D[31:0] 1 1 U32 A[25:2] U27 25 ABE3 A2 24 A3 23 A4 22 A5 21 A6 20 A7 19 A8 A9 8 A10 7 A11 6 A12 5 A13 3.3V 2 R190 10K 805 R177 10K 805 4 A14 3 A15 2 A16 1 A17 48 A18 17 A19 16 A20 R189 10K 805 18 9 A21 10 A22 13 26 AMS0 28 AOE 11 AWE 47 FLASH_WP 14 FLASH_RP 12 3.3V A0 A1 A2 VCC 37 A3 A4 D0 A5 D1 A6 D2 A7 D3 A8 D4 A9 D5 A10 D6 A11 D7 A12 D8 A13 D9 A14 D10 A15 D11 A16 D12 A17 D13 A18 D14 A19 D15 29 D0 31 D1 33 D2 35 D3 38 D4 40 D5 42 D6 44 D7 30 D8 32 D9 34 D10 36 D11 23 A3 24 A4 25 A5 26 A6 29 A7 30 A8 31 A9 32 A10 33 A11 34 SCAS 41 D13 SRAS 43 D14 45 D15 R183 10K 805 A20 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A13 35 A14 36 A11 A12_NC A18 20 A19 21 BA0 BA1 16 SWE 3.3V A0 22 SA10 D12 39 A2 WE 17 CAS 18 RAS 2 DQ0 4 DQ1 5 DQ2 7 DQ3 8 DQ4 10 DQ5 11 DQ6 13 DQ7 42 DQ8 44 DQ9 45 DQ10 47 DQ11 48 DQ12 50 DQ13 51 DQ14 53 DQ15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 19 CS 37 CKE 38 CLK SMS0 2 SCKE SCLK0 15 ABE0 DQML 39 ABE1 DQMH A21 CE RDY 15 MT48LC16M16A2TG-75 TSOP54 FLASH_RDY OE U33 WE BYTE VSS2 WP/VPP VSS1 46 A2 23 A3 24 A4 25 A5 26 A6 29 A7 30 A8 31 A0 27 RP M29W64OD TSOP48 A1 A2 A3 A4 A5 A6 A9 32 A10 33 A11 34 A7 A8 A9 22 A10 3 A13 35 A14 36 A11 A12_NC A18 20 A19 21 BA0 BA1 2 DQ0 4 DQ1 5 DQ2 7 DQ3 8 DQ4 10 DQ5 11 DQ6 13 DQ7 42 DQ8 44 DQ9 45 DQ10 47 DQ11 48 DQ12 50 DQ13 51 DQ14 53 DQ15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 3 D27 D28 D29 D30 D31 Memory Map 16 START 0x0000 0000 0x2000 0000 END 0x03FF FFFF 0x207F FFFF BANK SDRAM Bank 0 ASYNC Memory Bank 0 WE DEVICE 17 CAS 18 64MB SDRAM 8MB FLASH RAS ABE2 ABE3 19 CS 37 CKE 38 CLK 15 DQML 39 DQMH MT48LC16M16A2TG-75 TSOP54 ANALOG DEVICES 4 Title ADSP-BF561 EZ-KIT LITE: Size Board No. C Date A B 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD MEMORY - FLASH & SDRAM Rev A0185-2003 1.2B Sheet 12-16-2003_11:03 D 5 of 18 A B C D ADC2 ADC1 R61 33 805 U16 1 LEFT (WHITE) 3 OUT OE 1 DAC1 R161 10K 805 DAC2 DAC3 3.3V AD1836_CLK R18 5.49K 1206 RIGHT (RED) 12.288MHZ OSC003 OUT (J4) R145 11.0K 1206 IN (J5) C7 100PF 1206 1 R138 3.32K 1206 OUT1R- C96 330PF 805 3.3V 6 U5 7 DAC1 RIGHT 5 C117 680PF 805 R30 5.49K 1206 AD8606AR SOIC8 R29 1.65K 1206 R126 604 1206 OUT1R+ R57 10K 805 J5 3X2 CON024 CT8 10UF CAP002 DAC1_RIGHT 7 AUDIO CODEC R151 2.74K 1206 U15 47 DR0PRI 48 ASDATA1 DR0SEC ASDATA2 44 RFS0 OUT1L- ABCLK OUT1R+ 2 OUT1R45 AD1836_CLK OUT2L+ CLATCH 51 SCK OUT2L- CDATA OUT2R+ COUT OUT2R- IN1L+ OUT3L+ 49 MISO ADC1 LEFT R46 10K 805 R45 10K 805 16 IN1L+ R47 10K 805 17 IN1L- ADC1 RIGHT IN1L- OUT3L- IN1R+ OUT3R+ 18 IN1R+ 19 IN1R- OUT1L- DAC1 LEFT 31 OUT1R+ 30 OUT1R- DAC1 RIGHT 2 6 OUT2L+ 7 OUT2L- AGND DAC2 LEFT CCLK 2 MOSI OUT1L+ 9 MCLK 50 PF4 8 9 R109 49.9K 1206 C77 2200PF 1206 ALRCLK 43 RSCLK0 OUT1L+ C14 220PF 1206 IN1R- OUT3R- 33 OUT2R+ 32 OUT2R- 4 OUT3L+ 5 OUT3L- 35 OUT3R+ 34 OUT3R- DAC2 RIGHT DAC3 LEFT R17 5.49K 1206 R144 11.0K 1206 DAC3 RIGHT C6 100PF 1206 R137 3.32K 1206 OUT1L20 IN2L+/CL2/CL2 21 ADC2 LEFT IN2L-/CL1/CL1 22 IN2L1 NC/IN2L1/IN2L+ 23 IN2L2 NC/IN2L2/IN2L- 24 IN2R2 ADC2 RIGHT IN2R1 DT0PRI FILTR IN2R-/CR1/CR1 FILTD 26 NC/IN2R1/IN2R+ 27 2 U5 1 TFS0 TSCLK0 DAC1 LEFT R159 0.00 1206 3 C116 680PF 805 R27 5.49K 1206 13 12 AD8606AR SOIC8 R28 1.65K 1206 C38 0.001UF 805 C39 0.001UF 805 3 DAC1_LEFT 8 CT16 10UF B C124 0.1UF 805 CT15 10UF B C123 0.1UF 805 R150 2.74K 1206 C13 220PF 1206 9 3 C133 0.001UF 805 R108 49.9K 1206 C76 2200PF 1206 AD1836AAS MQFP52 C40 0.001UF 805 J5 3X2 CON024 CT7 10UF CAP002 IN2R+/CR2/CR2 PD/RST R158 10K 805 R125 604 1206 OUT1L+ 3 AD1836_RESET C95 330PF 805 DT0SEC NC/IN2R2/IN2R- 25 3 38 DSDATA1 41 DSDATA2 42 DSDATA3 36 DLRCLK 37 DBCLK U12 1 AD1836_VREF AGND 2 AD8606AR SOIC8 R43 0.00 1206 R55 0.00 1206 AGND 5 U12 AGND 7 SW10: Audio Loopback For Test Purposes Default = All Off 6 AD8606AR SOIC8 SW10 ON 11 3 10 4 9 5 8 6 7 3 ADC2_LEFT 4 ADC2_RIGHT 12 2 2 ADC1_RIGHT 1 ADC1_LEFT 4 1 R44 0.00 1206 R71 0.00 1206 ANALOG DEVICES DAC1_LEFT DAC1_RIGHT Nashua, NH 03063 4 PH: 1-800-ANALOGD DAC2_LEFT DAC2_RIGHT 5 DAC3_LEFT AGND Title ADSP-BF561 EZ-KIT LITE: AUDIO CODEC 6 DAC3_RIGHT Size SWT017 DIP6 Board No. C Date A 20 Cotton Road B Rev A0185-2003 1.2B Sheet 12-11-2003_13:24 D 6 of 18 A B C D 1 1 R19 5.49K 1206 R146 11.0K 1206 C8 100PF 1206 R22 5.49K 1206 R139 3.32K 1206 OUT2R- R149 11.0K 1206 C97 330PF 805 2 C100 330PF 805 3 R31 5.49K 1206 C118 680PF 805 AD8606AR SOIC8 R32 1.65K 1206 R142 3.32K 1206 OUT3R- U6 1 DAC2 RIGHT C11 100PF 1206 6 U7 7 DAC3 RIGHT R128 604 1206 5 J5 3X2 CON024 CT10 10UF CAP002 OUT2R+ DAC2_RIGHT R38 5.49K 1206 4 C121 680PF 805 AD8606AR SOIC8 R37 1.65K 1206 R130 604 1206 R152 2.74K 1206 C15 220PF 1206 J5 3X2 CON024 CT12 10UF CAP002 OUT3R+ 6 AD1836_VREF DAC3_RIGHT 1 R111 49.9K 1206 C79 2200PF 1206 R155 2.74K 1206 C18 220PF 1206 3 R113 49.9K 1206 C81 2200PF 1206 2 2 AGND AGND R20 5.49K 1206 R147 11.0K 1206 C9 100PF 1206 R21 5.49K 1206 R140 3.32K 1206 R148 11.0K 1206 OUT2L- R141 3.32K 1206 OUT3L- C98 330PF 805 6 U6 C99 330PF 805 7 3 C10 100PF 1206 DAC2 LEFT 2 U7 5 R34 5.49K 1206 C119 680PF 805 AD8606AR SOIC8 R33 1.65K 1206 R127 604 1206 OUT2L+ 3 J5 3X2 CON024 CT9 10UF CAP002 DAC2_LEFT 5 R153 2.74K 1206 C16 220PF 1206 3 1 DAC3 LEFT R35 5.49K 1206 C120 680PF 805 AD8606AR SOIC8 R36 1.65K 1206 R129 604 1206 J5 3X2 CON024 CT11 10UF CAP002 OUT3L+ DAC3_LEFT 2 6 R110 49.9K 1206 C78 2200PF 1206 R154 2.74K 1206 C17 220PF 1206 3 R112 49.9K 1206 C80 2200PF 1206 AGND AGND ANALOG DEVICES 4 Title ADSP-BF561 EZ-KIT LITE: Size Board No. C Date A B 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD AUDIO OUT Rev A0185-2003 1.2B Sheet 12-10-2003_18:18 D 7 of 18 A 1 J4 2X2 CON013 B CT5 10UF CAP002 FER10 600 1206 2 R121 5.76K 1206 C R49 5.76K 1206 1 J4 2X2 CON013 5 3 C62 100PF 1206 2 R123 5.76K 1206 R62 5.76K 1206 ADC2_LEFT 6 C142 120PF 1206 C72 100PF 1206 R53 237 1206 U11 AGND 2 1 IN1L- AGND 1 AGND C25 0.001UF 805 R50 5.76K 1206 AD8606AR SOIC8 C26 100PF 1206 R58 5.76K 1206 R63 5.76K 1206 ADC1 LEFT C130 120PF 1206 C23 0.001UF 805 R164 750K 1206 R54 237 1206 U11 6 7 U18 7 IN1L+ 5 2 ADC2 LEFT C144 120PF 1206 AGND 6 IN2L2 3 AD8606AR SOIC8 R156 750K 1206 U18 AGND 3 R40 5.76K 1206 CT13 10UF CAP002 FER12 600 1206 ADC1_LEFT C128 120PF 1206 D IN2L1 5 AD8606AR SOIC8 2 AD8606AR SOIC8 AGND AGND J4 2X2 CON013 CT6 10UF CAP002 FER11 600 1206 1 R122 5.76K 1206 J4 2X2 CON013 R15 5.76K 1206 ADC1_RIGHT 4 3 C103 120PF 1206 C63 100PF 1206 2 CT14 10UF CAP002 FER9 600 1206 R25 237 1206 U9 R69 5.76K 1206 ADC2_RIGHT 6 AGND R124 5.76K 1206 C161 120PF 1206 C61 100PF 1206 2 1 IN1R- AGND 1 AGND 3 R8 5.76K 1206 AD8606AR SOIC8 C36 0.001UF 805 R16 5.76K 1206 C34 100PF 1206 R64 5.76K 1206 AGND 6 ADC1 RIGHT C33 0.001UF 805 R173 750K 1206 6 7 ADC2 RIGHT C163 120PF 1206 R26 237 1206 U9 3 R70 5.76K 1206 C105 120PF 1206 R132 750K 1206 IN2R2 3 AD8606AR SOIC8 3 U24 AGND U24 7 IN1R+ 5 IN2R1 5 AD8606AR SOIC8 AD8606AR SOIC8 AGND AGND AD1836_VREF ANALOG DEVICES 4 Title ADSP-BF561 EZ-KIT LITE: Size Board No. C Date A B 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD AUDIO IN Rev A0185-2003 1.2B Sheet 12-10-2003_18:18 D 8 of 18 A B C D SW11 1 7 3 6 4 5 3 VIDEO_AVIN5 8 2 2 VIDEO_AVIN4 ON 1 VIDEO_AVIN1 VIDEO_DAC_A VIDEO_DAC_C VIDEO_DAC_B 4 SWT018 DIP4 SW11: Video Loopback For Test Purposes Default = All Off 1 R136 1K 1206 A3V DAC A DAC B DAC C Composite Video CVSB CVSB C Component Video G B R Differential Component Video Y U V S Video Y 1 C VIDEO_DAC_A U3 5 4 L1 0.68UH 805 L5 2.2UH 805 L4 0.68UH 805 1 3 2 R114 75 1206 C92 330PF 805 C86 330PF 805 J6 3X2 CON024 R104 75 1206 R6 75 1206 8 DAC A AD8061ART SOT23-5 9 R10 1K 1206 AGND2 VIDEO ENCODER 3V_B R116 1K 1206 2 2 U8 VAA1 VAA2 VAA3 VAA4 VAA5 PPI1_D7 PPI1_D[15:0] 5 PPI1_D6 4 PPI1_D5 3 PPI1_D4 39 PPI1_D3 38 PPI1_D2 37 PPI1_D1 36 PPI1_D0 35 P7 DAC_A P6 DAC_B P5 DAC_C 1 P3 COMP P2 VREF P1 RSET 16 3 PF1 PF[15:0] PF0 22 21 CLOCK FIELD/VSYNC GND1 GND2 SDATA GND3 SCLOCK GND5 GND6 34 33 25 C115 0.1UF 805 C12 0.1UF 805 R23 1.2K 1206 U1 27 GND7 SCRESET/RTC GND8 TTX GND9 TTXREQ GND10 L9 2.2UH 805 L2 0.68UH 805 1 28 3 2 24 23 R135 75 1206 30 C94 330PF 805 C82 330PF 805 R4 75 1206 DAC B 5 AD8061ART SOT23-5 6 R115 1K 1206 31 13 VENC_HS 14 VENC_VS 15 R118 1K 1206 6 7 3 8 A3V 1 9 R3 150 1206 11 12 D1 AD1580 SOT23D VIDEO_DAC_C 2 U2 17 4 19 L6 0.68UH 805 26 L7 2.2UH 805 5 1 3 40 2 R134 75 1206 R9 100K 1206 C93 330PF 805 C84 330PF 805 J6 3X2 CON024 R105 75 1206 L3 0.68UH 805 ADV7179 LFCSP40 R143 10K 805 5 4 L8 0.68UH 805 29 J6 3X2 CON024 R107 75 1206 AGND2 ALSB 3V_B 32 R14 10K 805 RESET GND4 R13 100K 1206 VIDEO_DAC_B 18 P0 BLANK 20 VENC_RESET A3V 10 P4 HSYNC VENC_27MHZ_CLK 2 R5 75 1206 2 DAC C AD8061ART SOT23-5 3 R117 1K 1206 AGND2 R133 0.00 1206 ANALOG DEVICES 4 Title ADSP-BF561 EZ-KIT LITE: AGND2 Size Board No. C Date A B 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD VIDEO ENCODER (VIDEO OUT) Rev A0185-2003 1.2B Sheet 12-11-2003_13:22 D 9 of 18 C DAC_D B DAC_B DAC_C A 3.3V (WHITE) OUT 1 D VIDEO DECODER R12 10K 805 (RED) IN R11 10K 805 R131 10K 805 R2 10K 805 Note: Signal Names in brackets refer to ADV7183KST 1 XTAL1 P15 P14 P13 Composite Video CVBS CVBS CVBS Differential Component Video Y S Video Y PF[15:0] V PF1 67 PF0 68 ALSB P12 SDA P11 SCLK P10 U P9 C 64 VDEC_RESET 36 J6 3X2 CON024 R99 0.00 805 7 AVIN1 P8 PWRDN P7 P6 R7 10K 805 C60 0.1UF 805 RESET 65 NC[ISO] P4 VIDEO_AVIN1 42 41 AIN1 P3 AIN7 P2 9 P1 TP1 J6 3X2 CON024 2 4 AVIN4 44 43 R103 0.00 805 P5 C66 0.1UF 805 P0 46 45 AIN3 LLC2 AIN9 NC[LLCREF] 6 ELPF 58 J6 3X2 CON024 57 R106 0.00 805 1 AVIN5 C65 0.1UF 805 60 59 AIN10 AIN5 AIN11 3 R100 75 1206 R102 75 1206 HS 62 61 CT3 10UF B C58 0.1UF 805 CT1 10UF B FIELD NC[VREF] NC[HREF] TP3 R101 75 1206 C2 0.1UF 805 AGND2 52 49 AGND2 CT4 10UF B C59 0.1UF 805 C68 0.001UF 805 AIN12 REFOUT CML CAPY1 CAPY2 54 NC[CLKIN] SFL[HFF] NC[AEF] NC[RD] OE CAPC1 NC[GPO3] CAPC2 NC[GPO2] 3 NC[GPO1] NC[GPO0] C4 0.1UF 805 CT2 10UF B C57 0.1UF 805 C67 0.001UF 805 50 AVDD DVDD1 DVDD2 DVDD3 AGND2 A3V A5V AGND2 38 C54 0.1UF 805 C1 0.1UF 805 PVDD DVDDIO1 DVDDIO2 39 DNP FER13 600 1206 40 47 53 AGND2 5 PPI0_D3 6 PPI0_D2 7 PPI0_D1 8 PPI0_D0 19 R39 33 805 20 AGND2 56 FER14 600 1206 63 21 4 22 SN74LVC1G32 SOT23-5 23 24 PVDD_ADV7183 32 33 27 C5 0.01UF 805 26 25 2 C64 82NF 805 R1 1.5K 805 37 2 VDEC_HS 1 VDEC_VS 80 VDEC_FIELD 69 VDEC_VREF 70 VDEC_HREF 16 11 SW2 12 ON VENC_HS 12 11 R24 10K 805 13 78 10 9 VENC_VS 77 8 79 7 C55 0.1UF 805 C3 0.01UF 805 C73 0.1UF 805 34 DVDD_ADV7183 1.8V 35 FER15 600 1206 30 10 72 DNP FER17 600 1206 4 3 4 5 PF3 6 PF2 PPI1_SYNC1 PPI0_SYNC1 PPI0_SYNC2 PPI1_SYNC2 PF[15:0] 3.3V 3 SW2: Video Sync Signals and Encoder Enable Select Defalut = OFF, OFF, OFF, OFF, OFF, ON Position Function 1-5 Connect video sync signals to DSP ON = PF2 Used to enable or disable 6 the encoder digital interface OFF = Encoder digital interface always disabled 15 AGND1 AGND2 DGND1 AGND3 DGND2 AGND4 DGND3 AGND5 DGND4 NC[AGND6] DGND5 3 9 14 31 71 ANALOG DEVICES C74 0.01UF 805 AGND2 Size Board No. C Date B 2 18 Title ADSP-BF561 EZ-KIT LITE: A 1 17 A1.8V 4 VDEC_CLKOUT 2 ADV7183AKST LQFP80 PVDD_ADV7183 DNP FER1 600 1206 FER2 600 1206 R41 33 805 U10 1 SWT017 DIP6 55 C56 0.1UF 805 PPI0_D4 AIN6 NC[DV] 48 76 3.3V NC[AFF] 51 PPI0_D5 AIN4 VS VIDEO_AVIN5 75 PPI0_D[15:0] AIN8 LLC1 TP2 VIDEO_AVIN4 AIN2 PPI0_D6 1 AVIN5 74 2 AVIN4 PPI0_D7 3 66 AVIN1 73 4 28 XTAL 5 29 VDEC_27MHZ_CLK 6 AVIN1 AVIN4 AVIN5 U4 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD VIDEO ENCODER (VIDEO IN) Rev A0185-2003 1.2B Sheet 12-16-2003_17:45 D 10 of 15 A B C D 3.3V 3.3V 3.3V R248 10K 805 PF5 R242 100 805 3 1 R247 0.00 1206 U47 SW6 SWT013 SPST-MOMENTARY R98 10K 805 4 74LVC14A SOIC14 R246 10K 805 U47 1 CT25 1UF A U47 2 74LVC14A SOIC14 13 1 12 74LVC14A SOIC14 5V 3.3V 3.3V 3.3V POWER LED1 GREEN-SMT LED001 R249 10K 805 R119 680 1206 RESET LED2 RED-SMT LED001 USB RESET LED3 RED-SMT LED001 R120 270 1206 3.3V PF6 R243 100 805 U47 11 SW7 SWT013 SPST-MOMENTARY R185 10K 805 R223 0.00 1206 R193 270 1206 10 74LVC14A SOIC14 CT26 1UF A 2 1 U28 4 R229 10K 805 RESET 2 U46 1 SW1 SWT013 SPST-MOMENTARY 4 3.3V MR PFI 2 SN74AHC1G00 SOT23-5 8 RESET 7 RESET 5 PFO RESET ADM708SAR SOIC8 R250 10K 805 PF7 R244 100 805 R224 0.00 1206 U47 9 SW8 SWT013 SPST-MOMENTARY 8 74LVC14A SOIC14 3.3V CT27 1UF A C158 0.1UF 805 3 C159 0.1UF 805 3.3V R184 0.00 805 PF[15:0] TX PF5 2 11 PF6 6 PF7 4 9 PF8 5 8 TFS0 6 6 RSCLK0 5 74LVC14A SOIC14 10 4 5 3 3 R225 0.00 1206 U47 CT28 1UF A PF5 2 R245 100 805 SW9 SWT013 SPST-MOMENTARY ON 12 1 PF8 1 RX R192 0.00 805 2 FER21 600 603 6 V- P2 T1IN T1OUT T2IN T2OUT 12 FER19 600 603 14 FER20 600 603 13 C148 0.1UF 805 FER18 600 603 8 9 DNP 5 TSCLK0 SWT017 DIP6 SW4 PB Enable Switch Default = ON, ON, ON, ON, OFF, OFF Position Function Connects the push buttons to the Programmable Flags of the DSP 1-4 Useful if using the PFs for another purpose. OFF, OFF = AD1836A -> TDM Mode 5,6 ON, ON = AD1836A -> I2S Mode DB9M 9PIN ANALOG DEVICES Title ADSP-BF561 EZ-KIT LITE: Size Board No. C Date A UART 3 4 NOTE: Remove R192 when populating R191 and R184 4 6 2 7 PF6 7 1 7 R1OUT R1IN 9 8 R2OUT R2IN ADM3202ARN SOIC16 R191 0.00 805 RFS0 3 IDC2X1 2X1 2 V+ 4 C2+ 5 C2- 11 P1 1 C147 0.1UF 805 1 C1+ 3 C1- 10 DNP SW4 R251 10K 805 U21 B 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD RESET, PUSH-BUTTON SWITCHES, UART Rev A0185-2003 1.2B Sheet 12-16-2003_15:28 D 11 of 15 A B C D EXPANSION INTERFACE (TYPE B) 5V 3.3V D[31:0] A[25:2] 5V 3.3V J1 1 2 1 4 3 6 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 22 24 23 26 25 8 7 A2 A5 10 9 A4 A7 12 11 A6 A9 14 13 A8 16 15 18 17 A12 A15 20 19 A14 A17 22 21 A16 A19 24 23 A18 28 27 30 29 32 31 34 33 36 35 38 37 40 39 42 41 PPI0_D5 44 43 PPI0_D4 PPI0_D7 46 45 PPI0_D6 PPI0_D9 48 47 PPI0_D11 50 PPI0_D13 J3 2 1 4 3 6 5 8 7 PPI1_D2 10 9 PPI1_D3 PPI1_D4 12 11 PPI1_D5 19 PPI1_D6 14 13 PPI1_D7 21 PPI1_D8 16 15 PPI1_D9 PPI1_D10 18 17 PPI1_D11 PPI1_D12 20 19 PPI1_D13 PPI1_D14 22 21 PPI1_D15 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39 PPI0_D8 42 41 49 PPI0_D10 44 43 52 51 PPI0_D12 46 45 PPI0_D15 54 53 PPI0_D14 48 47 PF2 56 55 PF3 50 49 PF0 58 57 PF1 52 51 60 59 54 53 62 61 56 55 64 63 58 57 66 65 60 59 68 67 62 61 70 69 64 63 72 71 66 65 74 73 68 67 76 75 70 69 78 77 72 71 80 79 74 73 82 81 76 75 84 83 78 77 86 85 80 79 88 87 82 81 90 89 84 83 86 85 88 87 90 89 MOSI MISO A10 A13 PF5 A21 26 25 A20 A23 28 27 A22 PPI0_SYNC2 PF0 A25 D1 D3 D5 2 PF[15:0] 3 29 32 31 DT1SEC 34 33 DT1PRI 36 35 TFS1 38 37 TSCLK1 40 39 42 41 44 43 D0 DT0SEC D2 DT0PRI D4 TFS0 TSCLK0 45 D6 D9 48 47 D8 50 49 52 51 53 D14 D17 56 55 D16 D19 58 57 D18 D21 60 59 D20 D23 62 61 D22 D25 64 63 D24 ABE3 D27 66 65 D26 ABE2 D29 68 67 D28 ABE1 69 PPI0_D0 72 71 PPI0_D2 74 73 ABE0 D30 AOE EXP_PPI0_CLK AWE PPI0_D1 PF14 76 75 PPI0_D3 SMS2 PF12 78 77 PF15 SMS0 PF10 80 79 PF13 PF8 82 81 PF11 PF6 84 83 PF9 PF4 86 TX NMI0 PPI0_SYNC3 PPI0_SYNC1 DR1SEC DR1PRI RFS1 RSCLK1 RESET DR0SEC DR0PRI VDEC_HS RFS0 VDEC_FIELD RSCLK0 VDEC_HREF DSP_VDD_EXT PPI1_SYNC2 PPI1_D1 RX EXP_PPI1_CLK CLK_OUT_EXP1 EXT_DSP_CLK VDEC_VS 85 SRAS PF7 88 87 SA10 90 89 SWE 45X2 CON019 AMS3 AMS2 AMS1 AMS0 ARDY ARE SMS3 SMS1 SCKE SCAS CLK_OUT_EXP2 45X2 CON019 EXT_27MHZ_CLK 2 VDEC_VREF DSP_3V_VOUT PPI1_SYNC3 PPI1_SYNC1 D12 54 70 SCK D10 D15 D31 PPI1_D0 A24 46 D13 PPI0_D[15:0] 30 D7 D11 PPI1_D[15:0] 5 A3 A11 1 J2 2 3 BR BG BGH 45X2 CON019 SPORT0 DT0PRI R72 0.00 1206 DT0SEC TFS0 TSCLK0 4 P3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CON014 10X2 RSCLK0 ANALOG DEVICES RFS0 R80 0.00 1206 DR0SEC DR0PRI Title ADSP-BF561 EZ-KIT LITE: Size Board No. C Date A B 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD EXTENDER CARD CONNECTORS Rev A0185-2003 1.2B Sheet 12-10-2003_18:18 D 12 of 18 A B C 5V F1 2.5A FUS001 FER5 CHOKE_COIL 1 4 3 1 2 D3 2A DO-214AA UNREG_IN 3 INPUT GND 1 1 D2 2A DO-214AA 2 R157 100K 1206 CT23 10UF C FER6 600 1206 UNREG_IN 2 OUTPUT1 4 OUTPUT2 J7 C160 1000PF 1206 A5V R163 0.00 1206 VR1 D C122 0.1UF 805 ADP3339AKC-5 SOT-223 A3V 3V_B VR3 3 INPUT CT24 10UF C C29 0.1UF 805 GND 1 3 7.5V_POWER CON005 2.5MM_JACK R73 0.00 1206 2 OUTPUT1 4 OUTPUT2 1 FER16 600 1206 ADP3338AKC-33 SOT-223 C32 1UF 805 CT17 10UF C C35 0.1UF 805 C153 1000PF 1206 3.3V NOTE: R252 or R253 gets populated R83 0.00 805 Default is R252 IN and R253 OUT DSP_VDD_EXT R252 0.00 805 SHGND DSP_VCORE DSP_VDD_INT TP7 DSP_VDD_EXT UNREG_IN DSP_3V_VOUT VR6 3 GND 1 2 CT20 10UF C R253 0.00 805 2 OUTPUT1 4 OUTPUT2 INPUT R84 0.00 805 U29 DNP ADP3339AKC-33 SOT-223 C53 0.1UF 805 CT21 10UF C R195 3.32K 805 VROUT L11 10UH IND001 1 5 2 6 3 7 4 8 D7 2A DO-214AA DNP 3 1 NDS8434A SO-8 R82 0.00 805 CT22 68UF D D5 ZHCS1000 SOT23D 1A 2 DSP_VDD_INT C48 0.1UF 805 3.3V UNREG_IN D4 CMDSH-3 100MA SOD-323 R78 10K 805 VR5 2 VIN R79 0.00 805 5 SHDN C43 2.2UF 805 BOOST SW 8 SYNC FB 4 GND VC L10 1.5UH IND003 R74 0.00 805 6 SD R180 17.4K 805 6 7 C46 2200PF 1206 D6 SL22 2A DO-214AA R194 3.32K 805 R186 10.0K 1206 C169 4.7UF 805 OUT2 OUT3 3 LT1765 SO-8 3 C170 0.18UF 805 1 OUT1 1 1V2 R75 53.6K 805 3 R77 0.00 805 C45 1UF 805 1 OUT1 2 OUT2 3 OUT3 5 FB GND 4 ADP3336ARM MSOP8 6 SD C44 1UF 805 CT18 10UF C R48 76.8K 1206 C21 1UF 805 R76 1M 805 A1.8V FER4 600 1206 VR2 7 IN1 8 IN2 R52 10K 805 2 5 FB GND 4 ADP3336ARM MSOP8 1.8V R81 0.00 805 3.3V VR4 7 IN1 8 IN2 3.3V C24 1UF 805 R56 147K 1206 CT19 100UF C 3 FER3 600 1206 MH2 MH1 MH3 MH4 MH5 3.3V FPGA_1V8 TP8 TP5 TP11 TP10 TP6 TP4 TP9 R207 332K 805 SHGND FER8 600 1206 VR7 2 INPUT 6 SD C218 0.47UF 805 4 3 ERR 1 OUTPUT 5 FB GND 4 ADP3331ART SOT23-6 R90 0.00 1206 C230 0.47UF 805 R211 340K 805 SHGND SHGND ANALOG DEVICES R210 698K 805 Title ADSP-BF561 EZ-KIT LITE: Size Board No. C Date A B 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD POWER Rev A0185-2003 1.2B Sheet 12-11-2003_13:22 D 13 of 18 A B C D DSP_VDD_EXT DSP_VDD_INT 1 C137 0.01UF 805 C140 0.01UF 805 C49 0.01UF 805 C174 0.01UF 805 C30 0.1UF 805 C151 0.1UF 805 C179 0.1UF 805 C155 0.1UF 805 C175 0.1UF 805 C51 0.1UF 805 C31 10UF 1210 C50 10UF 1210 C47 10UF 1210 C173 0.01UF 805 C154 0.01UF 805 C145 0.1UF 805 C172 0.1UF 805 C178 0.1UF 805 C152 0.1UF 805 C176 0.01UF 805 C138 0.01UF 805 C52 0.1UF 805 C164 0.1UF 805 C139 0.1UF 805 C171 0.1UF 805 C177 0.1UF 805 C167 0.1UF 805 C146 0.01UF 805 C41 0.01UF 805 1 ADSP-DM203 3.3V 3.3V C126 0.1UF 805 C135 0.1UF 805 27MHZ OSC U3 C136 0.01UF 805 3.3V 5V C134 0.01UF 805 C168 0.01UF 805 A5V C19 0.1UF 805 C37 0.1UF 805 3 C156 0.01UF 805 C183 0.1UF 805 C184 0.1UF 805 C185 0.01UF 805 C22 0.1UF 805 A5V C108 0.22UF 805 AGND 3.3V C186 0.01UF 805 C201 0.01UF 805 C200 0.01UF 805 C182 0.01UF 805 A5V C107 0.22UF 805 A5V C162 0.22UF 805 A5V C143 0.22UF 805 A5V C129 0.22UF 805 AGND AGND AGND AGND AGND AGND AD8606 U15 AD8606 U16 AD8606 U17 AD8606 U18 AD8606 U19 AD8606 U20 3V_B 3.3V 3.3V A3V C20 0.1UF 805 SN74AHC1G08 U21 3.3V 3.3V C75 0.01UF 805 C85 0.1UF 805 C70 0.01UF 805 AGND AGND AD8606 U13 C83 0.1UF 805 AGND2 AGND2 AD8061 U23 AD8061 U24 3.3V 2 3.3V AGND2 3.3V C106 0.22UF 805 AD8606 U12 A3V AD8061 U22 3.3V A5V C125 0.22UF 805 74LVC14A U10 A3V C71 0.1UF 805 A5V C256 0.01UF 805 74LVC00AD U9 3.3V C104 0.22UF 805 3.3V C180 0.01UF 805 SDRAM U8 A5V C131 0.1UF 805 AD1836 U14 C157 0.01UF 805 3.3V M29W640D U5 IDT2305 U4 2 U1 3.3V C69 0.01UF 805 3.3V C149 0.01UF 805 C150 0.01UF 805 ADG752 U25 3.3V ADG752 U26 3 3.3V DVDD_ADV7183 C101 0.01UF 805 C114 0.01UF 805 C91 0.1UF 805 C89 0.1UF 805 C102 0.1UF 805 C90 0.1UF 805 C109 0.1UF 805 C110 0.1UF 805 C113 0.01UF 805 ADV7179 U27 C112 0.01UF 805 C87 0.1UF 805 C111 0.1UF 805 C88 0.1UF 805 C249 0.01UF 805 ADM708SAR U29 ADV7183 U28 C141 0.01UF 805 ADM3202 U30 C181 0.01UF 805 IDT74FCT3244APY U31 C127 0.01UF 805 IDT74FCT3244APY U36 C165 0.01UF 805 C166 0.01UF 805 ADG752 U40 ADG752 U45 C27 0.1UF 805 IDT2305 U46 C28 0.01UF 805 C132 0.1UF 805 39MHZ OSC U54 3.3V C189 0.1UF 805 4 C191 0.1UF 805 C202 0.01UF 805 C203 0.01UF 805 C190 0.01UF 805 C187 0.01UF 805 ANALOG DEVICES C188 0.01UF 805 Title ADSP-BF561 EZ-KIT LITE: Size SDRAM U53 C Date A Board No. B 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD DECOUPLING CAPS Rev A0185-2003 1.2B Sheet 12-10-2003_18:18 D 14 of 18 A B C D All USB interface circuitry is considered propreitary andh has been omitted from this schematic When designin your JTAG interface please refer to the Engineer to Engineer Note EE-68 which can be found at http://www.analog.com 1 1 3.3V U36 EMULATOR_TMS EMULATOR_TCK EMULATOR_TRST R239 10K 805 R241 10K 805 EMULATOR_TDI 2 I0A 3 I1A 5 I0B 6 I1B 11 I0C 10 I1C 14 I0D 13 I1D TMS 4 YA R87 0.00 805 7 YB TCK 9 YC TRST 12 YD TDI 1 S 15 E 3.3V ADG774A QSOP16 P4 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 2 R201 10K 805 U37 EMULATOR_EMU EMULATOR_TDO IDC7X2 7X2 DSP JTAG HEADER 2 I0A 3 I1A 5 I0B 6 I1B 11 I0C 10 I1C 14 I0D 13 I1D 4 YA EMU 7 YB TDO 9 YC 12 YD 1 S 15 E ADG774A QSOP16 3 3 3.3V 3.3V C196 0.1UF 402 12.288MHz 3.3V C195 0.1UF 402 ADG774A C209 0.1UF 402 ADG774A ANALOG DEVICES 4 Title ADSP-BF561 EZ-KIT LITE: Size Board No. C Date A B 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD DEBUG AGENT - JTAG Rev A0185-2003 1.2B Sheet 12-16-2003_15:28 D 15 of 15 A B C D 1 1 2 2 ADSP-BF561 EZ-KIT Lite Schematic 3 3 ANALOG DEVICES 4 Approvals Drawn JSZ Checked Engineering A B C Date Title ADSP-BF561 EZ-KIT LITE: 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD TITLE 10/10/03 Size Board No. C Date Rev A0185-2003 1.3A Sheet 12-16-2003_11:50 D 1 of 18 A B C D U48 D0 D[31:0] 1 B16 D1 C15 D2 E12 D3 C16 D4 E14 D5 D15 D6 D16 D7 E15 D8 F13 D9 F15 D10 F12 D11 F16 D12 F14 3.3V D13 G15 D14 G13 D15 G12 A[25:2]_S D0 A2 D1 A3 D2 A4 D3 A5 D4 A6 D5 A7 D6 A8 D7 A9 D8 A10 D9 A11 D10 A12 D11 A13 D12 A14 D13 A15 D14 A16 D15 A17 R42 10K 805 D16 R60 33 805 U14 1 OE OUT 3 H12 D17 H15 D18 H13 D19 H16 D20 H14 D21 J15 OSC_30MHZ 30.0000MHZ OSC003 R51 DNP 805 EXT_DSP_CLK D22 J13 D23 J16 D24 K14 D25 K15 D26 K13 D27 L15 3.3V 2 R160 10K 805 R196 10K 805 D28 K12 D29 L16 D30 D31 J12 M15 D16 A18 D17 A19 D18 A20 D19 A21 D20 A22 D21 A23 D22 A24 D23 A25 B12 ARDY F1 3.3V G1 D27 D28 D29 D30 SDQM0/ ABE0 SDQM1/ ABE1 SDQM2/ ABE2 SDQM3/ ABE3 BR BGH ARDY ARE RESET CLKIN AMS1 XTAL AMS2 SRAS SCAS R170 10K 805 SWE SA10 SMS0 3 DSP_BYPASS BMODE0 G4 M10 BMODE1 N10 BYPASS SMS1 SMS2 BMODE0 SMS3 BMODE1 SCKE P11 NMI0 NMI1 R9 A5_S B14 A6_S C14 A7_S A2_S 1 F11 A8_S A3_S 2 RN4 D7 A9_S A4_S 3 A6 A10_S A5_S 4 C6 A11_S A12_S E6 A13_S A5 A14_S A6_S 1 E5 A15_S A7_S 2 B4 A16_S A8_S 3 A17_S B3 A18_S A9_S 4 A3 A20_S F5 A21_S A10_S 1 B2 A22_S A11_S 2 D4 A23_S A12_S 3 C3 A25_S R2B R3A R3B R4A R4B 1 BMODE0 2 BMODE1 ON ON RESERVED OFF ON 8-BIT FLASH ON OFF SPI SROM 8-BIT OFF OFF SPI SROM 16-BIT A13_S NMI0 SCLK0 NMI1 SCLK1 6 A4 5 A5 R1A R1B R2A R2B R3A R3B R4A R4B 8 A6 7 A7 1 A15_S 2 A16_S 3 A17_S 4 R1A R2A R3A R4A 4 R1B R2B R3B R4B 8 A14 7 A15 6 A16 5 A17 8 A18 7 A19 6 A20 5 A21 8 A22 7 A23 6 A24 5 A25 E11 ABE0_S 1 B13 ABE1_S 2 A14 ABE2_S 3 A15 ABE3_S 4 A13 6 A8 5 A18_S 1 A19_S 2 A20_S 3 A21_S 4 R1A R2A A9 R3A R4A R1B R2B R3B R4B R1A R1B R2A R2B R3A R3B R4A R4B 8 A10 7 A11 6 A12 RN8 5 A22_S 1 A23_S 2 A24_S 3 A25_S 4 R1A R2A A13 R3A R4A R1B R2B R3B R4B A[25:2] R1A R1B R2A R2B R3A R3B R4A R4B 8 C12 7 ABE1 6 ABE2 5 ABE3 BGH C7 AOE B8 ARE A8 AWE C8 AMS0 B7 AMS1 E7 AMS2 A7 AMS3 RN10 C10 SRAS_S 1 D10 SCAS_S 2 E10 SWE_S 3 D11 SA10_S 4 E9 SMS0_S B9 SMS1_S C9 SMS2_S A10 SMS3_S 1 2 B10 A11 SCKE 3 SCLK0_S 4 A12 R1A R1B R2A R2B R3A R3B R4A R4B 8 SRAS 7 SCAS 6 SWE 5 SA10 10 RA8/38V RN9 SCLK1_S 3 R1A R1B R2A R2B R3A R3B R4A R4B 8 SMS0 7 SMS1 6 SMS2 5 SMS3 R187 22 805 SCLK0 3.3V U20 1 REF CLKOUT CLK1 DEFAULT 6 VDD 4 GND CLK3 CLK4 R68 22 805 8 3 CLK_OUT_EXP1 2 R67 22 805 5 CLK_OUT_EXP2 7 R65 22 805 IDT2305-1DC SOIC8 SW3 ON 1 3 6 4 5 2 3 ANALOG DEVICES 8 7 2 ABE0 10 RA8/38V BG SCLK1 2 1 10 RA8/38V CLK2 DNP 4 SWT018 DIP4 Approvals Drawn JSZ Checked Engineering A A14_S RN6 R176 10K 805 BOOT MODE 4 RN12 10 RA8/38V R188 22 805 1 A3 RN7 ADSP-BF561SKBC-600 MBGA256 SW3: BOOT MODE/BYPASS Select (Default = OFF, ON, ON, OFF) 7 10 RA8/38V 10 RA8/38V R169 10K 805 A2 10 RA8/38V A19_S A24_S R2A 8 RN5 C4 A2 R1B 10 RA8/38V B5 F6 R1A D31 AMS3 R168 10K 805 G10 RN11 C42 0.1UF 805 DNP R167 10K 805 A4_S D26 AMS0 DSPCK_30MHZ A3_S B15 10 RA8/38V AWE F3 RESET G11 D25 AOE D9 A2_S D24 BG BR D13 B C Date Title ADSP-BF561 EZ-KIT LITE: 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD DSP - EXT MEM INTERFACE 10/10/03 Size Board No. C Date Rev A0185-2003 1.3A Sheet 5-12-2004_16:35 D 2 of 18 A B C D U48 P15 RSCLK0 1 R16 RFS0 L12 DR0PRI P16 DR0SEC N16 TSCLK0 L13 TFS0 M16 DT0PRI N15 DT0SEC RSCLK0/PF28 PF15/TMRXCLK RFS0/PF19 PF14 DR0PRI PF13 DR0SEC/PF20 PF12 TSCLK0/PF29 PF11 TFS0/PF16 PF10 DT0PRI/PF18 PF9 DT0SEC/PF17 PF8 PF7/SPIS7/TMR7 P13 RSCLK1 N13 RFS1 M12 DR1PRI T14 DR1SEC R14 TSCLK1 P14 TFS1 R15 DT1PRI T15 DT1SEC RSCLK1/PF30 PF6/SPIS6/TMR6 RFS1/PF24 PF5/SPIS5/TMR5 DR1PRI PF4/SPIS4/TMR4 DR1SEC/PF25 PF3/SPIS3/TMR3 TSCLK1/PF31 PF2/SPIS2/TMR2 TFS1/PF21 PF1/SPIS1/TMR1 DTIPRI/PF23 PF0/SPISS/TMR0 P8 PF15 R8 PF14 N8 PF13 T7 PF12 P7 PF11 PF[15:0] 1 RN1 R7 N6 R6 PF15 1 PF14 2 PF13 3 PF10 PF9 PF8 4 R1A R2A R1B R2B R3A R3B R4B M7 PF7 R4A T5 PF6 10 RA8/38V P6 PF5 R5 PF4 M6 PF3 T4 PF2 N5 PF1 P4 PF0 8 AD1836_RESET 7 VENC_RESET 6 VDEC_RESET 5 DT1SEC/PF22 PROGR. FLAG T13 RX R13 TX N11 MOSI 2 R12 MISO 3.3V M11 SCK R10 T10 T9 R85 10K 805 R200 10K 805 R179 10K 805 P10 RX/PF27 SLEEP TX/PF26 MOSI MISO SCK TDI TDO N9 TDO TMS TCK TRST EMU FUNCTION T11 R11 EMU PF15 AD1836 CODEC RESET PF14 ADV7179 VIDEO ENCODER RESET PF13 ADV7183A VIDEO DECODER RESET PF12 GENERAL PURPOSE PF11 GENERAL PURPOSE PF10 GENERAL PURPOSE PF9 GENERAL PURPOSE PF8 GENERAL PURPOSE / PUSH BUTTON STATUS INPUT PF7 GENERAL PURPOSE / PUSH BUTTON STATUS INPUT PF6 GENERAL PURPOSE / PUSH BUTTON STATUS INPUT/ UART SIGNAL PF5 GENERAL PURPOSE / PUSH BUTTON STATUS INPUT/ UART SIGNAL 2 PF4 GENERAL PURPOSE / AD1836 LATCH SIGNAL TDI PF3 GENERAL PURPOSE / VIDEO DECODER FIELD TMS PF2 GENERAL PURPOSE / VIDEO DECODER OUTPUT ENABLE PF1 GENERAL PURPOSE / I2C SERIAL DATA PF0 GENERAL PURPOSE / I2C SERIAL CLOCK TCK ADSP-BF561SKBC-600 MBGA256 TRST R86 4.7K 805 DSP_VDD_EXT DSP_VDD_INT U48 A1 A16 A4 A9 B11 B6 D12 E16 F2 G16 G3 J6 K16 K6 L10 L5 M14 T1 T12 T16 T3 T6 T8 3 C11 C13 C5 D14 D5 D6 D8 E1 E13 F10 F8 G14 G2 G6 G7 G8 H1 H10 H2 H8 H9 4 VDDEXT1 VDDEXT2 VDDEXT3 VDDEXT4 VDDEXT5 VDDEXT6 VDDEXT7 VDDEXT8 VDDEXT9 VDDEXT10 VDDEXT11 VDDEXT12 VDDEXT13 VDDEXT14 VDDEXT15 VDDEXT16 VDDEXT17 VDDEXT18 VDDEXT19 VDDEXT20 VDDEXT21 VDDEXT22 VDDEXT23 VDDINT1 VDDINT2 VDDINT3 VDDINT4 VDDINT5 VDDINT6 VDDINT7 VDDINT8 VDDINT9 VDDINT10 VDDINT11 VDDINT12 VDDINT13 VDDINT14 VROUT1 VROUT2 NC0 NC1 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND41 GND40 GND39 GND38 GND37 GND36 GND35 GND34 GND33 GND32 GND31 GND30 GND29 GND28 GND27 GND26 GND25 GND24 GND23 GND22 ADSP-BF561SKBC-600 MBGA256 E8 F7 F9 G9 H11 H6 H7 J10 J8 J9 K11 K8 L8 M8 J1 3 VROUT J2 M5 M13 P9 P5 P2 P12 N7 N14 N12 M9 M4 L9 L7 L3 L14 L11 K9 K7 K10 J7 J14 J11 ANALOG DEVICES Approvals Drawn JSZ Checked Engineering A B C Date Title ADSP-BF561 EZ-KIT LITE: 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD DSP - PROGR. FLAGS, SPI 10/10/03 Size Board No. C Date Rev A0185-2003 1.3A Sheet 5-6-2004_16:04 D 3 of 18 A B C D SW5: PPI CLK Routing Select (Default: 1 = OFF, 2 = ON, 3 = ON, 4 = ON) 1 or 3 PPIxCLK_SEL0 2 or 4 PPIxCLK_SEL1 PPIxCLK ON ON PPI_27MHZ_CLK OFF ON VDEC_CLKOUT X OFF EXPANSION_CLK 3.3V 3.3V R166 33 805 VDEC_27MHZ_CLK R165 33 805 1 R162 10K 805 U22 3 R174 10K 805 VENC_27MHZ_CLK 3.3V R175 10K 805 R182 10K 805 R181 10K 805 R171 33 805 R59 33 805 U17 1 OE OUT 3 U23 1 1 R66 0.00 805 3 6 1 PPI0_CLK 6 4 EXT_27MHZ_CLK U19 4 OSC_27M OSC27M 1 REF CLKOUT CLK1 27MHZ OSC003 CLK2 6 VDD CLK3 4 GND CLK4 8 ADG752BRT SOT23-6 3 ADG752BRT SOT23-6 EXP_PPI0_CLK 2 R172 33 805 5 U26 7 PPI_27MHZ_CLK 3 U25 1 IDT2305-1DC SOIC8 SW5 1 6 VDEC_CLKOUT 2 7 PPI0CLK_SEL1 3 6 PPI1CLK_SEL0 4 5 PPI1CLK_SEL1 ON PPI0CLK_SEL0 1 8 R178 0.00 805 3 1 PPI1_CLK 6 4 2 4 3 4 SWT018 DIP4 ADG752BRT SOT23-6 ADG752BRT SOT23-6 EXP_PPI1_CLK U48 2 PPI0_D[15:0] PPI0_D15 D2 PPI0_D14 G5 PPI0_D13 D1 PPI0_D12 E3 PPI0_D11 E2 PPI0_D10 F4 PPI0_D9 H3 PPI0_D8 K3 PPI0_D7 H4 PPI0_D6 K1 H5 PPI0_D4 K2 PPI0_D3 J4 PPI0_D2 J3 PPI0_D1 J5 PPI0_D0 L1 3 PPI0_D13/PF45 PPI1_D13/PF37 PPI0_D12/PF44 PPI1_D12/PF36 PPI0_D11/PF43 PPI1_D11/PF35 PPI0_D10/PF42 PPI1_D10/PF34 PPI0_D9/PF41 PPI1_D9/PF33 PPI1_D8/PF32 PPI0_D7 PPI1_D7 PPI0_D6 PPI1_D6 PPI0_D5 PPI1_D5 PPI0_D4 PPI1_D4 PPI0_D3 PPI1_D3 PPI0_D2 PPI1_D2 PPI1_D1 PPI1_D0 PPI0_CLK C1 D3 PPI0_SYNC3 PPI1_D14/PF38 PPI0_D0 E4 PPI0_SYNC2 PPI0_D14/PF46 PPI0_D1 C2 PPI0_SYNC1 PPI1_D15/PF39 PPI0_D8/PF40 PPI0_D5 PPI0_CLK PPI0_D15/PF47 PPI1_CLK PPI0_SYN1/TMR8 PPI1_SYN1/TMR10 PPI0_SYN2/TMR9 PPI1_SYN2/TMR11 PPI0_SYN3 PPI1_SYN3 M1 PPI1_D15 K5 PPI1_D14 M2 PPI1_D13 N1 PPI1_D12 L6 PPI1_D11 PPI1_D8 2 N2 PPI1_D10 PPI1_D9 4 M3 PPI1_D9 PPI1_D10 6 P1 PPI1_D8 PPI1_D11 8 R1 PPI1_D7 PPI1_D12 11 R2 PPI1_D6 PPI1_D13 13 PPI1_D14 15 PPI1_D15 17 2 PPI1_D[15:0] U13 1A1 1A2 1A3 1A4 2A1 2A2 P3 PPI1_D5 T2 PPI1_D4 N3 PPI1_D3 R3 PPI1_D2 1 N4 PPI1_D1 19 R4 PPI1_D0 2A3 2A4 18 1Y1 16 1Y2 14 1Y3 12 1Y4 9 2Y1 7 2Y2 5 2Y3 3 2Y4 OE1 LED20 AMBER-SMT LED001 OE2 LED19 AMBER-SMT LED001 LED18 AMBER-SMT LED001 LED17 AMBER-SMT LED001 LED16 AMBER-SMT LED001 LED15 AMBER-SMT LED001 LED14 AMBER-SMT LED001 LED13 AMBER-SMT LED001 IDT74FCT3244APY SSOP20 B1 PPI1_CLK K4 R237 270 1206 PPI1_SYNC1 L2 R236 270 1206 R235 270 1206 R234 270 1206 R233 270 1206 R232 270 1206 R231 270 1206 R230 270 1206 PPI1_SYNC2 L4 3 PPI1_SYNC3 ADSP-BF561SKBC-600 MBGA256 U30 PPI0_D8 2 PPI0_D9 4 PPI0_D10 6 PPI0_D11 8 PPI0_D12 11 PPI0_D13 13 PPI0_D14 15 PPI0_D15 17 1 19 18 1A1 1Y1 1A2 1Y2 1A3 1Y3 1A4 1Y4 2A1 2Y1 2A2 2Y2 2A3 2Y3 2A4 2Y4 16 14 12 9 7 5 3 OE1 OE2 LED12 AMBER-SMT LED001 LED11 AMBER-SMT LED001 LED10 AMBER-SMT LED001 LED9 AMBER-SMT LED001 LED8 AMBER-SMT LED001 LED7 AMBER-SMT LED001 LED6 AMBER-SMT LED001 LED5 AMBER-SMT LED001 ANALOG DEVICES IDT74FCT3244APY SSOP20 4 R220 270 1206 R219 270 1206 R218 270 1206 R217 270 1206 R216 270 1206 R215 270 1206 R214 270 1206 R213 270 1206 Approvals Drawn JSZ Checked Engineering A B C Date Title ADSP-BF561 EZ-KIT LITE: 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD DSP - PPI0 AND PPI1 10/10/03 Size Board No. C Date Rev A0185-2003 1.3A Sheet 5-12-2004_16:32 D 4 of 18 A B C FLASH A (8MB) D SDRAM 64MB (256Mb x 2 Chips) 4M x 16 D[31:0] 1 1 U32 A[25:2] U27 25 ABE3 A2 24 A3 23 A4 22 A5 21 A6 20 A7 19 A8 A9 8 A10 7 A11 6 A12 5 A13 3.3V 2 R190 10K 805 R177 10K 805 4 A14 3 A15 2 A16 1 A17 48 A18 17 A19 16 A20 R189 10K 805 18 9 A21 10 A22 13 26 AMS0 28 AOE 11 AWE 47 FLASH_WP 14 FLASH_RP 12 3.3V A0 A1 A2 VCC 37 A3 A4 D0 A5 D1 A6 D2 A7 D3 A8 D4 A9 D5 A10 D6 A11 D7 A12 D8 A13 D9 A14 D10 A15 D11 A16 D12 A17 D13 A18 D14 A19 D15 29 D0 31 D1 33 D2 35 D3 38 D4 40 D5 42 D6 44 D7 30 D8 32 D9 34 D10 36 D11 23 A3 24 A4 25 A5 26 A6 29 A7 30 A8 31 A9 32 A10 33 A11 34 SCAS 41 D13 SRAS 43 D14 45 D15 R183 10K 805 A20 D4 10 D5 11 D6 13 D7 42 D8 44 D9 DQ7 A8 DQ8 A9 DQ9 45 DQ10 47 DQ11 48 DQ12 50 DQ13 51 DQ14 53 DQ15 A10 A11 A12_NC 21 8 DQ6 A7 A19 D3 DQ5 A6 20 D2 7 DQ4 A5 A18 5 DQ3 A4 36 D1 DQ2 A3 A14 D0 4 DQ1 A2 35 2 DQ0 A1 A13 BA0 BA1 16 SWE 3.3V A0 22 SA10 D12 39 A2 D10 D11 D12 D13 D14 D15 19 CS 37 CKE 38 CLK WE 17 CAS 18 RAS SMS0 2 SCKE SCLK0 15 ABE0 DQML 39 ABE1 DQMH A21 CE RDY 15 MT48LC16M16A2TG-75 TSOP54 FLASH_RDY OE U33 WE BYTE VSS2 WP/VPP VSS1 46 A2 23 A3 24 A4 25 A5 26 A6 29 A7 30 A8 31 A0 27 RP M29W64OD TSOP48 A1 34 A7 36 A11 A12_NC A18 20 A19 21 D21 11 D22 13 D23 42 D24 44 D25 45 DQ10 47 DQ11 48 DQ12 50 DQ13 51 DQ14 53 DQ15 D26 DQ9 A10 A14 D20 10 DQ8 A9 35 8 DQ7 A8 A13 D19 DQ6 22 3 D18 7 DQ5 A6 A11 5 DQ4 A5 33 D17 DQ3 A4 32 4 DQ2 A3 A9 D16 DQ1 A2 A10 2 DQ0 BA0 BA1 3 D27 D28 D29 D30 D31 Memory Map 16 START 0x0000 0000 0x2000 0000 END 0x03FF FFFF 0x207F FFFF BANK SDRAM Bank 0 ASYNC Memory Bank 0 19 CS 37 CKE 38 CLK WE DEVICE 17 CAS 18 64MB SDRAM 8MB FLASH RAS ABE2 ABE3 15 DQML 39 DQMH MT48LC16M16A2TG-75 TSOP54 ANALOG DEVICES 4 Approvals Drawn JSZ Checked Engineering A B C Date Title ADSP-BF561 EZ-KIT LITE: 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD MEMORY - FLASH & SDRAM 10/10/03 Size Board No. C Date Rev A0185-2003 1.3A Sheet 12-16-2003_11:03 D 5 of 18 A B C D ADC2 ADC1 R61 33 805 U16 1 OE 1 DAC1 R161 10K 805 DAC2 DAC3 3.3V LEFT (WHITE) OUT 3 AD1836_CLK RIGHT (RED) 1 12.288MHZ OSC003 OUT (J4) R18 5.49K 1206 IN (J5) R145 11.0K 1206 C7 100PF 1206 R138 3.32K 1206 OUT1R- C96 330PF 805 3.3V 6 U5 7 DAC1 RIGHT 5 C117 680PF 805 R30 5.49K 1206 R57 10K 805 AD8606AR SOIC8 R29 1.65K 1206 R126 604 1206 OUT1R+ AUDIO CODEC J5 3X2 CON024 CT8 10UF CAP002 DAC1_RIGHT 7 U15 47 DR0PRI OUT1L+ OUT1L+ ASDATA2 9 OUT1L- OUT1L- 48 DR0SEC 44 RFS0 31 ABCLK OUT1R+ OUT1R+ 30 2 OUT1R45 AD1836_CLK OUT1R- 6 CLATCH 51 SCK ADC1 LEFT R46 10K 805 R45 10K 805 ADC1 RIGHT IN1L+ OUT3L+ OUT3L+ IN1L- 5 OUT3L- OUT3L- OUT2R+ 32 OUT2R- 4 35 IN1R+ 19 IN1R- DAC1 RIGHT 2 DAC2 LEFT AGND 33 OUT2R- 18 IN1R+ OUT2L- OUT2R+ 17 IN1L- OUT2L+ 7 OUT2L- COUT 16 IN1L+ R47 10K 805 OUT2L+ CDATA 49 MISO 9 R109 49.9K 1206 C77 2200PF 1206 CCLK 2 MOSI C14 220PF 1206 MCLK 50 PF4 R151 2.74K 1206 DAC1 LEFT ALRCLK 43 RSCLK0 8 ASDATA1 OUT3R+ OUT3R+ 34 IN1R- OUT3R- OUT3R- DAC2 RIGHT DAC3 LEFT R17 5.49K 1206 R144 11.0K 1206 DAC3 RIGHT C6 100PF 1206 R137 3.32K 1206 OUT1L20 IN2L+/CL2/CL2 21 ADC2 LEFT DSDATA2 NC/IN2L1/IN2L+ DSDATA3 NC/IN2L2/IN2L- DLRCLK 23 IN2L2 IN2R2 ADC2 RIGHT IN2R1 3 42 TSCLK0 26 IN2R-/CR1/CR1 27 U5 3 R159 0.00 1206 C116 680PF 805 R27 5.49K 1206 AD8606AR SOIC8 R28 1.65K 1206 C38 0.001UF 805 C39 0.001UF 805 3 DAC1_LEFT 8 CT16 10UF B C124 0.1UF 805 CT15 10UF B C123 0.1UF 805 R150 2.74K 1206 C13 220PF 1206 9 3 C133 0.001UF 805 R108 49.9K 1206 C76 2200PF 1206 AD1836AAS MQFP52 C40 0.001UF 805 J5 3X2 CON024 CT7 10UF CAP002 IN2R+/CR2/CR2 PD/RST R158 10K 805 R125 604 1206 OUT1L+ 3 AD1836_RESET DAC1 LEFT 13 FILTR 12 FILTD NC/IN2R1/IN2R+ 2 1 TFS0 37 NC/IN2R2/IN2R- 25 C95 330PF 805 DT0SEC 36 DBCLK 24 DT0PRI 41 IN2L-/CL1/CL1 22 IN2L1 DSDATA1 38 U12 1 AD1836_VREF AGND 2 AD8606AR SOIC8 R43 0.00 1206 R55 0.00 1206 AGND 5 U12 AGND 7 SW10: Audio Loopback For Test Purposes Default = All Off 6 AD8606AR SOIC8 SW10 ON 11 3 10 4 9 5 8 6 7 3 ADC2_LEFT 4 ADC2_RIGHT 12 2 2 ADC1_RIGHT 1 ADC1_LEFT 4 1 R44 0.00 1206 R71 0.00 1206 DAC1_LEFT DAC1_RIGHT 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD DAC2_LEFT Approvals DAC2_RIGHT 5 DAC3_LEFT AGND 6 DAC3_RIGHT SWT017 DIP6 Drawn JSZ Checked Engineering A ANALOG DEVICES B C Date Title ADSP-BF561 EZ-KIT LITE: AUDIO CODEC 10/10/03 Size Board No. C Date Rev A0185-2003 1.3A Sheet 5-12-2004_16:35 D 6 of 18 A B C D 1 1 R19 5.49K 1206 R146 11.0K 1206 C8 100PF 1206 R22 5.49K 1206 R139 3.32K 1206 OUT2R- R149 11.0K 1206 C97 330PF 805 2 C100 330PF 805 3 R31 5.49K 1206 C118 680PF 805 AD8606AR SOIC8 R32 1.65K 1206 R142 3.32K 1206 OUT3R- U6 1 DAC2 RIGHT C11 100PF 1206 6 U7 7 DAC3 RIGHT R128 604 1206 5 J5 3X2 CON024 CT10 10UF CAP002 OUT2R+ DAC2_RIGHT R38 5.49K 1206 4 C121 680PF 805 AD8606AR SOIC8 R37 1.65K 1206 R130 604 1206 R152 2.74K 1206 C15 220PF 1206 J5 3X2 CON024 CT12 10UF CAP002 OUT3R+ 6 AD1836_VREF DAC3_RIGHT 1 R111 49.9K 1206 C79 2200PF 1206 R155 2.74K 1206 C18 220PF 1206 3 R113 49.9K 1206 C81 2200PF 1206 2 2 AGND AGND R20 5.49K 1206 R147 11.0K 1206 C9 100PF 1206 R21 5.49K 1206 R140 3.32K 1206 R148 11.0K 1206 OUT2L- R141 3.32K 1206 OUT3L- C98 330PF 805 6 U6 C99 330PF 805 7 3 C10 100PF 1206 DAC2 LEFT 2 U7 5 R34 5.49K 1206 C119 680PF 805 AD8606AR SOIC8 R33 1.65K 1206 R127 604 1206 OUT2L+ 3 J5 3X2 CON024 CT9 10UF CAP002 DAC2_LEFT 5 R153 2.74K 1206 C16 220PF 1206 3 1 DAC3 LEFT R35 5.49K 1206 C120 680PF 805 AD8606AR SOIC8 R36 1.65K 1206 R129 604 1206 J5 3X2 CON024 CT11 10UF CAP002 OUT3L+ DAC3_LEFT 2 6 R110 49.9K 1206 C78 2200PF 1206 R154 2.74K 1206 C17 220PF 1206 3 R112 49.9K 1206 C80 2200PF 1206 AGND AGND ANALOG DEVICES 4 Approvals Drawn JSZ Checked Engineering A B C Date Title ADSP-BF561 EZ-KIT LITE: 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD AUDIO OUT 10/10/03 Size Board No. C Date Rev A0185-2003 1.3A Sheet 12-10-2003_18:18 D 7 of 18 A 1 J4 2X2 CON013 B CT5 10UF CAP002 FER10 600 1206 2 R121 5.76K 1206 C R49 5.76K 1206 1 J4 2X2 CON013 5 3 C62 100PF 1206 2 R123 5.76K 1206 R62 5.76K 1206 ADC2_LEFT 6 C142 120PF 1206 C72 100PF 1206 R53 237 1206 U11 AGND U18 2 1 IN1L- AGND AGND 1 AGND 3 C25 0.001UF 805 R50 5.76K 1206 AD8606AR SOIC8 C26 100PF 1206 R58 5.76K 1206 R63 5.76K 1206 ADC1 LEFT C130 120PF 1206 6 C23 0.001UF 805 R164 750K 1206 R54 237 1206 U11 U18 6 7 7 IN1L+ 5 2 ADC2 LEFT C144 120PF 1206 AGND R156 750K 1206 IN2L2 3 AD8606AR SOIC8 R40 5.76K 1206 CT13 10UF CAP002 FER12 600 1206 ADC1_LEFT C128 120PF 1206 D IN2L1 5 AD8606AR SOIC8 2 AD8606AR SOIC8 AGND AGND J4 2X2 CON013 CT6 10UF CAP002 FER11 600 1206 1 R122 5.76K 1206 J4 2X2 CON013 R15 5.76K 1206 ADC1_RIGHT 4 3 C103 120PF 1206 C63 100PF 1206 2 CT14 10UF CAP002 FER9 600 1206 R25 237 1206 U9 R69 5.76K 1206 ADC2_RIGHT 6 AGND R124 5.76K 1206 C161 120PF 1206 C61 100PF 1206 2 1 1 IN1R- AGND AGND 3 R8 5.76K 1206 AD8606AR SOIC8 C36 0.001UF 805 R16 5.76K 1206 C34 100PF 1206 R64 5.76K 1206 AGND 6 ADC1 RIGHT C33 0.001UF 805 R173 750K 1206 6 7 ADC2 RIGHT C163 120PF 1206 R26 237 1206 U9 3 R70 5.76K 1206 C105 120PF 1206 R132 750K 1206 IN2R2 3 AD8606AR SOIC8 3 U24 AGND U24 7 IN1R+ 5 IN2R1 5 AD8606AR SOIC8 AD8606AR SOIC8 AGND AGND AD1836_VREF ANALOG DEVICES 4 Approvals Drawn JSZ Checked Engineering A B C Date Title ADSP-BF561 EZ-KIT LITE: 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD AUDIO IN 10/10/03 Size Board No. C Date Rev A0185-2003 1.3A Sheet 12-10-2003_18:18 D 8 of 18 A B C D SW11 1 7 3 6 4 5 3 VIDEO_AVIN5 8 2 2 VIDEO_AVIN4 ON 1 VIDEO_AVIN1 VIDEO_DAC_A VIDEO_DAC_C VIDEO_DAC_B 4 SWT018 DIP4 SW11: Video Loopback For Test Purposes Default = All Off 1 R136 1K 1206 1 A3V VIDEO_DAC_A U3 L1 0.68UH 805 L5 2.2UH 805 L4 0.68UH 805 1 3 2 R114 75 1206 C92 330PF 805 C86 330PF 805 R104 75 1206 5 4 J6 3X2 CON024 R6 75 1206 8 DAC A DAC A DAC B DAC C Composite Video CVSB CVSB C Component Video G B R Differential Component Video Y U V S Video Y C AD8061ART SOT23-5 9 R10 1K 1206 AGND2 VIDEO ENCODER 3V_B R116 1K 1206 2 2 U8 VAA1 VAA2 VAA3 VAA4 VAA5 PPI1_D7 PPI1_D[15:0] 5 PPI1_D6 4 PPI1_D5 3 PPI1_D4 39 PPI1_D3 38 PPI1_D2 37 PPI1_D1 36 PPI1_D0 35 P7 DAC_A P6 DAC_B P5 DAC_C 1 P3 COMP P2 VREF P1 RSET 16 3 PF1 PF[15:0] PF0 22 21 CLOCK FIELD/VSYNC GND1 GND2 SDATA GND3 SCLOCK GND5 GND6 34 33 25 C115 0.1UF 805 C12 0.1UF 805 R23 1.2K 1206 U1 27 GND7 SCRESET/RTC GND8 TTX GND9 TTXREQ GND10 L9 2.2UH 805 L2 0.68UH 805 1 28 3 2 24 23 R135 75 1206 30 C94 330PF 805 C82 330PF 805 R4 75 1206 DAC B 5 AD8061ART SOT23-5 6 R115 1K 1206 31 13 VENC_HS 14 VENC_VS 15 R118 1K 1206 6 7 3 8 A3V 1 9 R3 150 1206 11 12 D1 AD1580 SOT23D VIDEO_DAC_C 2 U2 17 L6 0.68UH 805 26 L7 2.2UH 805 L3 0.68UH 805 1 3 40 2 R134 75 1206 R9 100K 1206 C93 330PF 805 C84 330PF 805 J6 3X2 CON024 R105 75 1206 5 4 19 ADV7179 LFCSP40 R143 10K 805 5 4 L8 0.68UH 805 29 J6 3X2 CON024 R107 75 1206 AGND2 ALSB 3V_B 32 R14 10K 805 RESET GND4 R13 100K 1206 VIDEO_DAC_B 18 P0 BLANK 20 VENC_RESET A3V 10 P4 HSYNC VENC_27MHZ_CLK 2 R5 75 1206 2 DAC C AD8061ART SOT23-5 3 R117 1K 1206 AGND2 R133 0.00 1206 ANALOG DEVICES 4 AGND2 Approvals Drawn JSZ Checked Engineering A B C Date Title ADSP-BF561 EZ-KIT LITE: 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD VIDEO ENCODER (VIDEO OUT) 10/10/03 Size Board No. C Date Rev A0185-2003 1.3A Sheet 5-12-2004_16:35 D 9 of 18 C DAC_D B DAC_B DAC_C A 3.3V (WHITE) OUT 1 D VIDEO DECODER R12 10K 805 (RED) IN R11 10K 805 R131 10K 805 R2 10K 805 Note: Signal Names in brackets refer to ADV7183KST 1 XTAL1 P15 P14 P13 Composite Video CVBS CVBS CVBS Differential Component Video Y S Video Y PF[15:0] V PF1 67 PF0 68 ALSB P12 SDA P11 SCLK P10 U P9 C 64 VDEC_RESET 36 J6 3X2 CON024 R99 0.00 805 7 AVIN1 P8 PWRDN P7 P6 R7 10K 805 C60 0.1UF 805 RESET 65 NC[ISO] P4 VIDEO_AVIN1 42 41 AIN1 P3 AIN7 P2 9 P1 TP1 J6 3X2 CON024 2 4 AVIN4 44 43 R103 0.00 805 P5 C66 0.1UF 805 P0 46 45 AIN3 LLC2 AIN9 NC[LLCREF] 6 ELPF 58 J6 3X2 CON024 57 R106 0.00 805 1 AVIN5 C65 0.1UF 805 60 59 AIN10 AIN5 AIN11 3 R100 75 1206 R102 75 1206 HS 62 61 CT3 10UF B C58 0.1UF 805 CT1 10UF B FIELD NC[VREF] NC[HREF] TP3 R101 75 1206 C2 0.1UF 805 AGND2 52 49 AGND2 CT4 10UF B C59 0.1UF 805 C68 0.001UF 805 AIN12 REFOUT CML CAPY1 CAPY2 54 NC[CLKIN] SFL[HFF] NC[AEF] NC[RD] OE CAPC1 NC[GPO3] CAPC2 NC[GPO2] 3 NC[GPO1] NC[GPO0] C4 0.1UF 805 CT2 10UF B C57 0.1UF 805 C67 0.001UF 805 50 AVDD DVDD1 DVDD2 DVDD3 AGND2 A3V A5V AGND2 38 C54 0.1UF 805 C1 0.1UF 805 PVDD DVDDIO1 DVDDIO2 39 DNP FER13 600 1206 40 47 53 AGND2 5 PPI0_D3 6 PPI0_D2 7 PPI0_D1 8 PPI0_D0 19 R39 33 805 20 AGND2 56 FER14 600 1206 63 21 4 22 SN74LVC1G32 SOT23-5 23 24 PVDD_ADV7183 32 33 27 C5 0.01UF 805 26 25 R1 1.5K 805 37 2 VDEC_HS 1 VDEC_VS 80 VDEC_FIELD 69 VDEC_VREF 70 VDEC_HREF 16 11 C55 0.1UF 805 VENC_HS 11 R24 10K 805 13 78 10 9 VENC_VS 77 8 79 7 1 2 3 4 5 PF3 6 PF2 PPI1_SYNC1 PPI0_SYNC1 PPI0_SYNC2 PPI1_SYNC2 PF[15:0] 17 18 34 DVDD_ADV7183 1.8V 35 FER15 600 1206 30 10 DNP FER17 600 1206 72 4 3.3V 3 SW2: Video Sync Signals and Encoder Enable Select Defalut = OFF, OFF, OFF, OFF, OFF, ON Position Function 1-5 Connect video sync signals to DSP ON = PF2 Used to enable or disable 6 the encoder digital interface OFF = Encoder digital interface always disabled 15 AGND1 AGND2 DGND1 AGND3 DGND2 AGND4 DGND3 AGND5 DGND4 NC[AGND6] DGND5 3 9 14 31 71 C3 0.01UF 805 C73 0.1UF 805 ANALOG DEVICES C74 0.01UF 805 Drawn AGND2 JSZ Checked Engineering B SW2 12 ON 12 Approvals A 2 C64 82NF 805 A1.8V 4 VDEC_CLKOUT 2 ADV7183AKST LQFP80 PVDD_ADV7183 DNP FER1 600 1206 FER2 600 1206 R41 33 805 U10 1 SWT017 DIP6 55 C56 0.1UF 805 PPI0_D4 AIN6 NC[DV] 48 76 3.3V NC[AFF] 51 PPI0_D5 AIN4 VS VIDEO_AVIN5 75 PPI0_D[15:0] AIN8 LLC1 TP2 VIDEO_AVIN4 AIN2 PPI0_D6 1 AVIN5 74 2 AVIN4 PPI0_D7 3 66 AVIN1 73 4 28 XTAL 5 29 VDEC_27MHZ_CLK 6 AVIN1 AVIN4 AVIN5 U4 C Date Title ADSP-BF561 EZ-KIT LITE: 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD VIDEO ENCODER (VIDEO IN) 10/10/03 Size Board No. C Date Rev A0185-2003 1.3A Sheet 12-16-2003_11:24 D 10 of 18 A B C D 3.3V 3.3V 3.3V R248 10K 805 PF5 R242 100 805 3 1 R247 0.00 1206 U47 R98 10K 805 SW6 SWT013 SPST-MOMENTARY 4 74LVC14A SOIC14 R246 10K 805 U47 1 CT25 1UF A U47 2 13 74LVC14A SOIC14 1 12 74LVC14A SOIC14 5V 3.3V 3.3V 3.3V RESET LED2 RED-SMT LED001 POWER LED1 GREEN-SMT LED001 R249 10K 805 R119 680 1206 USB RESET LED3 RED-SMT LED001 R120 270 1206 3.3V PF6 R243 100 805 U47 11 R185 10K 805 R223 0.00 1206 R193 270 1206 10 SW7 SWT013 SPST-MOMENTARY 74LVC14A SOIC14 CT26 1UF A 2 4 R229 10K 805 RESET 2 1 MR 4 PFI SW1 SWT013 SPST-MOMENTARY USB_RESET 2 SN74AHC1G00 SOT23-5 U46 8 RESET 7 RESET RESET 5 PFO 3.3V ADM708SAR SOIC8 SOFT_RESET R250 10K 805 PF7 U28 1 USB_CONFIGURED R244 100 805 R224 0.00 1206 U47 9 SW8 SWT013 SPST-MOMENTARY 8 74LVC14A SOIC14 3.3V CT27 1UF A C158 0.1UF 805 U21 1 C1+ 3 C1- 3 C159 0.1UF 805 R184 0.00 805 PF[15:0] 11 TX T1IN PF5 SW4 R225 0.00 1206 U47 2 11 PF6 6 10 PF7 4 9 PF8 5 8 TFS0 6 6 RSCLK0 5 74LVC14A SOIC14 3 4 5 CT28 1UF A PF5 3 R245 100 805 SW9 SWT013 SPST-MOMENTARY ON 12 2 PF8 1 1 R251 10K 805 10 T2IN DNP 2 P2 FER19 600 603 14 T1OUT FER20 600 603 13 R191 0.00 805 7 C148 0.1UF 805 FER18 600 603 8 9 DNP 5 TSCLK0 SWT017 DIP6 SW4 PB Enable Switch Default = ON, ON, ON, ON, OFF, OFF Position Function Connects the push buttons to the Programmable Flags of the DSP 1-4 Useful if using the PFs for another purpose. OFF, OFF = AD1836A -> TDM Mode 5,6 ON, ON = AD1836A -> I2S Mode DB9M 9PIN ANALOG DEVICES Approvals Drawn JSZ Checked Engineering A UART 3 4 NOTE: Remove R192 when populating R191 and R184 4 6 2 7 PF6 RFS0 1 7 T2OUT R1OUT R1IN 9 8 R2OUT R2IN ADM3202ARN SOIC16 R192 0.00 805 3 FER21 600 603 6 V- 12 RX 2 IDC2X1 2X1 V+ 4 C2+ 5 C2- 3.3V P1 1 C147 0.1UF 805 B C Date Title ADSP-BF561 EZ-KIT LITE: 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD RESET, PUSH-BUTTON SWITCHES, UART 10/10/03 Size Board No. C Date Rev A0185-2003 1.3A Sheet 12-16-2003_11:24 D 11 of 18 A B C D EXPANSION INTERFACE (TYPE B) 5V 3.3V D[31:0] A[25:2] J1 2 1 4 3 5V 1 A3 6 5 8 7 10 9 A4 A7 12 11 A6 A9 14 13 A8 16 15 MOSI MISO A10 A13 18 17 A12 A15 20 19 A14 A17 22 21 A16 PF5 A19 A21 24 23 26 25 28 27 A22 30 29 A24 PPI0_SYNC2 PF0 2 32 31 DT1SEC 34 33 DT1PRI 35 TFS1 38 37 TSCLK1 40 39 D0 DT0SEC D3 42 41 D2 DT0PRI D5 44 43 D4 TFS0 D7 46 45 D6 TSCLK0 D9 48 47 D8 D11 50 49 D10 D13 52 51 D12 D15 54 53 D14 D17 56 55 D16 D19 58 57 D18 62 61 D22 D25 64 63 D24 ABE3 D26 ABE2 PPI0_D[15:0] D29 68 67 D28 ABE1 D31 70 69 D30 ABE0 PPI0_D0 72 71 PPI0_D2 74 73 PF14 PF[15:0] 3 65 76 75 14 13 16 15 18 17 20 19 SCK 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39 NMI0 7 PPI1_D2 10 9 PPI1_D3 PPI1_D4 12 11 PPI1_D5 PPI1_D7 PPI1_D8 16 15 PPI1_D9 PPI0_SYNC1 PPI1_D10 18 17 PPI1_D11 DR1SEC PPI1_D12 20 19 PPI1_D13 DR1PRI PPI1_D14 22 21 PPI1_D15 RFS1 24 23 RSCLK1 26 25 28 27 DR0PRI 30 29 RFS0 32 31 34 33 36 35 38 37 40 39 42 41 44 43 46 45 48 47 RESET VDEC_HS RSCLK0 DSP_VDD_EXT PPI0_D8 PPI1_SYNC2 PPI0_D10 54 53 PPI0_D14 PF2 56 55 PF3 AWE PPI0_D3 SMS2 SMS0 78 77 PF15 80 79 PF13 PF8 82 81 PF11 PF6 84 83 PF9 85 SRAS PF7 88 87 SA10 90 89 SWE 45X2 CON019 57 60 59 62 61 64 63 66 65 68 67 70 69 72 71 74 73 76 75 78 77 80 79 82 81 84 83 86 85 88 87 90 89 EXP_PPI1_CLK CLK_OUT_EXP1 EXT_DSP_CLK 2 VDEC_VS VDEC_VREF DSP_3V_VOUT PPI1_SYNC3 PPI1_SYNC1 PPI0_D12 PPI0_D15 58 RX 13 VDEC_HREF 51 5 8 14 PPI0_D6 52 6 PPI1_D6 PPI0_D4 49 3 PPI1_D1 PPI0_SYNC3 45 50 4 DR0SEC 41 47 1 TX 43 48 1 J3 2 PPI1_D0 46 EXP_PPI0_CLK PPI0_D1 PF10 86 11 44 AOE PF12 PF4 9 12 D20 D23 66 10 PPI0_D7 PF0 D27 7 PPI0_D5 PPI0_D13 59 8 3.3V PPI1_D[15:0] VDEC_FIELD PPI0_D11 60 5 42 PPI0_D9 D21 3 6 A20 A25 D1 4 A18 A23 36 1 A2 A5 A11 J2 2 PF1 50 49 AMS3 52 51 AMS2 54 53 AMS1 56 55 AMS0 58 57 ARDY 60 59 ARE 62 61 SMS3 64 63 SMS1 66 65 68 67 70 69 72 71 SCKE 74 73 SCAS 76 75 CLK_OUT_EXP2 78 77 80 79 82 81 84 83 86 85 88 87 90 89 45X2 CON019 EXT_27MHZ_CLK 3 BR BG BGH 45X2 CON019 SPORT0 DT0PRI R72 0.00 1206 DT0SEC TFS0 TSCLK0 4 P3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CON014 10X2 RSCLK0 ANALOG DEVICES RFS0 R80 0.00 1206 DR0SEC DR0PRI Approvals Drawn JSZ Checked Engineering A B C Date Title ADSP-BF561 EZ-KIT LITE: 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD EXTENDER CARD CONNECTORS 10/10/03 Size Board No. C Date Rev A0185-2003 1.3A Sheet 5-12-2004_16:35 D 12 of 18 A B C 5V F1 2.5A FUS001 FER5 CHOKE_COIL 1 4 3 1 2 D3 2A DO-214AA UNREG_IN 3 INPUT 2 UNREG_IN A3V 4 OUTPUT2 GND 1 1 2 FER6 600 1206 OUTPUT1 J7 D2 2A DO-214AA C160 1000PF 1206 A5V R163 0.00 1206 VR1 D R157 100K 1206 CT23 10UF C C122 0.1UF 805 ADP3339AKC-5 SOT-223 1 3V_B VR3 CT24 10UF C C29 0.1UF 805 3 3 7.5V_POWER CON005 2.5MM_JACK R73 0.00 1206 2 OUTPUT1 4 OUTPUT2 INPUT GND 1 FER16 600 1206 ADP3338AKC-33 SOT-223 C32 1UF 805 CT17 10UF C C35 0.1UF 805 C153 1000PF 1206 3.3V NOTE: R252 or R253 gets populated R83 0.00 805 Default is R252 IN and R253 OUT DSP_VDD_EXT R252 0.00 805 SHGND DSP_VCORE DSP_VDD_INT TP7 DSP_VDD_EXT UNREG_IN DSP_3V_VOUT VR6 3 INPUT OUTPUT1 OUTPUT2 GND 1 2 CT20 10UF C R253 0.00 805 2 R84 0.00 805 U29 4 DNP ADP3339AKC-33 SOT-223 C53 0.1UF 805 CT21 10UF C R195 3.32K 805 VROUT L11 10UH IND001 1 5 2 6 3 7 4 8 D7 2A DO-214AA 3 1 NDS8434A SO-8 R82 0.00 805 CT22 68UF D D5 ZHCS1000 SOT23D 1A 2 DSP_VDD_INT C48 0.1UF 805 3.3V UNREG_IN D4 CMDSH-3 100MA SOD-323 VR4 R78 10K 805 VR5 2 VIN R79 0.00 805 5 SHDN 8 SYNC 4 GND C43 2.2UF 805 L10 1.5UH IND003 SW IN2 R74 0.00 805 6 7 C46 2200PF 1206 D6 SL22 2A DO-214AA C169 4.7UF 805 1V2 2 OUT2 R75 53.6K 805 6 SD 5 FB GND 4 ADP3336ARM MSOP8 R77 0.00 805 C45 1UF 805 1 OUT1 2 OUT2 3 OUT3 5 FB GND 4 ADP3336ARM MSOP8 6 SD C44 1UF 805 CT18 10UF C R48 76.8K 1206 C21 1UF 805 R76 1M 805 A1.8V FER4 600 1206 VR2 7 IN1 8 IN2 R52 10K 805 DNP 3 R194 3.32K 805 R186 10.0K 1206 1 OUT1 OUT3 R180 17.4K 805 FB VC 8 3 LT1765 SO-8 3 C170 0.18UF 805 1 BOOST IN1 1.8V R81 0.00 805 3.3V 7 3.3V C24 1UF 805 R56 147K 1206 CT19 100UF C 3 FER3 600 1206 MH2 MH1 MH3 MH4 MH5 3.3V FPGA_1V8 TP8 TP5 TP11 TP10 TP6 TP4 TP9 R207 332K 805 SHGND FER8 600 1206 VR7 2 6 INPUT SD 3 ERR R90 0.00 1206 1 OUTPUT 5 FB C218 0.47UF 805 4 GND 4 ADP3331ART SOT23-6 C230 0.47UF 805 R211 340K 805 SHGND SHGND ANALOG DEVICES R210 698K 805 Approvals Drawn JSZ Checked Engineering A B C Date Title ADSP-BF561 EZ-KIT LITE: 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD POWER 10/10/03 Size Board No. C Date Rev A0185-2003 1.3A Sheet 5-12-2004_16:35 D 13 of 18 A B C D DSP_VDD_EXT DSP_VDD_INT 1 1 C137 0.01UF 805 C140 0.01UF 805 C49 0.01UF 805 C174 0.01UF 805 3.3V C30 0.1UF 805 C151 0.1UF 805 C179 0.1UF 805 3.3V C126 0.1UF 805 C135 0.1UF 805 27MHZ OSC U3 3.3V C136 0.01UF 805 5V C134 0.01UF 805 C168 0.01UF 805 C37 0.1UF 805 C31 10UF 1210 C50 10UF 1210 C47 10UF 1210 C173 0.01UF 805 C154 0.01UF 805 C145 0.1UF 805 C172 0.1UF 805 C178 0.1UF 805 C152 0.1UF 805 C157 0.01UF 805 C156 0.01UF 805 C183 0.1UF 805 C22 0.1UF 805 C138 0.01UF 805 C52 0.1UF 805 C164 0.1UF 805 C139 0.1UF 805 A5V A5V C107 0.22UF 805 A5V C162 0.22UF 805 A5V C143 0.22UF 805 A5V C129 0.22UF 805 C184 0.1UF 805 C185 0.01UF 805 C186 0.01UF 805 C201 0.01UF 805 C104 0.22UF 805 AGND AGND AGND AGND AGND AGND AD8606 U16 AD8606 U17 AD8606 U18 AD8606 U19 AD8606 U20 3V_B 3.3V 3.3V C200 0.01UF 805 C182 0.01UF 805 C20 0.1UF 805 C75 0.01UF 805 C85 0.1UF 805 C256 0.01UF 805 A5V C125 0.22UF 805 74LVC14A U10 C70 0.01UF 805 AGND AGND AD8606 U13 C83 0.1UF 805 AGND2 AGND2 AD8061 U24 3.3V 2 3.3V AD8061 U23 3.3V C106 0.22UF 805 AD8606 U12 A3V AGND2 3.3V C41 0.01UF 805 A5V AD8061 U22 3.3V C146 0.01UF 805 3.3V A3V C71 0.1UF 805 SN74AHC1G08 U21 C167 0.1UF 805 C180 0.01UF 805 A3V 3.3V C177 0.1UF 805 74LVC00AD U9 3.3V AD8606 U15 C171 0.1UF 805 3.3V SDRAM U8 C108 0.22UF 805 AGND C176 0.01UF 805 3.3V ADSP-DM203 U1 A5V C131 0.1UF 805 AD1836 U14 3 C51 0.1UF 805 M29W640D U5 A5V C19 0.1UF 805 C175 0.1UF 805 3.3V IDT2305 U4 2 C155 0.1UF 805 C69 0.01UF 805 3.3V C149 0.01UF 805 C150 0.01UF 805 ADG752 U25 3.3V ADG752 U26 3 3.3V DVDD_ADV7183 C101 0.01UF 805 C114 0.01UF 805 C91 0.1UF 805 C89 0.1UF 805 C102 0.1UF 805 C90 0.1UF 805 C109 0.1UF 805 C110 0.1UF 805 C113 0.01UF 805 ADV7179 U27 C112 0.01UF 805 C87 0.1UF 805 C111 0.1UF 805 C88 0.1UF 805 C249 0.01UF 805 ADM708SAR U29 ADV7183 U28 C141 0.01UF 805 ADM3202 U30 C181 0.01UF 805 IDT74FCT3244APY U31 C127 0.01UF 805 IDT74FCT3244APY U36 C165 0.01UF 805 C166 0.01UF 805 ADG752 U40 ADG752 U45 C27 0.1UF 805 IDT2305 U46 C28 0.01UF 805 C132 0.1UF 805 39MHZ OSC U54 3.3V C189 0.1UF 805 4 C191 0.1UF 805 C202 0.01UF 805 C203 0.01UF 805 C190 0.01UF 805 C187 0.01UF 805 ANALOG DEVICES C188 0.01UF 805 Approvals Drawn JSZ Checked SDRAM U53 Engineering A B C Date Title ADSP-BF561 EZ-KIT LITE: 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD DECOUPLING CAPS 10/10/03 Size Board No. C Date Rev A0185-2003 1.3A Sheet 5-12-2004_16:35 D 14 of 18 A B C D All USB interface circuitry is considered propreitary andh has been omitted from this schematic When designin your JTAG interface please refer to the Engineer to Engineer Note EE-68 which can be found at http://www.analog.com 1 1 3.3V U36 EMULATOR_TMS YA TMS 4 R87 0.00 805 I1A EMULATOR_TCK 5 I0B YB 7 TCK 6 USB_TCK I1B EMULATOR_TRST 11 I0C YC 9 TRST 10 USB_TRST R241 10K 805 I0A 3 USB_TMS R239 10K 805 2 I1C EMULATOR_TDI 14 I0D YD 12 TDI 13 USB_TDI I1D 1 S 15 E 3.3V ADG774A QSOP16 P4 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 2 R201 10K 805 U37 EMULATOR_EMU USB_EMU EMULATOR_TDO IDC7X2 7X2 USB_TDO 2 I0A YA 4 EMU 3 I1A 5 I0B YB 7 TDO 6 I1B 11 I0C YC 9 10 I1C 14 I0D YD 12 13 I1D DSP JTAG HEADER 1 S 15 E ADG774A QSOP16 3 3 3.3V 3.3V C196 0.1UF 402 12.288MHz 3.3V C195 0.1UF 402 ADG774A C209 0.1UF 402 ADG774A ANALOG DEVICES 4 Approvals Drawn JSZ Checked Engineering A B C Date Title ADSP-BF561 EZ-KIT LITE: 20 Cotton Road Nashua, NH 03063 4 PH: 1-800-ANALOGD DEBUG AGENT - JTAG 10/10/03 Size Board No. C Date Rev A0185-2003 1.3A Sheet 12-11-2003_13:22 D 15 of 18 I INDEX ADV7183A, video decoder, 2-7, 3-8, Symbols 3-10 ~AMS0, memory select pin, 2-3 ~OE signal, ADV7183A video decoder, ASYNC memory bank 0, 2-2 audio 3-10 applications, -xi ~SMS0, memory select pin, 2-3 codec, 2-6 connectors (J4, J5), 3-18 A interface, see SPORT0 AD1836A, audio codec, 2-6, 3-3, 3-12 see also AD1836A Add New Hardware Wizard, Windows 98, 1-8 B address bus (A25-A2), 3-3 background telemetry channel (BTC), ADSP-BF561 processor 2-8 audio interface, see SPORT0 bill of materials, A-1 core voltage, 3-2 External Bus Interface Unit (EBIU), boot mode switch (SW3), 3-11 3-3 C external memory, 2-2 IO voltage, 3-2 clock memory restrictions, 2-2 frequency, 2-4 parallel peripheral interfaces (PPIs), PPI interfaces, 3-13 3-6 select switch (SW5), 3-13 peripheral ports, -xii source setup, 3-13 SDRAM memory map, 2-3 codecs, see AD1836A, ADV7179, see also input clock ADV7183A ADV7179, video encoder, 2-7, 3-7, connecting, EZ-KIT Lite board, 1-5 3-10 connectors, 1-5, 3-17 J1 (expansion interface), 3-9 ADSP-BF561 EZ-KIT Lite Evaluation System Manual I-1 INDEX J2 (expansion interface), 3-9 J3 (expansion interface), 3-9 J4 (audio), 3-18 J5 (audio), 3-18 J6 (video), 3-18 J7 (power), 3-18 J8 (USB), 1-6, 3-19 P4 (JTAG), 3-9, 3-20 P9 (SPORT0), 3-20 RS232 (P2), 3-20 see also expansion interface contents, EZ-KIT Lite package, 1-1 control bus, 3-3 conventions, manual, -xix customer support, -xiv cycle counters, 2-11 D D15-8 pins PPI0, 2-5 PPI1, 2-5 data bus, 3-3, 3-6 Device Manager window, 1-15 DIP switches, 3-10 see also SW E EBIU_SDBCTL register, 2-4, 2-5 EBIU_SDGCTL register, 2-4 EBIU_SDRRC register, 2-4, 2-5 electrostatic discharge, 1-2 example programs, 2-8 expansion connectors (J3-1), 3-3 I-2 interface, 3-3, 3-8, 3-17 External Bus Interface Unit (EBIU), 3-3 external memory, 2-2, 3-9 EZ-KIT Lite board architecture, 3-2 features, -x F features, EZ-KIT Lite board, -x Field pin, 3-4 FIO0_FLAG_D register, 2-5 flag pins, see programmable flags (PFs) flash memory, -xi, 3-3 ports PB39-P32, 3-16 ports PB47-P40, 3-16 Found New Hardware Wizard Windows XP, 1-14 G general purpose IO, 2-5 graphical user interface (GUI), 2-9 H Help, online, -xvii HSYNC signal, 3-6, 3-7 I input clock, 3-2, 3-6, 3-7 installation, summary, 1-3 installing EZ-KIT Lite USB driver, 1-7 VisualDSP++ and EZ-KIT Lite ADSP-BF561 EZ-KIT Lite Evaluation System Manual INDEX license, 1-5 VisualDSP++ and EZ-KIT Lite software, 1-4 IO voltage, 3-2 J JTAG connector (P4), 3-20 emulation port, 3-9 jumper settings, 1-5, 3-10 L LEDs, 1-5, 2-5, 3-14 J7, 1-6, 3-15 LED12-5, 3-5, 3-16 LED2, 1-6, 3-15 LED20-13, 3-5, 3-16 LED3, 1-6, 3-15 LED4, 1-15, 1-16, 3-16 license restrictions, 2-2 M memory external memory map, 2-2 select pins, see ~AMS0, ~SMS0 writes, 2-11 O opcode scan method, 2-11 P P3, SPORT connector, 3-3 package contents, 1-1 Parallel Peripheral Interfaces (PPIs), -xi, 2-7, 2-8, 3-6 clock select switch (SW5), 3-13 see also PPI0 and PPI1 PC configuration, 1-3 PFs, see programmable flags power connector (J7), 3-18 specifications, 3-19 supply, 3-19 PPI0, 2-5, 2-7, 3-6, 3-8, 3-16 Clock, primary processor pin, 3-7 primary processor pins 7-0, 3-6 SYNC1, primary processor pin, 3-6 SYNC2, primary processor pin, 3-7 PPI1, 2-5, 3-6 Clock, primary processor pin, 3-7 primary processor pins 7-0, 3-6 SYNC1 signal, 3-7, 3-11 SYNC2 signal, 3-7, 3-11 video output, 3-7 primary processor pins (PPIs) PPI0 Clock, 3-7 PPI0 SYNC1, 3-6 PPI0 SYNC2, 3-7 PPI1 Clock, 3-7 PPI1 SYNC1, 3-7 PPI1 SYNC2, 3-7 PPIs bits 7-0, 3-6 processor SDRAM map, see ADSP-BF561 processor programmable flags (PFs), 3-4, 3-16 PF0, 2-7, 3-4 PF1, 2-8, 3-4 ADSP-BF561 EZ-KIT Lite Evaluation System Manual I-3 INDEX PF12-PF9, 3-4 PF13, 2-7, 3-5 PF14, 2-7, 3-5 PF15, 2-6, 3-5 PF16, 3-5 PF17, 3-5 PF18, 3-5 PF19, 3-5 PF2, 2-7, 3-4, 3-10 PF20, 3-5 PF21, 3-5 PF22, 3-5 PF23, 3-5 PF24, 3-5 PF25, 3-5 PF26, 3-5 PF27, 3-5 PF28, 3-5 PF29, 3-5 PF3, 3-4 PF30, 3-5 PF31, 3-5 PF39-32, 3-5 PF4, 2-6, 3-3, 3-4 PF47-40, 3-5 PF5, 2-5, 3-4, 3-12, 3-15 PF6, 2-5, 3-4, 3-12, 3-15 PF7, 2-5, 3-4, 3-12, 3-15 PF8, 2-5, 3-4, 3-12, 3-15 see also push buttons push buttons, 2-5, 3-14 connecting to PF pins, 3-15 see also SW I-4 R registering, this product, 1-2, 1-5 reset cycle counters, 2-11 options, 2-9 processor, 3-15 push button (SW1), 3-14 registers, 2-11 RFS0, signal, 3-12 RSCLK0 register, 2-6 signals, 3-12 S SDRAM, -xi, 2-2, 2-3 default settings, 2-4 optimum settings, 2-4 SDRAM memory, 2-3 core MMRs, 2-3 data bank A SRAM, 2-3 data bank B SRAM, 2-3 instruction SRAM, 2-3 instruction SRAM/CACHE, 2-3 reserved, 2-3 scratch pad SRAM, 2-3 system MMRs, 2-3 serial clock (SCL), 2-7 data (SDAT), 2-8 Serial Peripheral Interconnect (SPI), 3-3 setting EZ-KIT Lite hardware, 1-5 target options, 2-9 SPI ADSP-BF561 EZ-KIT Lite Evaluation System Manual INDEX interface, 3-4 SPORT0, -xi, 2-6, 3-3, 3-12, 3-20 starting VisualDSP++, 1-16 SW1, reset push button, 3-14 SW10, test DIP switch, 3-13 SW11, test DIP switch, 3-13 SW2, video config switch, 2-7, 3-6, 3-7, 3-8, 3-10 SW3, boot mode switch, 3-10, 3-11 SW4, enable push button, 2-6, 3-12, 3-15 SW5, clock select switch, 3-6, 3-13 SW6, general input push button, 3-4, 3-12, 3-15 SW7, general input push button, 3-4, 3-12, 3-15 SW8, general input push button, 3-4, 3-12, 3-15 SW9, general input push button, 3-4, 3-12, 3-15 SYNC1 signal, 3-6 SYNC2 signal, 3-6 synchronization signals, 3-6 system architecture, EZ-KIT Lite board, 3-2 requirements, PC, 1-3 T target options miscellaneous, 2-11 on emulator exit, 2-10 reset, 2-9 XML file, 2-10 Target Options dialog box, 2-9 test DIP switches (SW10, SW11), 3-13 TFS0, signal, 3-12 Timer 0, 3-4 Timer 1, 3-4 Timer 10, 3-7 Timer 11, 3-7 Timer 2, 3-4 Timer 3, 3-4 Timer 4, 3-4 Timer 5, 3-4 Timer 6, 3-4 Timer 8, 3-6 Timer 9, 3-7 TSCLK0 register, 2-6 signal, 3-12 U UART, -xi, -xii, 3-5, 3-8 USB cable, 1-2 connector (P7), 3-19, 3-20 driver installation, Windows 2000, 1-12 driver installation, Windows 98, 1-8 driver installation, Windows XP, 1-13 interface, 3-9 interface chip (U34), 3-14, 3-15 monitor LED (LED4), 1-15, 3-16 user LEDs LED12-5, 3-16 LED20-13, 3-16 see also LEDs ADSP-BF561 EZ-KIT Lite Evaluation System Manual I-5 INDEX V verifying USB driver installation, 1-15 video, 2-7 blanking control, 3-7 configuration switch (SW2), 3-10 connecting to PPI, -xi connector (J6), 3-18 encoder/decoder, -xi input mode, 3-8 interface, 2-7 output mode, 3-7 VisualDSP++ documentation, -xviii I-6 installation, 1-4 license, 1-5 online Help, -xvii requirements, 1-3 session, 2-3 starting, 1-16 VSYNC signal, 3-7 X XML file version, 2-10 parser version, 2-10 register reset values, 2-11 ADSP-BF561 EZ-KIT Lite Evaluation System Manual