CrossLink Family Data Sheet

CrossLink Family
Preliminary Data Sheet
DS1055 Version 1.0
May 2016
CrossLink Family
Preliminary Data Sheet
Contents
Acronyms in This Document ................................................................................................................................................. 5
1. General Description ...................................................................................................................................................... 6
1.1.
Features ............................................................................................................................................................... 6
2. Application Examples .................................................................................................................................................... 7
2.1.
2:1 MIPI CSI-2 Image Sensor Aggregator Bridge ................................................................................................. 7
2.2.
1:2 MIPI DSI Display Interface Bridge .................................................................................................................. 8
2.3.
FPD-Link/OpenLDI LVDS to MIPI DSI Display Interface Bridge ............................................................................ 9
2.4.
MIPI DSI to FPD-Link/OpenLDI LVDS Display Interface Bridge .......................................................................... 10
2.5.
CMOS to MIPI DSI Display Interface Bridge ....................................................................................................... 11
2.6.
CMOS to MIPI CSI-2 Image Sensor Interface Bridge .......................................................................................... 12
2.7.
MIPI DSI to CMOS Display Interface Bridge ....................................................................................................... 13
2.8.
MIPI CSI-2 to CMOS Image Sensor Interface Bridge .......................................................................................... 14
2.9.
SubLVDS to MIPI CSI-2 Image Sensor Interface Bridge ..................................................................................... 15
3. Product Feature Summary .......................................................................................................................................... 16
4. Architecture Overview ................................................................................................................................................ 17
4.1.
MIPI D-PHY Blocks ............................................................................................................................................. 18
4.2.
Programmable I/O Banks .................................................................................................................................. 18
4.3.
Programmable FPGA Fabric .............................................................................................................................. 18
4.3.1. FPGA Fabric Overview ...................................................................................................................................18
4.3.2. Clocking Overview .........................................................................................................................................19
4.3.3. Embedded Block RAM Overview ..................................................................................................................20
4.4.
System Resources .............................................................................................................................................. 20
4.4.1. CMOS GPIO (Bank 0) .....................................................................................................................................20
4.4.2. Power Management Unit..............................................................................................................................20
4.4.3. Device Configuration.....................................................................................................................................22
2
4.4.4. User I C IP......................................................................................................................................................22
5. DC and Switching Characteristics................................................................................................................................ 23
5.1.
Absolute Maximum Ratings .............................................................................................................................. 23
5.2.
Recommended Operating Conditions ............................................................................................................... 23
5.3.
Preliminary Power Supply Ramp Rates ............................................................................................................. 24
5.4.
Preliminary Power-On-Reset Voltage Levels ..................................................................................................... 24
5.5.
ESD Performance ............................................................................................................................................... 24
5.6.
Preliminary DC Electrical Characteristics ........................................................................................................... 24
5.7.
Preliminary CrossLink Supply Current (Standby) ............................................................................................... 25
5.8.
Preliminary MIPI D-PHY Supply Current ............................................................................................................ 25
5.9.
Preliminary Power Management Unit (PMU) Timing ....................................................................................... 25
5.10. sysI/O Recommended Operating Conditions .................................................................................................... 26
5.11. Preliminary sysI/O Single-Ended DC Electrical Characteristics .......................................................................... 26
5.12. Preliminary sysI/O Differential Electrical Characteristics .................................................................................. 27
5.12.1.
Preliminary LVDS/subLVDS/SLVS ..............................................................................................................27
5.12.2.
Preliminary MIPI D-PHY ............................................................................................................................28
5.13. Preliminary CrossLink Maximum I/O Buffer Speed ........................................................................................... 29
5.14. Preliminary CrossLink External Switching Characteristics ................................................................................. 30
5.15. Preliminary sysCLOCK PLL Timing ...................................................................................................................... 34
5.16. MIPI D-PHY Performance .................................................................................................................................. 35
5.17. Preliminary Internal Oscillators (HFOSC, LFOSC) ............................................................................................... 35
2 1
5.18. Preliminary User I C ......................................................................................................................................... 35
5.19. CrossLink sysCONFIG Port Timing Specifications .............................................................................................. 36
5.20. Preliminary SRAM Configuration Time from NVCM .......................................................................................... 36
5.21. Switching Test Conditions ................................................................................................................................. 37
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
6.
Pinout Information ..................................................................................................................................................... 38
6.1.
WLCSP36 Pinout ................................................................................................................................................ 38
6.2.
ucfBGA64 Pinout ............................................................................................................................................... 39
6.3.
ctfBGA80 Pinout ................................................................................................................................................ 41
6.4.
csfBGA81 Pinout ................................................................................................................................................ 43
6.5.
Dual Function Pin Descriptions ......................................................................................................................... 45
6.6.
Dedicated Function Pin Descriptions ................................................................................................................ 45
6.7.
Pin Information Summary ................................................................................................................................. 46
7. Package Information ................................................................................................................................................... 47
7.1.
36-Ball WLCS Package ....................................................................................................................................... 47
7.2.
64-Ball ucfBGA Package .................................................................................................................................... 48
7.3.
80-Ball ctfBGA Package ..................................................................................................................................... 49
7.4.
81-Ball csfBGA Package ..................................................................................................................................... 50
8. CrossLink Part Number Description ............................................................................................................................ 51
8.1.
Ordering Part Numbers ..................................................................................................................................... 51
8.1.1. Industrial ....................................................................................................................................................... 51
References .......................................................................................................................................................................... 52
Technical Support ............................................................................................................................................................... 52
Revision History .................................................................................................................................................................. 52
Figures
Figure 2.1. 2:1 MIPI CSI-2 Image Sensor Aggregator Bridge ................................................................................................. 7
Figure 2.2. 1:2 MIPI DSI Display Interface Bridge ................................................................................................................. 8
Figure 2.3. FPD-Link/OpenLDI LVDS to MIPI DSI Display Interface Bridge............................................................................ 9
Figure 2.4. MIPI DSI to FPD-Link/OpenLDI LVDS Display Interface Bridge.......................................................................... 10
Figure 2.5. CMOS to MIPI DSI Display Interface Bridge ...................................................................................................... 11
Figure 2.6. CMOS to MIPI CSI-2 Image Sensor Interface Bridge ......................................................................................... 12
Figure 2.7. MIPI DSI to CMOS Display Interface Bridge ...................................................................................................... 13
Figure 2.8. MIPI CSI-2 to CMOS Image Sensor Interface Bridge ......................................................................................... 14
Figure 2.9. SubLVDS to MIPI CSI-2 Image Sensor Interface Bridge ..................................................................................... 15
Figure 4.1. CrossLink Device Block Diagram ....................................................................................................................... 17
Figure 4.2. CrossLink Device Simplified Block Diagram (Top Level) .................................................................................... 19
Figure 4.3. CrossLink MIPI D-PHY Block .............................................................................................................................. 21
Figure 4.4. CrossLink PMU State Machine .......................................................................................................................... 21
Figure 5.1. Receiver RX.CLK.Centered Waveforms ............................................................................................................. 31
Figure 5.2. Receiver RX.CLK.Aligned Input Waveforms ...................................................................................................... 32
Figure 5.3. Transmit TX.CLK.Centered Output Waveforms ................................................................................................ 32
Figure 5.4. Transmit TX.CLK.Aligned Waveforms ............................................................................................................... 32
Figure 5.5. DDRX71, DDRX141 Video Timing Waveforms .................................................................................................. 33
Figure 5.6. Output Test Load, LVTTL and LVCMOS Standards ............................................................................................ 37
Figure 7.1. 36-Ball WLCS Package Diagram ........................................................................................................................ 47
Figure 7.2. 64-Ball ucfBGA Package Diagram ...................................................................................................................... 48
Figure 7.3. 80-Ball ctfBGA Package Diagram ...................................................................................................................... 49
Figure 7.4. 81-Ball csfBGA Package Diagram ...................................................................................................................... 50
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
3
CrossLink Family
Preliminary Data Sheet
Tables
Table 2.1. 2:1 MIPI CSI-2 Image Sensor Aggregator Bridge Overview ..................................................................................7
Table 2.2. 1:2 MIPI DSI Display Interface Bridge Overview ..................................................................................................8
Table 2.3. FPD-Link/OpenLDI LVDS to MIPI Display Interface Bridge Overview ...................................................................9
Table 2.4. MIPI DSI to FPD-Link/OpenLDI LVDS Display Interface Bridge Overview ...........................................................10
Table 2.5. CMOS to MIPI DSI Display Interface Bridge Overview .......................................................................................11
Table 2.6. CMOS to MIPI CSI-2 Image Sensor Interface Bridge Overview ..........................................................................12
Table 2.7. MIPI DSI to CMOS Display Interface Bridge Overview .......................................................................................13
Table 2.8. MIPI CSI-2 to CMOS Image Sensor Interface Bridge Overview ..........................................................................14
Table 2.9. SubLVDS to MIPI CSI-2 Image Sensor Interface Bridge Overview ......................................................................15
Table 3.1. CrossLink Feature Summary ...............................................................................................................................16
Table 5.1. Absolute Maximum Ratings ...............................................................................................................................23
Table 5.2. Recommended Operating Conditions ................................................................................................................23
Table 5.3. Preliminary Power Supply Ramp Rates ..............................................................................................................24
Table 5.4. Preliminary Power-On-Reset Voltage Levels ......................................................................................................24
Table 5.5. Preliminary DC Electrical Characteristics ...........................................................................................................24
Table 5.6. Preliminary CrossLink Supply Current (Standby)................................................................................................25
1
Table 5.7. Preliminary MIPI D-PHY Supply Current ...........................................................................................................25
Table 5.8. Preliminary PMU Timing ....................................................................................................................................25
Table 5.9. sysI/O Recommended Operating Conditions .....................................................................................................26
Table 5.10. Preliminary sysI/O Single-Ended DC Electrical Characteristics .........................................................................26
1
1
Table 5.11. LVDS/subLVDS /SLVS ......................................................................................................................................27
Table 5.12. Preliminary MIPI D-PHY ....................................................................................................................................28
Table 5.13. Preliminary CrossLink Maximum I/O Buffer Speed ..........................................................................................29
Table 5.14. Preliminary CrossLink External Switching Characteristics ................................................................................30
Table 5.15. Preliminary sysCLOCK PLL Timing.....................................................................................................................34
Table 5.16. 1500 Mb/s MIPI_DPHY_X8_RX/TX Timing Table (1500 Mb/s > MIPI D-PHY Data Rate > 1200 Mb/s) ............35
Table 5.17. 1200 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1200 Mb/s > MIPI D-PHY Data Rate > 1000 Mb/s) ............35
Table 5.18. 1000 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1000 Mb/s > MIPI D-PHY Data Rate > 10 Mb/s) ................35
Table 5.19. Preliminary Internal Oscillators ........................................................................................................................35
2 1
Table 5.20. Preliminary User I C ........................................................................................................................................35
Table 5.21. CrossLink sysCONFIG Port Timing Specifications .............................................................................................36
Table 5.22. Preliminary SRAM Configuration Time from NVCM .........................................................................................36
Table 5.23. Test Fixture Required Components, Non-Terminated Interfaces ....................................................................37
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
Acronyms in This Document
A list of acronyms used in this document.
Acronym
BGA
CMOS
CSI
DSI
EBR
ECLK
FPD
2
IC
LUT
LVCMOS
LVDS
MIPI
NVCM
OTP
PCLK
PFU
PLL
PMU
SLVS
SPI
WLCSP
Definition
Ball Grid Array
Complementary Metal Oxide Semiconductor
Camera Serial Interface
Display Serial Interface
Embedded Block RAM
Edge Clock
Flat Panel Display
Inter-Integrated Circuit
Look Up Table
Low-Voltage Complementary Metal Oxide Semiconductor
Low-Voltage Differential Signaling
Mobile Industry Processor Interface
Non-Volatile Configuration Memory
One Time Programmable
Primary Clock
Programmable Functional Unit
Phase Locked Loops
Power Management Unit
Scalable Low-Voltage Signaling
Serial Peripheral Interface
Wafer Level Chip Scale Packaging
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
5
CrossLink Family
Preliminary Data Sheet
1. General Description

TM
CrossLink from Lattice Semiconductor is a
programmable video bridging device that supports a
variety of protocols and interfaces for mobile image
sensors and displays. The device is based on Lattice
mobile FPGA technology. It combines the extreme
flexibility of an FPGA with the low power, low cost and
small footprint of an ASIC.
CrossLink supports video interfaces including MIPI®
DPI, MIPI DBI, CMOS camera and display interfaces,
OpenLDI, FPD-Link, FLATLINK, MIPI D-PHY, MIPI CSI-2,
MIPI DSI, SLVS200, SubLVDS, HiSPi and more.
Lattice Semiconductor provides many pre-engineered
IP (Intellectual Property) modules for CrossLink. By
using these configurable soft core IPs as standardized
blocks, designers are free to concentrate on the unique
aspects of their design, increasing their productivity.
The Lattice Diamond® design software allows large
complex designs to be efficiently implemented using
CrossLink. Synthesis library support for CrossLink
devices is available for popular logic synthesis tools.
The Diamond tools use the synthesis tool output along
with the constraints from its floor planning tools to
place and route the design in the CrossLink device. The
tools extract the timing from the routing and
back-annotate it into the design for timing verification.
Interfaces on CrossLink provide a variety of bridging
solutions for smart phone, tablets, wearables, VR, AR,
Drone, Smart Home, HMI as well as adjacent ISM
markets. The device is capable of supporting
high-resolution, high-bandwidth content for mobile
cameras and displays at 4k UHD and beyond.
1.1. Features


Ultra-low power
 Sleep Mode Support
 Normal Operation – From 5 mW to 150 mW
Ultra small footprint packages
2
 36-ball WLCSP (6 mm )
2
 64-ball ucfBGA (12 mm )
2
 80-ball ctfBGA (40 mm )
2
 81-ball csfBGA (20 mm )






Programmable architecture
 5936 LUTs
 180 kb block RAM
 47 kb distributed RAM
Two hardened 4-lane MIPI D-PHY interfaces
 Transmit and receive
 6 Gb/s per D-PHY
Programmable source synchronous I/O
 MIPI D-PHY Rx, LVDS Rx, LVDS Tx, SubLVDS Rx,
SLVS200 Rx, HiSPi Rx
 1200 Mb/s per I/O
 Four high-speed clock inputs
Programmable CMOS I/O
 LVTTL and LVCMOS
 3.3 V, 2.5 V, 1.8 V and 1.2 V
 LVDS, LVCMOS differential I/Os
Flexible device configuration
 One Time Programmable (OTP) non-volatile
configuration memory
 Master SPI boot from external flash
 Dual image booting supported
2
 I C programming
 SPI programming
 TransFR™ I/O for simple field updates
Enhanced system level support
 Reveal logic analyzer
 TraceID for system tracking
2
 On-chip hardened I C block
Applications examples
 2:1 MIPI CSI-2 Image Sensor Aggregator
Bridge
 1:2 MIPI DSI Display Interface Bridge
 MIPI DSI to/from FPD-Link/OpenLDI LVDS
Display Interface Bridge
 MIPI DSI to/from CMOS Display Interface
Bridge
 MIPI CSI-2 to/from CMOS Image Sensor
Interface Bridge
 SubLVDS to MIPI CSI-2 Image Sensor Interface
Bridge
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
2. Application Examples
2.1. 2:1 MIPI CSI-2 Image Sensor Aggregator Bridge
Figure 2.1 shows the block diagram for the 2:1 MIPI CSI-2 image sensor aggregator bridge. This solution merges image
outputs from multiple sensors into a single CSI-2 output to an application processor.
Table 2.1 provides additional details on the application example, including input and output descriptions and device
resource usage. The interface bridge is fully programmable, supporting any input encoding, variable number of lanes,
and data rates up to 1.2 Gb/s per lane input or 1.5 Gb/s per lane output. Up to 8 image sensor inputs can be
aggregated, depending on data rate and number of lanes. For details, refer to IPUG121, 2:1 MIPI CSI-2 Bridge Soft IP
User Guide.
Image Sensor
Application
Processor
CrossLink
MIPI CSI-2
MIPI CSI-2
Mux /
Merge
Image Sensor
MIPI CSI-2
Figure 2.1. 2:1 MIPI CSI-2 Image Sensor Aggregator Bridge
Table 2.1. 2:1 MIPI CSI-2 Image Sensor Aggregator Bridge Overview
Application Example Details
Input Type
Programmable Fabric Operation(s)
Output Type
2 x 1080p60, 12-bit RAW
2 x 4-Lane MIPI D-PHY @ ~445 Mb/s per lane
Merge Image Sensor Outputs with no Frame drop
Mux/Merge in flexible combinations
1 x 1080p60, 12-bit RAW
1 x 4-Lane MIPI D-PHY @ ~445 Mb/s per lane
2
Additional System Functions
Support for I C Bridge/Mux for Camera Configuration
GPIO for image sensor sync and reset/power control
Preliminary Example Device Resource Usage*
Typical Power Consumption
Device I/O Used
~55 mW
20 Programmable I/O; 1 x Hard D-PHY Quads
Fabric Resources Used
~85% of LUT4; ~100% of EBR
*Note: For reference only – exact usage and power consumption depends on specific application parameters. Additional system
functions are not included in resource usage. The typical power consumption estimate is based on nominal supply voltages at
TJ = 25 °C.
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
7
CrossLink Family
Preliminary Data Sheet
2.2. 1:2 MIPI DSI Display Interface Bridge
Figure 2.2 shows the block diagram for the 1:2 MIPI DSI display interface bridge. This solution duplicates the display
output from single application processor DSI output to two different DSI displays.
Table 2.2 provides additional details on the application example, including input and output descriptions and device
resource usage. The interface bridge is fully programmable, supporting any input encoding, variable number of lanes,
and data rates up to 1.2 Gb/s per lane input or 1.5 Gb/s per lane output. The solution can be customized to split the
input image, or perform additional bridging operations. For details, refer to IPUG120, MIPI DSI to DSI Display Interface
Bridge Soft IP User Guide.
Application
Processor
CrossLink
Display
MIPI D-PHY (4-Lane)
DSI
MIPI D-PHY (4-Lane)
DSI
Split /
Duplicate
Display
MIPI D-PHY (4-Lane)
DSI
Figure 2.2. 1:2 MIPI DSI Display Interface Bridge
Table 2.2. 1:2 MIPI DSI Display Interface Bridge Overview
Application Example Details
Input Type
Programmable Fabric Operation(s)
Output Type
Additional System Functions
1080p60, 24-bit RGB
4-Lane MIPI D-PHY @ ~900 Mb/s per lane
Split/Duplicate Image
2 x 1080p60, 24-bit RGB
2 x 4-Lane MIPI D-PHY @ ~900 Mb/s per lane
Display Configuration (DCS)
Power and Reset Sequencing of Display
Backlight PWM Control
Preliminary Example Device Resource Usage*
Typical Power Consumption
Device I/O Used
~140 mW
10 Programmable I/O; 2 x Hard D-PHY Quads
Fabric Resources Used
80% of LUT4; ~80% of EBR
*Note: For reference only – exact usage and power consumption depends on specific application parameters. Additional system
functions are not included in resource usage. The typical power consumption estimate is based on nominal supply voltages at
TJ = 25 °C.
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
2.3. FPD-Link/OpenLDI LVDS to MIPI DSI Display Interface Bridge
Figure 2.3 shows the block diagram for the FPD-Link/OpenLDI LVDS to MIPI DSI display interface bridge. This solution
bridges the single or dual-channel FPD-Link/OpenLDI LVDS display output from the application processor to a MIPI DSI
input display.
Table 2.3 provides additional details on the application example, including input and output descriptions and device
resource usage. The interface bridge is fully programmable, supporting both RGB666 and RGB888, variable number of
LVDS data lanes, and data rates up to 1.2 Gb/s per lane input or 1.5 Gb/s per lane output. For details, refer to IPUG124,
OpenLDI/FPD-Link/LVDS to MIPI DSI Interface Bridge Soft IP User Guide.
Application
Processor
CrossLink
FPD-Link
MIPI DSI
Display
Bridge
Figure 2.3. FPD-Link/OpenLDI LVDS to MIPI DSI Display Interface Bridge
Table 2.3. FPD-Link/OpenLDI LVDS to MIPI Display Interface Bridge Overview
Application Example Details
Input Type
Programmable Fabric Operation(s)
Output Type
Additional System Functions
1080p60, 24-bit RGB
2 Channels (2 x 4 Data Lanes and 2 x 1 Clock Lane) @ 74.25 MHz FPD-Link Clock
Bridge
1 x 1080p60, 24-bit RGB
1 x 4-Lane MIPI D-PHY @ ~900 Mb/s per lane
Display Configuration (DCS)
Power and Reset Sequencing of Display
Backlight PWM Control
Preliminary Example Device Resource Usage*
Typical Power Consumption
Device I/O Used
TBD mW
20 Programmable I/O; 1 x Hard D-PHY Quads
Fabric Resources Used
~50% of LUT4; ~60% of EBR
*Note: For reference only – exact usage and power consumption depends on specific application parameters. Additional system
functions are not included in resource usage. The typical power consumption estimate is based on nominal supply voltages at
TJ = 25 °C.
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
9
CrossLink Family
Preliminary Data Sheet
2.4. MIPI DSI to FPD-Link/OpenLDI LVDS Display Interface Bridge
Figure 2.4 shows the block diagram for the MIPI DSI to FPD-Link/OpenLDI LVDS Display Interface Bridge. This solution
bridges the MIPI DSI output from the application processor to a single or dual channel FPD-Link/OpenLDI LVDS display
input.
Table 2.4 provides additional details on the application example, including input and output descriptions and device
resource usage. The interface bridge is fully programmable, supporting both RGB666 and RGB888, variable number of
LVDS data lanes, and data rates up to 1.2 Gb/s per lane input or 1.5 Gb/s per lane output. For details, refer to IPUG122,
MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge Soft IP User Guide.
Application
Processor
CrossLink
MIPI DSI
Bridge
FPD-Link /
OpenLDI
Display
Figure 2.4. MIPI DSI to FPD-Link/OpenLDI LVDS Display Interface Bridge
Table 2.4. MIPI DSI to FPD-Link/OpenLDI LVDS Display Interface Bridge Overview
Application Example Details
Input Type
Programmable Fabric Operation(s)
Output Type
Additional System Functions
1080p60, 24-bit RGB
4-Lane MIPI D-PHY @ ~900 Mb/s per lane
Bridge
1080p60, 24-bit RGB
2 Channels (2 x 4 Data Lanes and 2 x 1 Clock Lane) @ 74.25MHz FPD-Link Clock
Display Configuration
Power and Reset Sequencing of Display
Backlight PWM Control
Preliminary Example Device Resource Usage*
Typical Power Consumption
Device I/O Used
TBD mW
20 Programmable I/O; 1 x Hard D-PHY Quads
Fabric Resources Used
~30% of LUT4; ~30% of EBR
*Note: For reference only – exact usage and power consumption depends on specific application parameters. Additional system
functions are not included in resource usage. The typical power consumption estimate is based on nominal supply voltages at
TJ = 25 °C.
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
2.5. CMOS to MIPI DSI Display Interface Bridge
Figure 2.5 shows the block diagram for the CMOS to MIPI DSI display interface bridge. This solution bridges the CMOS
parallel output from the application processor to a DSI display input.
Table 2.5 provides additional details on the application example, including input and output descriptions and device
resource usage. The interface bridge is fully programmable, supporting a wide range of video formats, and data rates
up to 150 MHz at the CMOS input side or 1.5 Gb/s per lane output. For details, refer to IPUG126, CMOS to MIPI D-PHY
Interface Bridge Soft IP User Guide.
Application
Processor
CrossLink
CMOS Parallel
MIPI DSI
Display
Bridge
Figure 2.5. CMOS to MIPI DSI Display Interface Bridge
Table 2.5. CMOS to MIPI DSI Display Interface Bridge Overview
Application Example Details
Input Type
Programmable Fabric Operation(s)
Output Type
Additional System Functions
1080p60, 24-bit RGB
CMOS Parallel @ 148.5 MHz
Interface Bridge
1080p60, 24-bit RGB
4-Lane MIPI D-PHY @ ~900 Mb/s per lane
Display Configuration (DCS)
Power and Reset Sequencing of Display
Backlight PWM Control
Preliminary Example Device Resource Usage*
Typical Power Consumption
Device I/O Used
~80 mW
28 Programmable I/O; 1 x Hard D-PHY Quads
Fabric Resources Used
~40% of LUT4; ~20% of EBR
*Note: For reference only – exact usage and power consumption depends on specific application parameters. Additional system
functions are not included in resource usage. The typical power consumption estimate is based on nominal supply voltages at
TJ = 25 °C.
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
11
CrossLink Family
Preliminary Data Sheet
2.6. CMOS to MIPI CSI-2 Image Sensor Interface Bridge
Figure 2.6 shows the block diagram for the CMOS to MIPI CSI-2 Image Sensor Interface Bridge. This solution bridges the
CMOS parallel output from an image sensor to a CSI-2 input of an application processor.
Table 2.6 provides additional details on the application example, including input and output descriptions and device
resource usage. The interface bridge is fully programmable, supporting a wide range of video formats, and data rates
up to 150 MHz at the CMOS input side or 1.5 Gb/s per lane output. For details, refer to IPUG126, CMOS to MIPI D-PHY
Interface Bridge Soft IP User Guide.
CrossLink
Image Sensor
CMOS Parallel
MIPI CSI-2
Application
Processor
Bridge
Figure 2.6. CMOS to MIPI CSI-2 Image Sensor Interface Bridge
Table 2.6. CMOS to MIPI CSI-2 Image Sensor Interface Bridge Overview
Application Example Details
Input Type
1080p60, 12-bit RAW
CMOS Parallel @ 74.25 MHz
Programmable Fabric Operation(s)
Interface Bridge
Output Type
1080p60, 12-bit RAW
4-Lane MIPI D-PHY @ ~450 Mb/s per lane
Additional System Functions
I C for Camera Configuration
GPIO for image sensor reset/power control
2
Preliminary Example Device Resource Usage*
Typical Power Consumption
Device I/O Used
Fabric Resources Used
~75 mW
16 Programmable I/O; 1 x Hard D-PHY Quads
~40% of LUT4; ~20% of EBR
*Note: For reference only – exact usage and power consumption depends on specific application parameters. Additional system
functions are not included in resource usage. The typical power consumption estimate is based on nominal supply voltages at
TJ = 25 °C.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
2.7. MIPI DSI to CMOS Display Interface Bridge
Figure 2.7 shows the block diagram for the MIPI DSI to CMOS display interface bridge. This solution bridges the MIPI
DSI output from the application processor to CMOS parallel display input.
Table 2.7 provides additional details on the application example, including input and output descriptions and device
resource usage. The interface bridge is fully programmable, supporting multiple pixel formats and data rates up to 1.5
Gb/s per lane input and up to 150 MHz CMOS parallel output. For details, refer to IPUG123, MIPI D-PHY to CMOS
Interface Bridge Soft IP User Guide.
Application
Processor
CrossLink
Display
MIPI DSI
CMOS Parallel
Bridge
Figure 2.7. MIPI DSI to CMOS Display Interface Bridge
Table 2.7. MIPI DSI to CMOS Display Interface Bridge Overview
Application Example Details
Input Type
Programmable Fabric Operation(s)
Output Type
Additional System Functions
1080p60, 24-bit RGB
4-Lane MIPI D-PHY @ ~900 Mb/s per lane
Interface Bridge
1080p60, 24-bit RGB
CMOS Parallel @ 148.5 MHz
Power and Reset Sequencing of Display
Backlight PWM Control
Preliminary Example Device Resource Usage*
Typical Power Consumption
Device I/O Used
~80 mW
28 Programmable I/O; 1 x Hard D-PHY Quads
Fabric Resources Used
15% of LUT4; ~15% of EBR
*Note: For reference only – exact usage and power consumption depends on specific application parameters. Additional system
functions are not included in resource usage. The typical power consumption estimate is based on nominal supply voltages at
TJ = 25 °C.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
13
CrossLink Family
Preliminary Data Sheet
2.8. MIPI CSI-2 to CMOS Image Sensor Interface Bridge
Figure 2.8 shows the block diagram for the MIPI DSI to CMOS display interface bridge. This solution bridges the MIPI
DSI output from the application processor to CMOS parallel display input.
Table 2.8 provides additional details on the application example, including input and output descriptions and device
resource usage. The interface bridge is fully programmable, supporting multiple pixel formats and data rates up to 1.5
Gb/s per lane input and up to 150 MHz CMOS parallel output. For details, refer to IPUG123, MIPI D-PHY to CMOS
Interface Bridge Soft IP User Guide.
CrossLink
Image Sensor
MIPI CSI-2
CMOS Parallel
Application
Processor
Bridge
Figure 2.8. MIPI CSI-2 to CMOS Image Sensor Interface Bridge
Table 2.8. MIPI CSI-2 to CMOS Image Sensor Interface Bridge Overview
Application Example Details
Input Type
1080p60, RAW12
4-Lane MIPI D-PHY @ ~445 Mb/s per lane
Programmable Fabric Operation(s)
Output Type
Interface Bridge
1080p60, RAW12
CMOS Parallel @ 74.25 MHz
2
Additional System Functions
I C for Camera Configuration
GPIO for image sensor reset/power control
Preliminary Example Device Resource Usage*
Typical Power Consumption
Device I/O Used
60 mW
16 Programmable I/O; 1 x Hard D-PHY Quads
Fabric Resources Used
15% of LUT4; ~15% of EBR
*Note: For reference only – exact usage and power consumption depends on specific application parameters. Additional system
functions are not included in resource usage. The typical power consumption estimate is based on nominal supply voltages at
TJ = 25 °C.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
14
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
2.9. SubLVDS to MIPI CSI-2 Image Sensor Interface Bridge
Figure 2.9 shows the block diagram for a SubLVDS to MIPI CSI-2 Image Sensor Interface Bridge. This solution bridges
from an image sensor SubLVDS output to CSI-2 output to an application processor.
Table 2.9 provides additional details for a specific application example, including input and output descriptions and
device resource usage. The interface bridge is fully programmable, supporting RAW10 or RAW12 pixel width, variable
number of lanes, and data rates up to 1.2 Gb/s per lane input or 1.5 Gb/s per lane output. For details, refer to IPUG125,
SubLVDS to MIPI CSI-2 IP Image Sensor Interface Bridge Soft IP User Guide.
CrossLink
Image Sensor
SubLVDS
MIPI CSI-2
Application
Processor
Bridge
Figure 2.9. SubLVDS to MIPI CSI-2 Image Sensor Interface Bridge
Table 2.9. SubLVDS to MIPI CSI-2 Image Sensor Interface Bridge Overview
Application Example Details
Input Type
Programmable Fabric Operation(s)
Output Type
Additional System Functions
[email protected], RAW10
SubLVDS 10 data lane @ 600 Mb/s per lane
Interface Bridge
[email protected], RAW10
CSI-2 over 4-Lane MIPI D-PHY @ 1.5 Gb/s per lane
Image Frame Control
GPIO for reset and power control
Preliminary Example Device Resource Usage*
Typical Power Consumption
Device I/O Used
Fabric Resources Used
~130 mW
22 Programmable I/O; 1 x Hard D-PHY Quads
80% of LUT4; ~60% of EBR
*Note: For reference only – exact usage and power consumption depends on specific application parameters. Additional system
functions are not included in resource usage. The typical power consumption estimate is based on nominal supply voltages at
TJ = 25 °C.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
15
CrossLink Family
Preliminary Data Sheet
3. Product Feature Summary
Table 3.1 lists CrossLink device information and packages.
Table 3.1. CrossLink Feature Summary
Device
CrossLink
LUTs
5936
sysMEM Blocks (9 kb)
20
Embedded Memory (kb)
180
Distributed RAM Bits (kb)
47
General Purpose PLL
1
NVCM
Yes
Embedded I2C
2
Oscillator (10 KHz)
1
Oscillator (48 MHz)
1
Hardened MIPI D-PHY
2
Packages
I/O
1
2
36 WLCSP (2.535 × 2.583 mm2, 0.6 mm)
2
17
64 ucfBGA (3.5 × 3.5 mm , 1 mm)
29
80 ctfBGA (6.5 x 6.5 mm2, 1 mm)
36
2
81 csfBGA (4.5 × 4.5 mm , 1 mm)
37
Notes:
1. Additional D-PHY Rx interfaces are available using programmable I/O.
2. Only one Hardened D-PHY is available in 36 WLCSP package.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
4. Architecture Overview
CrossLink is designed as a flexible, chip-to-chip bridging solution which supports a wide variety of applications,
including those described in Application Examples section on page 7.
CrossLink provides three key building blocks for these bridging applications:
 Up to two embedded Hard D-PHY blocks
 Two banks of flexible programmable I/O supporting a variety of standards including D-PHY Rx, subLVDS, SLVS, LVDS,
and CMOS
 A programmable logic core providing the LUTs, memory, and system resources to implement a wide range of
bridging operations
In addition to these blocks, CrossLink also provides key system resources including a Power Management Unit, flexible
2
configuration interface, additional CMOS GPIO, and user I C blocks.
The block diagram for the device is shown in Figure 4.1.
Programmable IO
MIPI D-PHY
Rx: D-PHY / SubLVDS /
LVDS / SLVS200 / CMOS
Tx: LVDS / CMOS
1.2 Gb/s per Lane
14 IO / 7 Pairs
Programmable IO
Rx: D-PHY / SubLVDS /
LVDS / SLVS200 / CMOS
6 Gb/s
Rx & Tx
Programmable FPGA Fabric
5,936 LUTs
180 kbits block RAM
47 kbits distributed RAM
4 Data Lanes
1 Clock Lane
Enough FPGA resources to handle video:
Muxing
Merging
Demuxing
Arbitration
Splitting
Data Conversion
Custom Protocol Design
MIPI D-PHY
6 Gb/s
Rx & Tx
Tx: LVDS / CMOS
4 Data Lanes
1 Clock Lane
1.2 Gb/s per Lane
16 IO / 8 Pairs
Power Management Unit
I2C / SPI1
GPIOs
Figure 4.1. CrossLink Device Block Diagram
2
2
Note: I C and SPI configuration modes are supported. User mode hardened I C is also supported.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
17
CrossLink Family
Preliminary Data Sheet
4.1. MIPI D-PHY Blocks
The top side of the device includes two hard MIPI D-PHY quads. The D-PHY can be configured to support both camera
interface (CSI-2) and display interface (DSI) applications. Below is a summary of the features supported by the hard
D-PHY quads. Refer to TN1301, CrossLink High-Speed I/O Interface for more information on the Hard D-PHY quads.
 Transmit and Receive compliant to D-PHY Revision 1.1
 High-Speed (HS) and Low-Power (LP) mode support (including built-in contention detect)
 Up to 6 Gb/s per quad (1500 Mb/s data rate per lane)
 Dedicated PLL for Transmit Frequency Synthesis
 Dedicated Serializer and De-Serializer blocks for fabric interfacing
 Supports continuous clock mode or low power clock mode
Lattice Semiconductor provides a set of pre-engineered IP modules which include the full implementation and control
of the hard D-PHY blocks for the examples in Application Examples section on page 7, enabling designers to focus on
unique aspects of their design.
4.2. Programmable I/O Banks
CrossLink devices provide programmable I/O which can be used to interface to a variety of external standards. The I/O
features are summarized below, and described in detail in TN1301, CrossLink High-Speed I/O Interface and TN1305,
CrossLink sysI/O Usage Guide. The programmable LVDS/CMOS I/O (Banks 1 and 2) are described below, while the
CMOS GPIO (bank 0) and hard D-PHY quads are described separately.
Programmable LVDS/CMOS I/O (Bank 1 and 2) features:
 Built-in support for the following differential standards
 LVDS – Tx and Rx
 SLVS – Rx
 SubLVDS – Rx
 MIPI – Rx (both LP and HS receive on a single differential pair)
 Support for the following single ended standards (ratioed to VCCIO)
 LVCMOS33
 LVCMOS25
 LVCMOS18
 LVCMOS12
 LVTTL33
 Independent voltage levels per bank based on VCCIO supply
 Input/output gearboxes per LVDS pair supporting several ratios for video interface applications
 DDRX1, DDRX2, DDRX4, DDRX8 and DDRX71, DDRX141
 Programmable delay cells to support edge-aligned and center-aligned interfaces
 Programmable differential termination (~ 100 Ω) with dynamic enable control
 Tri-state control for output
 Input/output register blocks
 Single-ended standards support open-drain and programmable input hysteresis
 Optional weak pull-up resistors
4.3. Programmable FPGA Fabric
4.3.1. FPGA Fabric Overview
CrossLink is built around a programmable logic fabric consisting of 5936 four input lookup tables (LUT4) arranged
alongside dedicated registers in Programmable Functional Units (PFU). These PFU blocks are the building blocks for
logic, arithmetic, RAM and ROM functions. The PFU blocks are connected via a programmable routing network. The
Lattice Diamond design software configures the PFU blocks and the programmable routing for each unique design.
Interspersed between rows of PFU are rows of sysMEM™ Embedded Block RAM (EBR), with programmable I/O banks,
2
embedded I C and embedded MIPI D-PHY arranged on the top and bottom of the device as shown in Figure 4.2.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18
DS1055-1.0
MIPI D-PHY 0
PFU
PFU
I2C1
NVCM
I2C0
CrossLink Family
Preliminary Data Sheet
MIPI D-PHY 1
PFU
PFU
PFU
4 EBR Blocks (9 kb each)
4 EBR Blocks (9 Kb each)
4 EBR Blocks (9 kb each)
PFU
PFU
PFU
PFU
PFU
Bank 2
Clocking
PLL
OSC
Bank 1
DDRDLL1
4 EBR Blocks (9 kb each)
DDRDLL2
4 EBR Blocks (9 kb each)
PMU
CONFIG
Bank 0
Figure 4.2. CrossLink Device Simplified Block Diagram (Top Level)
4.3.2. Clocking Overview
The CrossLink device family provides resources to support a wide range of clocking requirements for programmable
video bridging. These resources are listed below. For details, refer to TN1304, CrossLink sysCLOCK PLL/DLL Design and
Usage Guide.
 sysCLOCK PLL
 Flexible Frequency Synthesis (See Table 5.15 for input frequency range and output frequency range.)
 Dynamically selectable Clock Input
 Four Clock Outputs
 Independent, dynamic enable control
 Programmable phase adjustment
 Standby Input
 Lock Output
 Clock Distribution Network
 Eight Primary Clocks
 Dedicated Clock input pins (PCLK)
 Source from PLL, Clock Divider, Hard D-PHY blocks or On-chip Oscillator
 Four Edge Clocks for high-speed DDR interfaces
 2 per Programmable I/O bank
 Source from PCLK pins, PLL or DLL blocks
 Programmable Clock divider per Edge Clock
 Delay primitives for 90 degree phase shifting of clock/data (DDRDLL, DLLDEL)
 Dynamic Clock Control
 Fabric control to disable clock nets for power savings
 Dynamic Clock Select
 Smart clock multiplexer with two independent inputs and glitchless output support
 Two On-Chip Oscillators
 Always-on Low Frequency (LFCLKOUT) with nominal frequency of 10 kHz
 High-Frequency (HFCLKOUT) with nominal frequency of 48 MHz, programmable output dividers, and dynamic
enable control
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
19
CrossLink Family
Preliminary Data Sheet
4.3.3. Embedded Block RAM Overview
CrossLink devices also contain sysMEM Embedded Block RAM (EBR). The EBR consists of a 9 kB RAM with memory core,
dedicated input registers and output registers with separate clock and clock enable. Supported modes and other
general information on the EBR are listed below. For details, refer to 1306, LIFMD Memory Usage Guide.
 Support for different memory configurations
 Single Port
 True Dual Port
 Pseudo Dual Port
 ROM
 FIFO (logic wrapper added automatically by design tools)
 Flexible customization features
 Initialization of RAM/ROM
 Memory cascading (handled automatically by design tools)
 Optional parity bit support
 Byte-enable
 Multiple block size options
 RAM modes support optional Write Through or Read-Before-Write modes
4.4. System Resources
4.4.1. CMOS GPIO (Bank 0)
CrossLink provides dedicated CMOS GPIO on Bank 0 of the device. These GPIO do not include differential signaling
support. A summary of the features associated with these GPIOs is listed below:
 Support for the following single ended standards (ratioed to VCCIO)
 LVCMOS33
 LVCMOS25
 LVCMOS18
 LVCMOS12
 LVTTL33
 Tri-state control for output
 Input/output register blocks
 Open-drain option and programmable input hysteresis
 Internal pull-up resistors with configurable values of 3.3 kΩ, 6.8 kΩ, 10 kΩ
4.4.2. Power Management Unit
The embedded Power Management Unit (PMU) allows low-power Sleep State of the device. Figure 4.3 on the next
page shows the block diagram of the PMU IP.
When instantiated in the design, PMU is always on, and uses the low-speed clock from oscillator of the device to
perform its operations.
The typical use case for the PMU is through a user implemented state machine that controls the sleep and wake up of
the device. The state machine implemented in the FPGA fabric identifies when the device needs to go into sleep mode,
issues the command through PMU’s FPGA fabric interface, assigns the parameters for sleep (time to wake up and so
on) and issues Sleep command.
The device can be woken up externally using the PMU Wake-Up (USRWKUP) pin, or from the PMU Watch Dog Timer
2
expiry or from I2C0 (address decoding detection or FIFO full in one of hardened I C).
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
Power Management Unit (PMU)
PMU Clock (From Oscillator)
(PMUCLK)
External User Wake-up
(USRWKUPN)
PMU Wake-up from I2C0
(PMUWKUP)
Watch Dog
Timer
PMU Control
Register
8-bit Addressable Fabric Interface
PMU Sleep Signal, SLEEP
Power Control Unit
Watch Dog Timer
User Mode Signals
From FPGA Fabric
Figure 4.3. CrossLink MIPI D-PHY Block
4.4.2.1. PMU State Machine
PMU can place the device in two mutually exclusive states – Normal State and Sleep State. Figure 4.4 shows the PMU
State Machine triggers for transition from one state to the other.
 Normal state – All elements of the device are active to the extent required by the design. In this state, the device is
at fully active and performing as required by the application.
Note that the power consumption of the device is highest in this state.
 Sleep state – The device is power gated such that the device is not operational. The configuration of the device and
the EBR contents are retained; thus in Sleep mode, the device does not lose configuration SRAM and EBR contents.
When it transitions to Normal state, device operates with these contents preserved.
The PMU is active along with the associated GPIOs.
The power consumption of the device is lowest in this state. This helps reduce the overall power consumption for
the device.
User Logic Initiated
Sleep Mode
Normal Mode
User I2C/
External Wake-up/
WDT Expiry Wake-up
Figure 4.4. CrossLink PMU State Machine
For more details, refer to TN1307, Power Management and Calculation for CrossLink Devices.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
21
CrossLink Family
Preliminary Data Sheet
4.4.3. Device Configuration
The CrossLink SRAM can be configured as follows:
 Internal Non Volatile Configuration Memory (NVCM)
2
 NVCM can be programmed using either the SPI or I C port
 Standard Serial Peripheral Interface (Master SPI Mode) Interface to external SPI Flash
 System microprocessor to drive a serial Slave SPI port (SSPI mode)
2
 System microprocessor to drive a serial Slave I C port
For more information, refer to TN1303, CrossLink Programming and Configuration Usage Guide. In addition to the
flexible configuration modes, the CrossLink configuration engine supports the following special features:
 TransFR (Transparent Field Reconfiguration) allowing users to update logic in field without interrupting system
operation by freezing I/O states during configuration
 Dual-Boot Support for primary and golden bitstreams provides automatic recovery from configuration failures
 Security and One-Time Programmable (OTP) modes protect bitstream integrity and prevent readback
 64-bit unique TraceID per device
4.4.4. User I2C IP
CrossLink devices have two I2C IP cores that can be configured either as an I2C master or as an I2C slave. The I2C0 core
2
has pre-assigned pins, and supports PMU wakeup over I C. The pins for the I2C1 interface are not pre-assigned – user
can use any General Purpose I/O pins.
The I2C cores support the following functionality:
 Master and Slave operation
 7-bit and 10-bit addressing
 Multi-master arbitration support
 Clock stretching
 Up to 1 MHz data transfer speed
 General call support
 Optionally delaying input or output data, or both
 Optional FIFO mode
 Transmit FIFO size is 10 bits x 16 bytes, receive FIFO size is 10 bits x 32 bytes
For further information on the User I2C, refer to TN308, LIFMD I2C Hardened IP Usage Guide.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
22
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
5. DC and Switching Characteristics
5.1. Absolute Maximum Ratings
Table 5.1. Absolute Maximum Ratings
Symbol
VCC
Parameter
Core Supply Voltage
Min
–0.5
Max
1.32
Unit
V
VCCPLL
PLL Supply Voltage
–0.5
1.32
V
VCCAUX25VPP
Auxiliary Supply Voltage for Bank 1, 2 and NVCM
–0.5
2.75
V
VCCIO
I/O Driver Supply Voltage for Banks 0, 1, 2
–0.5
3.63
V
—
VCC_DPHY
VCCA_DPHY
VCCPLL_DPHY
VCCMU_DPHY
—
Input or I/O Transient Voltage Applied
–0.5
3.63
V
MIPI D-PHY Supply Voltages
–0.5
1.32
V
Voltage Applied on MIPI D-PHY Pins
–0.5
1.32
V
TA
Storage Temperature (Ambient)
–65
150
°C
TJ
Junction Temperature (TJ)
—
+125
°C
Notes:
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is
not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
5.2. Recommended Operating Conditions
Table 5.2. Recommended Operating Conditions
Symbol
VCC
Parameter
Min
Max
Unit
Core Supply Voltage
1.14
1.26
V
VCCPLL
PLL Supply Voltage
1.14
1.26
V
VCCAUX25VPP
Auxiliary Supply Voltage for Bank 1, 2 and NVCM
2.375
2.625
V
VCCIO
I/O Driver Supply Voltage for Bank 0, 1, 2
1.14
3.465
V
TJIND
Junction Temperature, Industrial Operation
–40
100
°C
D-PHY External Power Supply
VCC_DPHYx
Supply Voltage for D-PHY
VCCA_DPHYx
Analog Supply Voltage for D-PHY
1.14
1.14
1.26
1.26
V
V
VCCPLL_DPHYx
1.14
1.26
V
1.14
1.26
V
VCCMU_DPHY
PLL Supply voltage for D-PHY
Supply for VCC_DPHY1, VCCA_DPHY1 and VCCPLL_DPHY1 on
the WLCSP36
Notes:
1. For Correct Operation, all supplies must be held in their valid operation range.
2. Like power supplies, must be tied together if they are at the same supply voltage. Follow the noise filtering recommendations in
TN1302, CrossLink Hardware Checklist.
3. See recommended voltages by I/O standard in Table 5.9 on page 26.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
23
CrossLink Family
Preliminary Data Sheet
5.3. Preliminary Power Supply Ramp Rates
Table 5.3. Preliminary Power Supply Ramp Rates
Symbol
Parameter
Min
Max
Unit
tRAMP
Power supply ramp rates for all power supplies except VCCAUX25VPP
0.6
10
V/ms
Note: Assumes monotonic ramp rates.
5.4. Preliminary Power-On-Reset Voltage Levels
Table 5.4. Preliminary Power-On-Reset Voltage Levels
Parameter
Symbol
VPORUP
Power-On-Reset ramp up trip point (Monitoring VCC,
VCCIO0, and VCCAUX25VPP)
Typ
Unit
VCC
0.685
V
VCCIO0
1.078
V
TBD
V
VCCAUX25VPP
Notes:
1. These POR ramp up trip points are only provided for guidance. Device operation is only characterized for power supply voltages
specified under recommended operating conditions.
2. Only VCCIO0 has a Power-On-Reset ramp up trip point. All other VCCIOs do not have Power-On-Reset ramp up detection.
3. VCCIO supplies should be powered-up before or together with the VCC and VCCAUX25VPP supplies.
4. Configuration starts after VCC, VCCIO0 and VCCAUX25VPP reach VPORUP. For details, see tREFRESH time in Table 5.22 on page 36.
5. Ensure all other VCCIO banks are active with valid input logic levels to properly control any critical output logic states.
5.5. ESD Performance
Refer to the LIFMD Product Family Qualification Summary for complete qualification data, including ESD performance.
5.6. Preliminary DC Electrical Characteristics
Over recommended operating conditions.
Table 5.5. Preliminary DC Electrical Characteristics
Symbol
Parameter
1, 4
IIL, IIH
Input or I/O Leakage
IPU
4
C1
2
C2
2
Condition
Max
Unit
—
—
±10
µA
−2.7
—
−31
µA
VCCIO = 1.8 V between 0 ≤ VIN ≤ 0.65 * VCCIO
−3
—
−31
µA
VCCIO = 2.5 V between 0 ≤ VIN ≤ 0.65 * VCCIO
−8
—
−72
µA
VCCIO = 3.3 V between 0 ≤ VIN ≤ 0.65 * VCCIO
−11
—
−128
µA
VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.2 V,
VCC = 1.2 V, VIO = 0 to VIH (MAX)
—
TBD
—
pf
VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.2 V,
VCC = 1.2 V, VIO = 0 to VIH (MAX)
—
TBD
—
pf
Hysteresis for Single-Ended VCCIO = 3.3 V, 2.5 V, 1.8 V
Inputs
VCC = 1.2 V, VIO = 0 to VIH (MAX)
—
200
—
mV
I/O Capacitance
2
Dedicated Input
2
Capacitance
3
Typ
VCCIO = 1.2 V between 0 ≤ VIN ≤ 0.65 * VCCIO
Internal Pull-Up Current
VHYST
0 ≤ VIN ≤ VCCIO
Min
Notes:
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is
not measured with the output driver active. Bus maintenance circuits are disabled.
2. TA = 25 oC, f = 1.0 MHz.
3. Hysteresis is not available for VCCIO = 1.2 V.
4. Weak pull-up setting. Programmable pull-up resistors on Bank 0 will see higher current. Refer to TN1305, CrossLink sysI/O
Usage Guide for details on programmable pull-up resistors.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
24
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
5.7. Preliminary CrossLink Supply Current (Standby)
Over recommended operating conditions.
Table 5.6. Preliminary CrossLink Supply Current (Standby)
Symbol
Parameter
Typ
Unit
ICC
Core Power Supply Current
4.5
mA
ICCPLL
PLL Power Supply Current
0.05
mA
0.5
mA
0.5
mA
0.6
mA
Normal Operation
Auxiliary Power Supply Current for Bank 1, 2 and NVCM Programming
Supply Current
Bank Power Supply Current (per Bank)
ICCAUX25VPP
ICCIO
Sleep Operation
Core Power Supply Current
ICC
Notes:
1. For further information on supply current, see the References section on page 52.
2. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the V CCIO or GND.
3. Frequency 0 Hz.
4. Normal operation pattern represents a “blank” configuration data file. Sleep operation includes
5. TJ = 25 °C, power supplies at nominal voltage.
6. To determine the CrossLink peak start-up current, use the Power Calculator tool in the Lattice Diamond Design Software.
5.8. Preliminary MIPI D-PHY Supply Current
Over recommended operating conditions.
Table 5.7. Preliminary MIPI D-PHY Supply Current
Symbol
1
Description
Typ
Unit
10
µA
Standby (Power Down)
ICCA_DPHYx
VCCA_DPHY Power Supply Current (per Channel) PHY
ICCPLL_DPHYx
PLL Supply voltage for D-PHY
5
µA
ICCMU_DPHYx
VCCA_DPHY1 and VCCPLL_DPHY1 on the WLCSP36
15
µA
Device
Max
Unit
All Devices
1
ms
Notes:
1. For further information on supply current, see the References section on page 52.
2. TJ = 25 °C, power supplies at nominal voltage.
5.9. Preliminary Power Management Unit (PMU) Timing
Table 5.8. Preliminary PMU Timing
Symbol
Parameter
tPMUWAKE
Time for PMU to wake from Sleep mode
Note: For details on PMU usage, refer to TN1307, Power Management and Calculation for CrossLink Devices.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
25
CrossLink Family
Preliminary Data Sheet
5.10. sysI/O Recommended Operating Conditions
Table 5.9. sysI/O Recommended Operating Conditions
VCCIO
Standard
Min
Typ
Max
LVCMOS33/LVTTL33
3.135
3.30
3.465
LVCMOS25
2.375
2.50
2.625
LVCMOS18
1.710
1.80
1.890
LVCMOS12
1.140
1.20
1.260
subLDVS (Input only)
2.375
2.50
2.625
SLVS (Input only)
2.375
2.50
2.625
LVDS
2.375
2.50
2.625
MIPI (Inputs)
1.140
1.20
1.260
Note: For input voltage compatibility, refer to TN1305, CrossLink sysI/O Usage Guide.
5.11. Preliminary sysI/O Single-Ended DC Electrical Characteristics
Table 5.10. Preliminary sysI/O Single-Ended DC Electrical Characteristics
Input/Output
Standard
VIL
VIH
Min (V)
Max (V)
Min (V)
Max (V)
LVCMOS33/
LVTTL33
–0.3
0.8
2.0
VCCIO+0.2
LVCMOS25
–0.3
0.7
1.7
VCCIO+0.2
LVCMOS18
–0.3
0.35 VCCIO
0.65 VCCIO
VCCIO+0.2
LVCMOS12
–0.3
0.35 VCCIO
0.8 VCCIO
VCCIO+0.2
VOL Max
(V)
VOH Min (V)
0.40
VCCIO − 0.4
8
–8
0.20
VCCIO − 0.2
0.1
–0.1
0.40
VCCIO − 0.4
6
–6
0.20
VCCIO − 0.2
0.1
–0.1
0.40
VCCIO − 0.4
4
–4
0.20
VCCIO − 0.2
0.1
–0.1
0.40
VCCIO − 0.4
2
–2
0.20
VCCIO − 0.2
0.1
–0.1
IOL (mA)
IOH (mA)
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
26
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
5.12. Preliminary sysI/O Differential Electrical Characteristics
5.12.1. Preliminary LVDS/subLVDS/SLVS
Over recommended operating conditions.
1
1
Table 5.11. LVDS/subLVDS /SLVS
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VINP, VINPM
Input Voltage
—
0.00
—
2.40
V
VCM
Input Common Mode Voltage
Half the sum of the two inputs
0.05
—
2.35
V
VTHD
Differential Input Threshold
Difference between the two inputs
±100
—
—
mV
VTHD(subLVDS)
Differential Input Threshold
Difference between the two inputs
±90
—
—
mV
Power On
—
—
±10
µA
IIN
Input Current
Power Off (standby)
—
—
±10
µA
VOH
Output High Voltage for VOP or VOM
RT = 100 Ω
—
1.43
1.60
V
VOL
Output Low Voltage for VOP or VOM
RT = 100 Ω
0.90
1.08
—
V
VOD
Output Voltage Differential
(VOP - VOM), RT = 100 Ω
250
350
450
mV
—
—
—
50
mV
VOS
Change in VOD Between High and
Low
Output Voltage Offset
1.13
1.20
1.375
V
∆VOS
Change in VOS Between H and L
—
—
—
50
mV
ISAB
Output Short Circuit Current
VOD = 0 V driver outputs shorted to
each other
—
—
12
mA
∆VOD
(VOP + VOM)/2, RT = 100 Ω
Notes:
1. Inputs only.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
27
CrossLink Family
Preliminary Data Sheet
5.12.2. Preliminary MIPI D-PHY
Table 5.12. Preliminary MIPI D-PHY
Description
Min
Typ
Max
Unit
70
—
330
mV
Receiver
High Speed
VCMRX
Common-Mode Voltage HS Receive Mode
VIDTH
Differential Input High Threshold
—
—
70
mV
VIDTL
Differential Input Low Threshold
−70
—
—
mV
VIHHS
Single-ended Input High Voltage
—
—
460
mV
VILHS
Single-ended Input Low Voltage
−40
—
—
mV
VTERM-EN
Single-ended Threshold for HS Termination Enable
—
—
450
mV
ZID
Differential Input Impedance
80
100
125
Ω
VIH
Logic 1 Input Voltage
880
—
—
mV
VIL
Logic 0 Input Voltage, not in ULP State
—
—
550
mV
VIL-ULPS
Logic 0 Input Voltage, in ULP State
—
—
300
mV
VHYST
Input Hysteresis
25
—
—
mV
Low Power
Transmitter
High Speed
VCMTX
HS Transmit Static Common Mode Voltage
150
200
250
mV
VOD
HS Transmit Differential Voltage
140
200
270
mV
VOHHS
HS Output High Voltage
—
—
360
mV
ZOS
Single-ended Output Impedance
40
50
62.5
Ω
ΔZOS
Single-ended Output Impedance Mismatch
—
—
10
%
VOH
Output High Level
1.1
1.2
1.3
V
VOL
Output Low Level
−50
—
50
mV
ZOLP
Output Impedance of LP Transmitter
110
—
—
Ω
Low Power
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
28
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
5.13. Preliminary CrossLink Maximum I/O Buffer Speed
Over recommended operating conditions.
Table 5.13. Preliminary CrossLink Maximum I/O Buffer Speed
Buffer
Description
Max
Unit
600
MHz
500
MHz
600
MHz
500
MHz
600
MHz
500
MHz
600
MHz
500
MHz
Maximum Input Frequency
LVDS, VCCIO = 2.5 V, csfBGA81, ctfBGA80, ucfBGA64
packages
LVDS, VCCIO = 2.5 V, WLCSP36 package
LVDS25
SUBLVDS, VCCIO = 2.5 V, csfBGA81, ctfBGA80,
ucfBGA64 packages
SUBLVDS, VCCIO = 2.5 V, WLCSP36 package
SUBLVDS
LVTTL33
MIPI D-PHY, csfBGA81, ctfBGA80, ucfBGA64
packages
MIPI D-PHY, WLCSP36 package
SLVS, VCCIO=2.5V, csfBGA81, ctfBGA80, ucfBGA64
packages
SLVS, VCCIO=2.5V, WLCSP36 package
LVTTL, VCCIO = 3.3 V
250
MHz
LVCMOS33
LVCMOS, VCCIO = 3.3 V
250
MHz
LVCMOS25D
Differential LVCMOS, VCCIO = 2.5 V
250
MHz
LVCMOS25
LVCMOS, VCCIO = 2.5 V
250
MHz
LVCMOS18
LVCMOS, VCCIO = 1.8 V
155
MHz
LVCMOS12
LVCMOS 1.2, VCCIO = 1.2 V
70
MHz
LVDS, VCCIO = 2.5 V, csfBGA81, ctfBGA80, ucfBGA64
packages
600
MHz
LVDS, VCCIO = 2.5 V, WLCSP36 package
500
MHz
LVTTL33
LVTTL, VCCIO = 3.3 V
250
MHz
LVCMOS33
LVCMOS, 3.3 V
250
MHz
LVCMOS33D
Differential LVCMOS, 3.3 V
250
MHz
LVCMOS25
LVCMOS, 2.5 V
250
MHz
LVCMOS25D
Differential LVCMOS, 2.5 V
250
MHz
LVCMOS18
LVCMOS, 1.8 V
155
MHz
LVCMOS12
LVCMOS, VCCIO = 1.2 V
70
MHz
MIPI D-PHY (HS Mode)
6
SLVS
Maximum Output Frequency
LVDS25
Notes:
1. These maximum speeds are characterized but not tested on every device.
2. Maximum I/O speed for differential output standards emulated with resistors depends on the layout.
3. LVCMOS timing is measured with the load specified in Table 5.23 on page 37.
4. Actual system operation may vary depending on user logic implementation.
5. Maximum data rate equals two times the clock rate when utilizing DDR.
6. This is the maximum MIPI D-PHY input rate on the programmable I/O banks 1 and 2. The hardened MIPI D-PHY input and
output rates are described in MIPI D-PHY Performance section on page 35.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
29
CrossLink Family
Preliminary Data Sheet
5.14. Preliminary CrossLink External Switching Characteristics
Over recommended commercial operating conditions.
Table 5.14. Preliminary CrossLink External Switching Characteristics
Parameter
Description
Device
Min
Clocks
Primary Clock
fMAX_PRI
Frequency for Primary Clock Tree
All Devices
—
tW_PRI
Clock Pulse Width for Primary Clock
All Devices
0.8
tISKEW_PRI
Primary Clock Skew Within a Clock
All Devices
—
Edge Clock
fMAX_EDGE
Frequency for Edge Clock Tree
All Devices
—
tW_EDGE
Clock Pulse Width for Edge Clock
All Devices
0.783
tISKEW_EDGE
Edge Clock Skew Within a Bank
All Devices
—
Generic DDR Input
Generic DDRX8 or DDRX4 I/O with Clock and Data Centered at Pin (GDDRX8_RX/TX.ECLK.Centered or
GDDRX4_RX/TX.ECLK.Centered)
tSU_GDDRX4_8
Input Data Set-Up Before CLK
tHO_GDDRX4_8
Input Data Hold After CLK
tDVB_GDDRX4_8
Output Data Valid Before CLK Output
tDVA_GDDRX4_8
Output Data Valid After CLK Output
fMAX_GDDRX4_8
Frequency for ECLK
Max
Unit
150
—
450
MHz
ns
ps
600
—
120
MHz
ns
ps
All Devices
All Devices
All Devices
All Devices
All Devices
All Devices
All Devices
csfBGA81,
ctfBGA80,
ucfBGA64
0.167
0.2
0.167
0.297
−0.120
0.297
−0.120
—
—
—
—
—
—
—
ns
UI
ns
ns
ns+1/2UI
ns
ns+1/2UI
—
600
MHz
WLCSP36
—
500
MHz
Generic DDRX8 or DDRX4 I/O with Clock and Data Aligned at Pin (GDDRX8_RX/TX.ECLK.Aligned or GDDRX4_RX/TX.ECLK.Aligned)
tDVA_GDDRX4_8
Input Data Valid After CLK
tDVE_GDDRX4_8
Input Data Hold After CLK
tDIA_GDDRX4_8
Output Data Invalid After CLK Output
Output Data Invalid Before CLK
Output
tDIB_GDDRX4_8
fMAX_GDDRX4_8
Frequency for ECLK
Programmable I/O MIPI D-PHY Rx with 1:8 or 1:16 Gearing
tSU_GDDRX_MP
Input Data Set-Up Before CLK
tHO_GDDRX_MP
Input Data Hold After CLK
fMAX_GDDRX_MP
Frequency for ECLK
All Devices
All Devices
All Devices
All Devices
All Devices
All Devices
All Devices
—
—
—
0.229
0.646
0.775
—
−0.229
0.188
0.22
—
—
—
0.120
ns+1/2UI
ns
UI
ns+1/2UI
ns
UI
ns
All Devices
—
0.120
ns
csfBGA81,
ctfBGA80,
WLCSP36
ucfBGA64
—
—
600
500
MHz
MHz
All Devices
All Devices
All Devices
csfBGA81,
ctfBGA80,
ucfBGA64
WLCSP36
0.167
−0.2
01.67
—
—
—
ns
UI
ns
—
600
MHz
—
500
MHz
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
30
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
Table 5.14. Preliminary CrossLink External Switching Characteristics (Continued)
Parameter
Description
Device
–6
Min
Generic DDRX71 or DDRX141 Inputs (GDDRX71_RX.ECLK or GDDRX141_RX.ECLK)
All Devices
Input Valid Bit "i" switching from CLK
tRPBi_DVA
Rising Edge ("i" = 0 to 6, 0 aligns with CLK)
All Devices
Max
Unit
—
0.3
UI
—
−0.222
ns+(i+ 1/2)*UI
tRPBi_DVE
Input Hold Bit "i" switching from CLK
Rising Edge ("i" = 0 to 6, 0 aligns with CLK)
All Devices
0.7
—
UI
All Devices
0.222
—
ns+(i+ 1/2)*UI
fMAX_RX71
DDR71 ECLK Frequency
All Devices
—
450
MHz
—
0.143
ns+i*UI
−0.143
—
ns+(i+ 1)*UI
—
—
—
0.15
525
500
UI
MHz
MHz
—
0.125
ns+i*UI
All Devices
−0.125
—
ns+(i+ 1)*UI
All Devices
csfBGA81
WLCSP36
—
—
—
0.15
600
500
UI
MHz
MHz
Generic DDRX71 Outputs with Clock and Data Aligned at Pin (GDDRX71_TX.ECLK)
Data Output Valid Bit "i" switching from
CLK Rising Edge ("i" = 0 to 6, 0 aligns with
TTPBi_DOV
All Devices
CLK)
TTPBi_DOI
Data Output Invalid Bit "i" switching from
CLK Rising Edge ("i" = 0 to 6, 0 aligns with
CLK)
TTPBi_skew_UI
TX skew in UI
All Devices
All Devices
csfBGA81
fMAX_TX71
DDR71 ECLK Frequency
WLCSP36
Generic DDRX141 Outputs with Clock and Data Aligned at Pin (GDDRX141_TX.ECLK)
Data Output Valid Bit "i" switching from
CLK Rising Edge ("i" = 0 to 6, 0 aligns with
TTPBi_DOV
All Devices
CLK)
TTPBi_DOI
Data Output Invalid Bit "i" switching from
CLK Rising Edge ("i" = 0 to 6, 0 aligns with
CLK)
TTPBi_skew_UI
TX skew in UI
fMAX_TX141
DDR71 ECLK Frequency
Notes:
1. General I/O timing numbers based on LVCMOS 2.5, 0 pf load.
2. Generic DDRX8, DDRX71 and DDRX141 timing numbers based on LVDS I/O.
3. Uses LVDS I/O standard.
4. Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment.
5. These numbers are generated using best case PLL located in the center of the device.
6. All numbers are generated with the Lattice Diamond software.
Rx CLK (in)
Rx DATA (in)
tSU/tDVBDQ
tSU/tDVBDQ
tHD/tDVADQ
tHD/tDVADQ
Figure 5.1. Receiver RX.CLK.Centered Waveforms
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
31
CrossLink Family
Preliminary Data Sheet
1/2 UI
1/2 UI
1 UI
Rx CLK (in)
Rx DATA (in)
tSU
tSU
tHD
tHD
Figure 5.2. Receiver RX.CLK.Aligned Input Waveforms
1/2 UI
1/2 UI
1/2 UI
1/2 UI
Tx CLK (out)
Tx DATA (out)
tDVB
tDVB
tDVA
tDVA
Figure 5.3. Transmit TX.CLK.Centered Output Waveforms
1 UI
Tx CLK (out)
Tx DATA (out)
tDIB
tDIB
tDIA
tDIA
Figure 5.4. Transmit TX.CLK.Aligned Waveforms
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
32
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
Figure 5.5. DDRX71, DDRX141 Video Timing Waveforms
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
33
CrossLink Family
Preliminary Data Sheet
5.15. Preliminary sysCLOCK PLL Timing
Over recommended operating conditions.
Table 5.15. Preliminary sysCLOCK PLL Timing
Parameter
Descriptions
Conditions
fIN
Input Clock Frequency (CLKI, CLKFB)
Output Clock Frequency (CLKOP, CLKOS)
fOUT
AC Characteristics
tDT
Output Clock Duty Cycle
tPH4
Output Phase Accuracy
Output Clock Period Jitter
1
tOPJIT
Output Clock Cycle-to-Cycle Jitter
Output Clock Phase Jitter
Min
Max
Unit
—
10
400
MHz
—
4.6875
600
MHz
—
45
55
—
fOUT ≥ 100 MHz
−5
—
—
5
100
%
%
fOUT < 100 MHz
fOUT ≥ 100 MHz
fOUT < 100 MHz
fPFD > 100 MHz
—
—
fPFD < 100 MHz
—
—
0.025
200
0.05
200
0.05
ps p-p
UIPP
ps p-p
UIPP
ps p-p
UIPP
tSPO
2
tLOCK
Static Phase Offset
PLL Lock-in Time
Divider ratio = integer
—
—
—
400
1
ps p-p
tUNLOCK
PLL Unlock Time
tIPJIT
Input Clock Period Jitter
—
fPFD ≥ 20 MHz
—
—
50
500
ns
ps p-p
tHI
Input Clock High Time
fPFD < 20 MHz
90% to 90%
—
0.5
0.02
—
UIPP
ns
ms
tLO
Input Clock Low Time
10% to 10%
0.5
—
ns
Notes:
1. Jitter sample is taken over 10,000 samples for Periodic jitter, and 2,000 samples for Cycle-to-Cycle jitter of the primary PLL
output with clean reference clock with no additional I/O toggling.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Period jitter and cycle-to-cycle jitter numbers are guaranteed for fPFD > 10 MHz. For fPFD < 10 MHz, the jitter numbers may not
be met in certain conditions.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
34
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
5.16. MIPI D-PHY Performance
Table 5.16. 1500 Mb/s MIPI_DPHY_X8_RX/TX Timing Table (1500 Mb/s > MIPI D-PHY Data Rate > 1200 Mb/s)
Parameter
Description
Min
Max
Unit
tSU_MIPIX8
Input Data Setup before CLK
0.133
—
ns
tHO_MIPIX8
Input Data Hold after CLK
0.133
—
ns
tDVB_MIPIX8
Output Data Valid before CLK Output
0.200
—
ns
tDVA_MIPIX8
Output Data Valid after CLK Output
0.200
—
ns
Note: For WLCSP36 package, the MIPI D-PHY fmax is 1200 Mb/s, instead of 1500 Mb/s for other packages.
Table 5.17. 1200 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1200 Mb/s > MIPI D-PHY Data Rate > 1000 Mb/s)
Parameter
Description
Min
Max
Unit
tSU_MIPIX4
Input Data Setup before CLK
0.167
—
ns
tHO_MIPIX4
Input Data Hold after CLK
0.167
—
ns
tDVB_MIPIX4
Output Data Valid before CLK Output
0.250
—
ns
Output Data Valid after CLK Output
0.250
—
ns
tDVA_MIPIX4
Table 5.18. 1000 Mb/s MIPI_DPHY_X4_RX/TX Timing Table (1000 Mb/s > MIPI D-PHY Data Rate > 10 Mb/s)
Parameter
Description
Min
Max
Unit
tSU_MIPIX4
Input Data Setup before CLK
0.150
—
ns
tHO_MIPIX4
Input Data Hold after CLK
0.150
—
ns
tDVB_MIPIX4
Output Data Valid before CLK Output
0.350
—
ns
tDVA_MIPIX4
Output Data Valid after CLK Output
0.250
—
ns
5.17. Preliminary Internal Oscillators (HFOSC, LFOSC)
Table 5.19. Preliminary Internal Oscillators
Parameter
Parameter Description
Min
Typ
Max
Unit
fCLKHF
HFOSC CLKK Clock Frequency
43.2
48
52.8
MHz
fCLKLF
LFOSC CLKK Clock Frequency
9
10
11
kHz
DCHCLKHF
HFOSC Duty Cycle (Clock High Period)
45
—
55
%
DCHCLKLF
LFOSC Duty Cycle (Clock High Period)
45
—
55
%
5.18. Preliminary User I2C1
2 1
Table 5.20. Preliminary User I C
Symbol
fscl
Parameter
SCL Clock
Freqeuency
STD Mode
FAST Mode
FAST Mode Plus
Min
Max
Min
Max
Min
Max
—
100
—
400
—
1000
2
Units
kHz
Notes:
2
1. Refer to the I C Specification for timing requirements.
2. Fast Mode Plus maximum speed may be achieved by using external pull up resistor on I.C bus. Internal pull up may not be
sufficient to support the maximum speed.
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
35
CrossLink Family
Preliminary Data Sheet
5.19. CrossLink sysCONFIG Port Timing Specifications
Over recommended operating conditions.
Table 5.21. CrossLink sysCONFIG Port Timing Specifications
Symbol
Parameter
Min
Max
Unit
CRESETB LOW Pulse Accepted
110
—
ns
fCCLK
SPI_SCK Input Clock Frequency
—
110
MHz
tSTSU
MOSI Setup Time
0.5
—
ns
tSTH
MOSI Hold Time
0.5
—
ns
tSTCO
SPI_SCK Falling Edge to Valid MISO Output
—
13.3
ns
tSCS
Chip Select HIGH Time
25
—
ns
tSCSS
Chip Select Setup Time
0.5
—
ns
tSCSH
Chip Select Hold Time
0.5
—
ns
MCK Output Clock Frequency
—
55
MHz
Maximum SCL Clock Frequency (Fast-Mode Plus
—
1
MHz
All Configuration Mode
tPRGM
Slave SPI
Master SPI
fCCLK
2
I C*
fMAX
2
*Note: Refer to the I C specification for timing requirements.
5.20. Preliminary SRAM Configuration Time from NVCM
Over recommended operating conditions.
Table 5.22. Preliminary SRAM Configuration Time from NVCM
Symbol
Parameter
Typ
Unit
tREFRESH
POR to Device I/O Active
60
ms
Note: Before and during configuration, the I/Os are held in tristate with weak internal pull ups enabled. I/Os are released to user
functionality once the device has finished configuration.
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
36
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
5.21. Switching Test Conditions
Figure 5.6 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are listed in Table 5.23.
VT
R1
Test Point
DUT
R2
CL*
*CL Includes Test Fixture and Probe Capacitance
Figure 5.6. Output Test Load, LVTTL and LVCMOS Standards
Table 5.23. Test Fixture Required Components, Non-Terminated Interfaces
Test Condition
R1
R2
CL
Timing Ref.
VT
LVCMOS 3.3 = 1.5 V
—
LVCMOS 2.5 = VCCIO/2
—
LVCMOS 1.8 = VCCIO/2
—
LVTTL and other LVCMOS settings (L ≥ H, H ≥ L)
∞
∞
0 pF
LVCMOS 1.2 = VCCIO/2
—
LVCMOS 2.5 I/O (Z ≥ H)
∞
1 MΩ
0 pF
VCCIO/2
—
LVCMOS 2.5 I/O (Z ≥ L)
1 MΩ
∞
0 pF
VCCIO/2
VCCIO
LVCMOS 2.5 I/O (H ≥ Z)
∞
100
0 pF
LVCMOS 2.5 I/O (L ≥ Z)
100
∞
0 pF
VOH – 0.10
VOL + 0.10
—
VCCIO
Note: Output test conditions for all other interfaces are determined by the respective standards.
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
37
CrossLink Family
Preliminary Data Sheet
6. Pinout Information
6.1. WLCSP36 Pinout
Pin Number
Pin Function
Bank
Dual Function
Differential
A1
GNDMU_DPHY1
GND
—
—
A2
VCCMU_DPHY1
DPHY1
—
—
A3
DPHY1_DP2
DPHY1
—
True_OF_DPHY1_DN2
A4
DPHY1_DN2
DPHY1
—
Comp_OF_DPHY1_DP2
A5
VCCAUX25VPP
VCCAUX
—
—
A6
PB2C
2
MIPI_CLKT2_0
True_OF_PB2D
B1
DPHY1_DP0
DPHY1
—
True_OF_DPHY1_DN0
B2
DPHY1_DP1
DPHY1
—
True_OF_DPHY1_DN1
B3
DPHY1_DP3
DPHY1
—
True_OF_DPHY1_DN3
B4
DPHY1_DN3
DPHY1
—
Comp_OF_DPHY1_DP3
B5
PB16D
2
PCLKC2_1
Comp_OF_PB16C
B6
PB2D
2
MIPI_CLKC2_0
Comp_OF_PB2C
C1
DPHY1_DN0
DPHY1
—
Comp_OF_DPHY1_DP0
C2
DPHY1_DN1
DPHY1
—
Comp_OF_DPHY1_DP1
C3
PB52
0
SPI_SS/CSN/SCL
—
C4
VCC
VCCAUX
—
—
C5
PB16C
2
PCLKT2_1
True_OF_PB16D
C6
GND
GND
—
—
D1
DPHY1_CKP
DPHY1
—
True_OF_DPHY1_CKN
D2
PB48
0
PCLKT0_1/USER_SCL
—
D3
PB47
0
PCLKT0_0/USER_SDA
—
D4
CRESET_B
0
CRESET_B
—
D5
PB16B
2
PCLKC2_0
Comp_OF_PB16A
D6
PB6B
2
—
Comp_OF_PB6A
E1
DPHY1_CKN
DPHY1
—
Comp_OF_DPHY1_CKP
E2
VCCIO0
0
—
—
E3
GND
GND
—
—
E4
PB50
0
MOSI
—
E5
PB16A
2
PCLKT2_0
True_OF_PB16B
E6
PB6A
2
GR_PCLK2_0
True_OF_PB6B
F1
PB51
0
MISO
—
F2
PB49
0
PMU_WKUPN/CDONE
—
F3
PB53
0
SPI_SCK/MCK/SDA
—
F4
PB12A
2
GPLLT2_0
True_OF_PB12B
F5
PB12B
2
GPLLC2_0
Comp_OF_PB12A
F6
VCCIO2
2
—
—
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
38
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
6.2. ucfBGA64 Pinout
Pin Number
Pin Function
Bank
Dual Function
Differential
A1
DPHY1_CKP
DPHY1
—
True_OF_DPHY1_CKN
A2
DPHY1_CKN
DPHY1
—
Comp_OF_DPHY1_CKP
A3
DPHY1_DP3
DPHY1
—
True_OF_DPHY1_DN3
A4
DPHY1_DN3
DPHY1
—
Comp_OF_DPHY1_DP3
A5
DPHY0_DN2
DPHY0
—
Comp_OF_DPHY0_DP2
A6
DPHY0_DN0
DPHY0
—
Comp_OF_DPHY0_DP0
A7
DPHY0_CKP
DPHY0
—
True_OF_DPHY0_CKN
A8
DPHY0_CKN
DPHY0
—
Comp_OF_DPHY0_CKP
B1
DPHY1_DP2
DPHY1
—
True_OF_DPHY1_DN2
B2
DPHY1_DN2
DPHY1
—
Comp_OF_DPHY1_DP2
B3
DPHY1_DP1
DPHY1
—
True_OF_DPHY1_DN1
B4
DPHY1_DN1
DPHY1
—
Comp_OF_DPHY1_DP1
B5
DPHY0_DP2
DPHY0
—
True_OF_DPHY0_DN2
B6
DPHY0_DP0
DPHY0
—
True_OF_DPHY0_DN0
B7
DPHY0_DP3
DPHY0
—
True_OF_DPHY0_DN3
B8
DPHY0_DN3
DPHY0
—
Comp_OF_DPHY0_DP3
C1
DPHY1_DP0
DPHY1
—
True_OF_DPHY1_DN0
C2
DPHY1_DN0
DPHY1
—
Comp_OF_DPHY1_DP0
C3
PB47
0
PCLKT0_0/USER_SDA
—
C4
VCC
VCC
—
—
C5
VCCA_DPHYX
DPHY
—
—
C6
GNDA_DPHYX
GND
—
—
C7
DPHY0_DP1
DPHY0
—
True_OF_DPHY0_DN1
C8
DPHY0_DN1
DPHY0
—
Comp_OF_DPHY0_DP1
D1
PB34B
1
—
Comp_OF_PB34A
D2
PB34A
1
GR_PCLK1_0
True_OF_PB34B
D3
PB52
0
SPI_SS/CSN/SCL
—
D4
GND
GND
—
—
D5
VCCPLL_DPHY1
DPHY1
—
—
D6
VCCAUX25VPP
VCCAUX
—
—
D7
PB16A
2
PCLKT2_0
True_OF_PB16B
D8
PB12A
2
GPLLT2_0
True_OF_PB12B
E1
PB51
0
MISO
—
E2
CRESET_B
0
CRESET_B
—
E3
PB48
0
PCLKT0_1/USER_SCL
—
E4
VCC
VCC
—
—
E5
GND
GND
—
—
E6
VCCIO2
2
—
—
E7
PB16B
2
PCLKC2_0
Comp_OF_PB16A
E8
PB12B
2
GPLLC2_0
Comp_OF_PB12A
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
39
CrossLink Family
Preliminary Data Sheet
ucfBGA64 Pinout (Continued)
Pin Number
Pin Function
Bank
Dual Function
Differential
F1
PB53
0
SPI_SCK/MCK/SDA
—
F2
PB50
0
MOSI
—
F3
VCCIO0
0
—
—
F4
VCCIO1
1
—
—
F5
GND
GND
—
—
F6
VCCIO2
2
—
—
F7
PB6A
2
GR_PCLK2_0
True_OF_PB6B
F8
PB6B
2
—
Comp_OF_PB6A
G1
PB38D
1
—
Comp_OF_PB38C
G2
PB38C
1
—
True_OF_PB38D
G3
PB49
0
PMU_WKUPN/CDONE
—
G4
VCCGPLL
VCCGPLL
—
—
G5
PB29B
1
PCLKC1_0
Comp_OF_PB29A
G6
PB29A
1
PCLKT1_0
True_OF_PB29B
G7
PB2C
2
MIPI_CLKT2_0
True_OF_PB2D
G8
PB2D
2
MIPI_CLKC2_0
Comp_OF_PB2C
H1
PB34D
1
MIPI_CLKC1_0
Comp_OF_PB34C
H2
PB34C
1
MIPI_CLKT1_0
True_OF_PB34D
H3
PB29D
1
PCLKC1_1
Comp_OF_PB29C
H4
PB29C
1
PCLKT1_1
True_OF_PB29D
H5
PB16D
2
PCLKC2_1
Comp_OF_PB16C
H6
PB16C
2
PCLKT2_1
True_OF_PB16D
H7
PB12D
2
—
Comp_OF_PB12C
H8
PB12C
2
—
True_OF_PB12D
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
40
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
6.3. ctfBGA80 Pinout
Pin Number
Pin Function
Bank
Dual Function
Differential
A1
DPHY1_DN2
DPHY1
—
Comp_OF_DPHY1_DP2
A2
DPHY1_DN0
DPHY1_DN0
—
Comp_OF_DPHY1_DP0
A3
DPHY1_CKN
DPHY1
—
Comp_OF_DPHY1_CKP
A4
DPHY1_DN1
DPHY1
—
Comp_OF_DPHY1_DP1
A5
DPHY1_DN3
DPHY1
—
Comp_OF_DPHY1_DP3
A6
DPHY0_DN2
DPHY0
—
Comp_OF_DPHY0_DP2
A7
DPHY0_DN0
DPHY0
—
Comp_OF_DPHY0_DP0
A8
DPHY0_CKN
DPHY0
—
Comp_OF_DPHY0_CKP
A9
DPHY0_DN1
DPHY0
—
Comp_OF_DPHY0_DP1
A10
DPHY0_DN3
DPHY0
—
Comp_OF_DPHY0_DP3
B1
DPHY1_DP2
DPHY1
—
True_OF_DPHY1_DN2
B2
DPHY1_DP0
DPHY1
—
True_OF_DPHY1_DN0
B3
DPHY1_CKP
DPHY1
—
True_OF_DPHY1_CKN
B4
DPHY1_DP1
DPHY1
—
True_OF_DPHY1_DN1
B5
DPHY1_DP3
DPHY1
—
True_OF_DPHY1_DN3
B6
DPHY0_DP2
DPHY0
—
True_OF_DPHY0_DN2
B7
DPHY0_DP0
DPHY0
—
True_OF_DPHY0_DN0
B8
DPHY0_CKP
DPHY0
—
True_OF_DPHY0_CKN
B9
DPHY0_DP1
DPHY0
—
True_OF_DPHY0_DN1
B10
DPHY0_DP3
DPHY0
—
True_OF_DPHY0_DN3
C1
GND
GND
—
—
C2
GNDA_DPHY1
DPHY1
—
—
C9
GNDA_DPHY0
DPHY0
—
—
C10
GND
GND
—
—
D1
PB48
0
PCLKT0_1/USER_SCL
—
D2
VCCPLL_DPHY1
DPHY1
—
—
D4
VCCA_DPHY1
DPHY1
—
—
D5
VCCAUX25VPP
VCCAUX
—
—
D6
GNDPLL_DPHYX
GND
—
—
D7
VCCPLL_DPHY0
DPHY0
—
—
D9
PB16A
2
PCLKT2_0
True_OF_PB16B
D10
PB16B
2
PCLKC2_0
Comp_OF_PB16A
E1
PB34A
1
GR_PCLK1_0
True_OF_PB34B
E2
PB34B
1
—
Comp_OF_PB34A
E4
VCC
VCC
—
—
E5
GND
GND
—
—
E6
VCC
VCC
—
—
E7
VCCA_DPHY0
DPHY0
—
—
E9
PB12A
2
GPLLT2_0
True_OF_PB12B
E10
PB12B
2
GPLLC2_0
Comp_OF_PB12A
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
41
CrossLink Family
Preliminary Data Sheet
ctfBGA80 Pinout (Continued)
Pin Number
Pin Function
Bank
Dual Function
Differential
F1
PB38A
1
—
True_OF_PB38B
F2
PB38B
1
—
Comp_OF_PB38A
F4
VCCIO0
0
—
—
F5
VCCIO1
1
—
—
F6
VCCIO2
2
—
—
F7
VCCIO2
2
—
—
F9
PB6A
2
GR_PCLK2_0
True_OF_PB6B
F10
PB6B
2
—
Comp_OF_PB6A
G1
PB50
0
MOSI
—
G2
GND
GND
—
—
G4
VCCIO1
1
—
—
G5
GND
GND
—
—
G6
VCCGPLL
VCCGPLL
—
—
G7
GNDGPLL
GND
—
—
G9
PB2A
2
—
True_OF_PB2B
G10
PB2B
2
—
Comp_OF_PB2A
H1
PB52
0
SPI_SS/CSN/SCL
—
H2
CRESET_B
0
CRESET_B
—
H9
PB2D
2
MIPI_CLKC2_0
Comp_OF_PB2C
H10
PB2C
2
MIPI_CLKT2_0
True_OF_PB2D
J1
PB53
0
SPI_SCK/MCK/SDA
—
J2
PB49
0
PMU_WKUPN/CDONE
—
J3
PB43D
1
—
Comp_OF_PB43C
J4
PB38D
1
—
Comp_OF_PB38C
J5
PB34D
1
MIPI_CLKC1_0
Comp_OF_PB34C
J6
PB29D
1
PCLKC1_1
Comp_OF_PB29C
J7
PB29A
1
PCLKT1_0
True_OF_PB29B
J8
PB16D
2
PCLKC2_1
Comp_OF_PB16C
J9
PB6D
2
—
Comp_OF_PB6C
J10
PB6C
2
—
True_OF_PB6D
K1
PB51
0
MISO
—
K2
PB47
0
PCLKT0_0/USER_SDA
—
K3
PB43C
1
—
True_OF_PB43D
K4
PB38C
1
—
True_OF_PB38D
K5
PB34C
1
MIPI_CLKT1_0
True_OF_PB34D
K6
PB29C
1
PCLKT1_1
True_OF_PB29D
K7
PB29B
1
PCLKC1_0
Comp_OF_PB29A
K8
PB16C
2
PCLKT2_1
True_OF_PB16D
K9
PB12D
2
—
Comp_OF_PB12C
K10
PB12C
2
—
True_OF_PB12D
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
42
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
6.4. csfBGA81 Pinout
Pin Number
Pin Function
Bank
Dual Function
Differential
A1
DPHY1_CKP
DPHY1
—
True_OF_DPHY1_CKN
A2
DPHY1_CKN
DPHY1
—
Comp_OF_DPHY1_CKP
A3
DPHY1_DP1
DPHY1
—
True_OF_DPHY1_DN1
A4
DPHY1_DP3
DPHY1
—
True_OF_DPHY1_DN3
A5
VCCA_DPHY1
DPHY1
—
—
A6
DPHY0_DN2
DPHY0
—
Comp_OF_DPHY0_DP2
A7
DPHY0_DN0
DPHY0
—
Comp_OF_DPHY0_DP0
A8
DPHY0_CKP
DPHY0
—
True_OF_DPHY0_CKN
A9
DPHY0_CKN
DPHY0
—
Comp_OF_DPHY0_CKP
B1
DPHY1_DP0
DPHY1
—
True_OF_DPHY1_DN0
B2
DPHY1_DN0
DPHY1
—
Comp_OF_DPHY1_DP0
B3
DPHY1_DN1
DPHY1
—
Comp_OF_DPHY1_DP1
B4
DPHY1_DN3
DPHY1
—
Comp_OF_DPHY1_DP3
B5
GNDPLL_DPHYX
GND
—
—
B6
DPHY0_DP2
DPHY0
—
True_OF_DPHY0_DN2
B7
DPHY0_DP0
DPHY0
—
True_OF_DPHY0_DN0
B8
DPHY0_DP1
DPHY0
—
True_OF_DPHY0_DN1
B9
DPHY0_DN1
DPHY0
—
Comp_OF_DPHY0_DP1
C1
DPHY1_DP2
DPHY1
—
True_OF_DPHY1_DN2
C2
DPHY1_DN2
DPHY1
—
Comp_OF_DPHY1_DP2
C3
GNDA_DPHY1
DPHY1
—
—
C4
VCCPLL_DPHY1
DPHY1
—
—
C5
GND
GND
—
—
C6
VCCPLL_DPHY0
DPHY0
—
—
C7
GNDA_DPHY0
DPHY0
—
—
C8
DPHY0_DP3
DPHY0
—
True_OF_DPHY0_DN3
C9
DPHY0_DN3
DPHY0
—
Comp_OF_DPHY0_DP3
D1
PB34A
1
GR_PCLK1_0
True_OF_PB34B
D2
PB34B
1
—
Comp_OF_PB34A
D3
VCCA_DPHY1
DPHY1
—
—
D4
GND
GND
—
—
D5
VCCAUX25VPP
VCCAUX
—
—
D6
GND
GND
—
—
D7
VCCA_DPHY0
DPHY0
—
—
D8
PB16B
2
PCLKC2_0
Comp_OF_PB16A
D9
PB16A
2
PCLKT2_0
True_OF_PB16B
E1
PB38A
1
—
True_OF_PB38B
E2
PB38B
1
—
Comp_OF_PB38A
E3
VCC
VCC
—
—
E4
VCC
VCC
—
—
E5
GND
GND
—
—
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
43
CrossLink Family
Preliminary Data Sheet
csfBGA81 Pinout (Continued)
Pin Number
Pin Function
Bank
Dual Function
Differential
E6
VCCIO2
2
—
—
E7
PB12B
2
GPLLC2_0
Comp_OF_PB12A
E8
PB6B
2
—
Comp_OF_PB6A
E9
PB6A
2
GR_PCLK2_0
True_OF_PB6B
F1
PB50
0
MOSI
—
F2
PB48
0
PCLKT0_1/USER_SCL
—
F3
VCCIO1
1
—
—
F4
GND
GND
—
—
F5
GNDGPLL
GND
—
—
F6
VCCIO2
2
—
—
F7
PB12A
2
GPLLT2_0
True_OF_PB12B
F8
PB2B
2
—
Comp_OF_PB2A
F9
PB2A
2
—
True_OF_PB2B
G1
PB52
0
SPI_SS/CSN/SCL
—
G2
CRESET_B
0
CRESET_B
—
G3
VCCIO0
0
—
—
G4
VCCIO1
1
—
—
G5
VCCGPLL
VCCGPLL
—
—
G6
PB29B
1
PCLKC1_0
Comp_OF_PB29A
G7
PB29A
1
PCLKT1_0
True_OF_PB29B
G8
PB2D
2
MIPI_CLKC2_0
Comp_OF_PB2C
G9
PB2C
2
MIPI_CLKT2_0
True_OF_PB2D
H1
PB53
0
SPI_SCK/MCK/SDA
—
H2
CDONE
0
CDONE
—
H2
PB49
0
PMU_WKUPN
—
H3
PB43D
1
—
Comp_OF_PB43C
H4
PB38D
1
—
Comp_OF_PB38C
H5
PB34D
1
MIPI_CLKC1_0
Comp_OF_PB34C
H6
PB29D
1
PCLKC1_1
Comp_OF_PB29C
H7
PB16D
2
PCLKC2_1
Comp_OF_PB16C
H8
PB6D
2
—
Comp_OF_PB6C
H9
PB6C
2
—
True_OF_PB6D
J1
PB51
0
MISO
—
J2
PB47
0
PCLKT0_0/USER_SDA
—
J3
PB43C
1
—
True_OF_PB43D
J4
PB38C
1
—
True_OF_PB38D
J5
PB34C
1
MIPI_CLKT1_0
True_OF_PB34D
J6
PB29C
1
PCLKT1_1
True_OF_PB29D
J7
PB16C
2
PCLKT2_1
True_OF_PB16D
J8
PB12D
2
—
Comp_OF_PB12C
J9
PB12C
2
—
True_OF_PB12D
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
44
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
6.5. Dual Function Pin Descriptions
The following table describes the dual functions available to certain pins on the CrossLink device. These pins may
alternatively be used as general purpose I/O when the described dual function is not enabled.
Signal Name
I/O
Description
USER_SCL
I/O
User Slave I2C0 clock input and Master I C0 clock output. Enables PMU wakeup via I2C0.
USER_SDA
I/O
User Slave I2C0 data input and Master I C0 data output. Enables PMU wakeup
via I2C0.
PMU_WKUPN
—
This pin wakes the PMU from sleep mode when toggled low.
General Purpose
2
2
Clock Functions
GPLL2_0[T, C]_IN
I
General Purpose PLL (GPLL) input pads: T = true and C = complement. These
pins can be used to input a reference clock directly to the General Purpose
PLL. These pins do not provide direct access to the primary clock network
GR_PCLK[Bank]0
I
These pins provide a short General Routing path to the primary clock network.
Refer to TN1304, CrossLink sysCLOCK PLL/DLL Design and Usage Guide for
details.
PCLK[T/C][Bank]_[num]
I/O
MIPI_CLK[T/C][Bank]_0
I/O
General Purpose Primary CLK pads: [T/C] = True/Complement, [Bank] = (0, 1
and 2). These pins provide direct access to the primary and edge clock
networks.
MIPI D-PHY Reference CLK pads: [T/C] = True/Complement, [Bank] = (0, 1 and
2). These pins can be used to input a reference clock directly to the D-PHY
PLLs. These pins do not provide direct access to the primary clock network
Configuration
CDONE
I/O
Open Drain pin. Indicates that the configuration sequence is complete, and the
startup sequence is in progress. Holding CDONE delays configuration.
SPI_SCK
I
MCK
O
Input Configuration Clock for configuring CrossLink in Slave SPI mode (SSPI).
Output Configuration Clock for configuring CrossLink in Master SPI mode
(MSPI).
SPI_SS
I
Input Chip Select for configuring CrossLink in Slave SPI mode (SSPI).
CSN
O
MOSI
I/O
Output Chip Select for configuring CrossLink in Master SPI mode (MSPI).
Data Output when configuring CrossLink in Master SPI mode (MSPI), data
input when configuring CrossLink in Slave SPI mode (SSPI).
MISO
I/O
Data Input when configuring CrossLink in Master SPI mode (MSPI), data output
when configuring CrossLink in Slave SPI mode (SSPI).
SCL
I/O
Slave I C clock I/O when configuring CrossLink in I C mode
SDA
I/O
Slave I C data I/O when configuring CrossLink in I C mode
2
2
2
2
6.6. Dedicated Function Pin Descriptions
Signal Name
I/O
Description
Configuration
CRESET_B
I
Configuration Reset, active LOW.
MIPI D-PHY
DPHY[num]_CK[P/N]
I/O
MIPI D-PHY Clock [num] = D-PHY 0 or 1, P = Positive, N = Negative.
DPHY[num]_D[P/N][lane]
I/O
MIPI D-PHY Data [num] = D-PHY 0 or 1, P = Positive, N = Negative, Lane = data
lane in the D-PHY block 0, 1, 2 or 3.
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
45
CrossLink Family
Preliminary Data Sheet
6.7. Pin Information Summary
Pin Type
CrossLink
WLCSP36
ucfBGA64
ctfBGA80
csfBGA81
General Purpose I/O per Bank
Bank 0
7
6
7
7
Bank 1
0
10
14
14
Bank 2
10
12
16
16
Total General Purpose Single Ended IO
17
28
37
37
Bank 0
0
0
0
0
Bank 1
0
5
7
7
Bank 2
5
6
8
8
Total General Purpose Differential I/O pairs
5
11
15
15
D-PHY
1
2
2
2
D-PHY Clock/Data
10
20
20
20
D-PHY VCC
1
2
4
4
D-PHY GND
1
1
3
3
VCC/VCCIOx/VCCAUX2V5/VCCGPLL
4
8
9
10
GND
3
4
9
9
CRESETB
1
1
1
1
Total Balls
36
64
80
81
Differential I/O pairs per Bank
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
46
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
7. Package Information
7.1. 36-Ball WLCS Package
(4X)
aaa
PIN #1 ID
36 X
e
b
ddd M C A B
eee M C
D
D1
e
E
A
E1
B
Top View
Bottom View
A
ccc C
A1
C
Side View
Item
Min
A
A1
D
—
0.113
E
D1/E1
b
0.188
Typ
Max
Item
—
0.600
—
—
2.535 BSC
e
aaa
ccc
0.40 BSC
0.030
0.050
2.585 BSC
2.00 BSC
ddd
eee
0.050
0.015
0.218
Min
Typ
Max
0.248
Figure 7.1. 36-Ball WLCS Package Diagram
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
47
CrossLink Family
Preliminary Data Sheet
7.2. 64-Ball ucfBGA Package
(4X)
A
aaa
8
7
6
5
4
3
2
1
D
A1 CORNER
INDEX AREA
M
B
A
B
D
E
N
C
E
F
G
e
H
e
b
ddd M C A B
eee M C
4X
S
Top View
Bottom View
A
bbb C
ccc C
A1 A2
C
Side View
Item
A
A1
Min
—
0.11
Typ
—
—
Max
1.00
—
Item
e
aaa
A2
D/E
0.62
—
3.50 BSC
—
bbb
ccc
0.10
0.08
ddd
eee
0.15
0.08
M/N
S
b
0.20
2.80 BSC
0.20 BSC
0.25
Min
Typ
Max
0.40 BSC
0.10
0.30
Figure 7.2. 64-Ball ucfBGA Package Diagram
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
48
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
7.3. 80-Ball ctfBGA Package
(4X)
A
aaa
10 9 8 7 6 5 4 3 2 1
M
D
A1 CORNER
INDEX AREA
B
e
B
C
D
E
E
N
A
F
G
H
J
K
e
b
4X
S
ddd M C A B
eee M C
Bottom View
Top View
A2 A
bbb C
ccc C
A1
C
Side View
Item
A
A1
Min
—
0.11
Typ
—
—
Max
1.00
—
Item
e
aaa
Min
Typ
Max
0.65 BSC
0.10
A2
D/E
0.61
—
6.50 BSC
—
bbb
ccc
0.10
0.08
M/N
S
b
5.85 BSC
0.325 BSC
0.20
0.25
0.30
ddd
eee
0.15
0.05
Figure 7.3. 80-Ball ctfBGA Package Diagram
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
49
CrossLink Family
Preliminary Data Sheet
7.4. 81-Ball csfBGA Package
(4X)
A
aaa
9
8
7
6
5 4
M
3
1
2
D
A1 CORNER
INDEX AREA
B
A
B
D
E
E
N
C
F
G
H
J
e
e
b
4X
S
ddd M C A B
eee M C
Bottom View
Top View
A
bbb C
ccc C
A1
C
A2
Side View
Item
A
Min
—
Typ
—
Max
1.00
Item
e
A1
A2
0.11
0.64
—
—
—
—
aaa
bbb
0.10
0.10
ccc
ddd
eee
0.08
0.15
0.08
D/E
M/N
S
b
4.50 BSC
4.00 BSC
0.00 BSC
0.20
0.25
Min
Typ
Max
0.50 BSC
0.30
Figure 7.4. 81-Ball csfBGA Package Diagram
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
50
DS1055-1.0
CrossLink Family
Preliminary Data Sheet
8. CrossLink Part Number Description
LIF-MD XXXX-X XXXXX X
Device Family
CrossLink FPGA
Grade
I = Industrial
Logic Capacity
6000 = 6000 LUTs
Package
UWG36 = 36-ball WLCSP
UMG64 = 64-ball ucfBGA
MG81 = 81-ball csfBGA
JMG80 = 80-ball ctfBGA
Speed
6 = Fastest
8.1. Ordering Part Numbers
8.1.1. Industrial
Part Number
Grade
Package
Pins
Temp.
LUTs (K)
LIF-MD6000-6UWG36ITR
–6
Lead free WLCSP
36
Industrial
5.9
LIF-MD6000-6UMG64I
–6
Lead free ucfBGA
64
Industrial
5.9
LIF-MD6000-6MG81I
–6
Lead free csfBGA
81
Industrial
5.9
LIF-MD6000-6JMG80I
–6
Lead free ctfBGA
80
Industrial
5.9
Note: UWG36 package is available in shipments of 5000 pcs./reel (TR), 1000 pcs./reel (TR1K), and 50 pcs./reel (TR50 – for samples
only).
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
DS1055-1.0
51
CrossLink Family
Preliminary Data Sheet
References
For more information, refer to the following technical notes:
 TN1301, CrossLink High-Speed I/O Interface
 TN1302, CrossLink Hardware Checklist
 TN1303, CrossLink Programming and Configuration Usage Guide
 TN1304, CrossLink sysCLOCK PLL/DLL Design and Usage Guide
 TN1305, CrossLink sysI/O Usage Guide
 TN1306, CrossLink Memory Usage Guide
 TN1307, Power Management and Calculation for CrossLink Devices
 TN1308, CrossLink I2C Hardened IP Usage Guide
 TN1309, Advanced CrossLink I2C Hardened IP Reference Guide
For further information on interface standards refer to the following websites:
 JEDEC Standards (LVTTL, LVCMOS): www.jedec.org
 MIPI Standards (D-PHY): www.mipi.org
Technical Support
For assistance, submit a technical support case at www.latticesemi.com/techsupport.
Revision History
Date
Version
May 2016
1.0
Change Summary
First preliminary release.
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
52
DS1055-1.0
TH
th
7 Floor, 111 SW 5 Avenue
Portland, OR 97204, USA
T 503.268.8000
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