TrilithIC BTS 775 G Overview Features • • • • • • • • • • • • • • • • • Quad switch driver Free configurable as bridge or quad-switch Optimized for DC motor management applications Ultra low RDS ON @ 25 °C: High-side switch: typ.85 mΩ, P-DSO-28-9 Low-side switch: typ. 45 mΩ Very high peak current capability Very low quiescent current Space- and thermal optimized power P-DSO-Package Full short-circuit-protection Operates up to 40 V Status flag diagnosis Overtemperature shut down with hysteresis Short-circuit detection and diagnosis Open-load detection and diagnosis C-MOS compatible inputs Internal clamp diodes Isolated sources for external current sensing Over- and under-voltage detection with hysteresis Type Ordering Code Package BTS 775 G Q67007-A9350 P-DSO-28-9 Description The BTS 775 G is a TrilithIC contains one double high-side switch and two low-side switches in one P-DSO-28-9 -Package. “Silicon instead of heatsink” becomes true The ultra low RDS ON of this device avoids powerdissipation. It saves costs in mechanical construction and mounting and increases the efficiency. The high-side switches are produced in the SIEMENS SMART SIPMOS® technology. It is fully protected and contains the signal conditioning circuitry for diagnosis. (The comparable standard high-side product is the BTS 621L1.) Semiconductor Group 1 1999-01-07 BTS 775 G For minimized RDS ON the two low-side switches are N channel vertical power FETs in the SIEMENS SMART SIPMOS® technology. Fully protected by embedded protection functions. (The comparable standard product is the BSP 78). Each drain of these three chips is mounted on separated leadframes (see P-DSO-28-9 pin configuration). The sources of all four power transistors are connected to separate pins. So the BTS 775 G can be used in H-Bridge configuration as well as in any other switch configuration. Moreover, it is possible to add current sense resistors. All these features open a broad range of automotive and industrial applications. Semiconductor Group 2 1999-01-07 BTS 775 G DL1 1 28 DL1 GL1 2 27 SL1 DL1 3 N.C. 4 25 DL1 DHVS 5 24 DHVS GND 6 23 SH1 GH1 7 LS-Lead Frame 1 26 SL1 22 SH1 HS-Lead Frame ST 8 21 SH2 GH2 9 20 SH2 DHVS 10 19 DHVS N.C. 11 18 DL2 DL2 12 GL2 13 16 SL2 DL2 14 15 DL2 LS-Lead Frame 2 17 SL2 AEP02071 Figure 1 Pin Configuration (top view) Semiconductor Group 3 1999-01-07 BTS 775 G Pin Definitions and Functions Pin No. Symbol Function 1, 3, 25, 28 DL1 Drain of low-side switch1 Leadframe 1 1) 2 GL1 Gate of low-side switch1 4 N.C. not connected 5, 10, 19, 24 DHVS Drain of high-side switches and power supply voltage Leadframe 2 1) 6 GND Ground 7 GH1 Gate of high-side switch1 8 ST Status of high-side switches; open Drain output 9 GH2 Gate of high-side switch2 11 N.C. not connected 12, 14, 15, 18 DL2 Drain of low-side switch2 Leadframe 3 1) 13 GL2 Gate of low-side switch2 16, 17 SL2 Source of low-side switch2 20, 21 SH2 Source of high-side switch2 22, 23 SH1 Source of high-side switch1 26, 27 SL1 Source of low-side switch1 1) To reduce the thermal resistance these pins are direct connected via metal bridges to the leadframe. Bold type: Pin needs power wiring Semiconductor Group 4 1999-01-07 BTS 775 G DHVS 5, 10, 19, 24 ST 8 Diagnosis GH1 GH2 7 9 Biasing and Protection Driver IN OUT 0 0 L L 0 1 L H 1 0 H L 1 1 H H R O1 R O2 20, 21 12, 14, 15, 18 GND 22, 23 6 1, 3, 25, 28 Protection GL1 2 SH2 DL2 SH1 DL1 Gate Driver Protection GL2 13 Gate Driver 26, 27 SL1 16, 17 SL2 AEB02676 Figure 2 Block Diagram Semiconductor Group 5 1999-01-07 BTS 775 G Circuit Description Input Circuit The control inputs GH1,2 consist of TTL/CMOS compatible Schmitt-Triggers with hysteresis. Buffer amplifiers are driven by these stages and convert the logic signal into the necessary form for driving the power output stages. The inputs GL1 and GL2 are connected to the internal gate-driving units of the fully protected N-channel vertical power-MOS-FETs. Output Stages The output stages consist of an ultra low RDS ON Power-MOS H-Bridge. Embedded protective circuits make the outputs short circuit proof to ground, to the supply voltage and load short circuit proof. Positive and negative voltage spikes, which occur when driving inductive loads, are limited by integrated power clamp diodes. Short Circuit Protection The outputs are protected against – output short circuit to ground – output short circuit to the supply voltage, and – overload (load short circuit). An internal OP-Amp controls the Drain-Source-Voltage by comparing the DS-VoltageDrop with an internal reference voltage. Above this trippoint the OP-Amp reduces the output current depending on the junction temperature and the drop voltage. In the case of overloaded high-side switches the status output is set to low. If the HS-Switches are in OFF-state-Condition internal resistors RO1,2 from SH1,2 to GND pull the voltage at SH1,2 to low values. On each output pin SH1 and SH2 an output examiner circuit compares the output voltages with the internal reference voltage VEO. This results in switching the status output to low. The fully protected low-side switches have no status output. Overtemperature Protection The highside and the lowside switch also incorporates an overtemperature protection circuit with hysteresis which switches off the output transistors and sets the status output to low. Undervoltage-Lockout (UVLO) When VS reaches the switch-on voltage VUVON the IC becomes active with a hysteresis. The High-Side output transistors are switched off if the supply voltage VS drops below the switch off value VUVOFF. Semiconductor Group 6 1999-01-07 BTS 775 G Overvoltage-Lockout (OVLO) When VS reaches the switch-off voltage VOVOFF the High-Side output transistors are switched off with a hysteresis. The IC becomes active if the supply voltage VS drops below the switch-on value VOVON. Open Load Detection Open load is detected by current measurement. If the output current drops below an internal fixed level the error flag is set with a delay. Status Flag Various errors as listed in the table “Diagnosis” are detected by switching the open drain output ST to low. Semiconductor Group 7 1999-01-07 BTS 775 G Truthtable and Diagnosis (valid only for the High-Side-Switches) Flag GH1 GH2 SH1 Inputs Normal operation; identical with functional truth table Open load at high-side switch1 Open load at high-side switch2 Short circuit to DHVS at high-side switch1 Short circuit to DHVS at high-side switch2 Overtemperature high-side switch1 Overtemperature high-side switch2 Overtemperature both high-side switch Over- and Under-Voltage SH2 ST Remarks Outputs 0 0 1 1 0 1 0 1 L L H H L H L H 1 1 1 1 0 0 1 0 1 X 0 1 X 0 0 1 Z Z H L H X L H X Z Z H 1 1 0 1 1 0 0 0 1 0 1 X 0 1 X 0 0 1 H H H L H X L H X H H H 0 1 1 0 1 1 0 1 X X L L X X 1 0 detected X X 0 1 X X L L 1 0 detected 0 X 1 0 1 X L L L L L L 1 0 0 detected detected X X L L 1 not detected Inputs: Outputs: Status: 0 = Logic LOW Z = Output in tristate condition 1 = No error 1 = Logic HIGH L = Output in sink condition 0 = Error X = don’t care H = Output in source condition stand-by mode switch2 active switch1 active both switches active detected detected detected detected X = Voltage level undefined Semiconductor Group 8 1999-01-07 BTS 775 G Electrical Characteristics Absolute Maximum Ratings – 40 °C < Tj < 150 °C Parameter Symbol Limit Values min. Unit Remarks max. High-Side-Switches (Pins DHVS, GH1,2 and SH1,2) Supply voltage HS-drain current HS-input current HS-input voltage VS IDHS IGH VGH – 0.3 43 V – – 10 * A * internally limited –2 2 mA Pin GH1 and GH2 – 10 16 V Pin GH1 and GH2 IST –5 5 mA Pin ST Status Output ST Status Output current Low-Side-Switches (Pins DL1,2, GL1,2 and SL1,2) Break-down voltage LS-drain current LS-input voltage V(BR)DSS IDLS VGL 40 – V VGS = 0 V; ID <= 1 mA 16 * A * internally limited – 0.3 10 V Pin GL1 and GL2 Tj Tstg – 40 150 °C – – 50 150 °C – – 20 K/W measured to pin3 or 12 – 20 K/W measured to pin19 – 60 K/W – Temperatures Junction temperature Storage temperature Thermal Resistances (one HS-LS-Path active) LS-junction case HS-junction case Junction ambient RthjCLS RthjCHS Rthja Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Semiconductor Group 9 1999-01-07 BTS 775 G Operating Range Parameter Symbol Limit Values min. Unit Remarks max. Supply voltage VS VUVOFF 36 V After VS rising above VUVON Input voltages VGH VGL IST TjHS TjLS – 0.3 15 V – – 0.3 10 V – 0 2 mA – – 40 150 °C – – 40 150 °C – Input voltages Output current HS-junction temperature LS-junction temperature Note: In the operating range the functions given in the circuit description are fulfilled. Semiconductor Group 10 1999-01-07 BTS 775 G Electrical Characteristics ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 °C < Tj < 150 °C; 8 V > VS > 18 V unless otherwise specified Parameter Symbol Limit Values min. typ. max. – 16 30 Unit Test Condition Current Consumption Quiescent current IS µA GH1 = GH2 = L VS = 13.2 V Tj = 25 °C Quiescent current IS – – 35 µA GH1 = GH2 = L VS = 13.2 V Supply current IS IS – 2 3.5 mA GH1 or GH2 = H – 4 7 mA GH1 and GH2 = H – 5.4 7 V 3.5 4.2 – V – 1.2 – V VS increasing VS decreasing VUVON – VUVOFF 36 37.8 43 V 35 37.1 – V – 0.7 – V 11 18 25 A 9 14 22 A 5 8 14 A Supply current Under Voltage Lockout (UVLO) VUVON Switch-OFF voltage VUVOFF Switch ON/OFF hysteresis VUVHY Switch-ON voltage Over Voltage Lockout (OVLO) VOVOFF Switch-ON voltage VOVON Switch OFF/ON hysteresis VOVHY Switch-OFF voltage VS increasing VS decreasing VOVOFF – VOVON Short Circuit of Highside Switch to GND Initial peak SC current Initial peak SC current Initial peak SC current Semiconductor Group ISCP ISCP ISCP 11 Tj = – 40 °C Tj = 25 °C Tj = 150 °C 1999-01-07 BTS 775 G Electrical Characteristics (cont’d) ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 °C < Tj < 150 °C; 8 V > VS > 18 V unless otherwise specified Parameter Symbol Limit Values min. typ. max. Unit Test Condition Short Circuit of Highside Switch to VS OFF-state examiner-voltage VEO 2 3 4 V VGH = 0 V Output pull-down-resistor RO 4 10 30 kΩ – 10 130 400 mA – Open Circuit Detection of Highside Switch Detection current IOCD Switching Times of Highside Switch Switch-ON-time; to 90% VSH tON – 0.2 0.4 ms resistive load ISH = 1 A; VS = 12 V Switch-OFF-time; to 10% VSH tOFF – 0.2 0.4 ms resistive load ISH = 1 A; VS = 12 V Note: switching times are guaranteed by design Control Inputs of Highside Switches GH 1, 2 H-input voltage L-input voltage Input voltage hysterese H-input current L-input current Input series resistance Zener limit voltage Semiconductor Group VGHH VGHL VGHHY IGHH IGHL RI VGHZ – 2.8 3.5 V – 1.5 2.3 – V – – 0.5 – V – 20 60 90 µA 1 25 50 µA VGH = 5 V VGH = 0.4 V 2.5 3.5 6 kΩ – 5.4 – – V IGH = 1.6 mA 12 1999-01-07 BTS 775 G Electrical Characteristics (cont’d) ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 °C < Tj < 150 °C; 8 V > VS > 18 V unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max. 0.9 1.7 2.2 V – 10 30 µA Control Inputs GL1, 2 Gate-threshold-voltage Input current VGL(th) IGLN IDL = 2 mA VGL = 5 V; normal operation Input current IGLF – 150 300 µA VGL = 5 V; failure mode Short Circuit of Lowside Switch to VS Initial peak SC current ISCP 18 26 34 A 15 21 27 A 10 14 18 A Tj = – 40 °C Tj = 25 °C Tj = 150 °C Switching Times of Lowside Switch Switch-ON-time; to 90% VSL tON – 100 200 µs resistive load ISH = 1 A; VS = 12 V Switch-OFF-time; to 10% VSL tOFF – 50 200 µs resistive load ISH = 1 A; VS = 12 V IST = 1.6 mA VST = 5 V IST = 1.6 mA Note: Switching times are guaranteed by design. Status Flag Output ST of Highside Switch Low output voltage Leakage current Zener-limit-voltage Semiconductor Group VSTL ISTLK VSTZ – 0.25 0.6 V – 0.5 10 µA 5.4 – – V 13 1999-01-07 BTS 775 G Electrical Characteristics (cont’d) ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 °C < Tj < 150 °C; 8 V > VS > 18 V unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max. Thermal shutdown junction TjSD temperature 155 – 190 °C – Thermal switch-on junction TjSO temperature 150 – 180 °C – ∆T – 10 – °C ∆T = TjSD – TjSO IHLK – 5 12 µA VGH = VSH = 0 V Leakage current of lowside ILKL switch – 1.3 10 µA Clamp-diode of highside switch; forward-Voltage VFH – 0.8 1.5 V VGL = 0 V VDS = 13 V IFH = 3 A Clamp-diode leakagecurrent of highside switch ILKCL – 2 10 mA IFH = 3 A Clamp-diode of lowside switch; forward-voltage VFL – 0.8 1.2 V IFL = 3 A Static drain-source on-resistance of highside switch RDS ON H – 85 110 mΩ ISH = 1 A Tj = 25 °C Static drain-source on-resistance of lowside switch RDS ON L – 45 60 mΩ ISL = 1 A; VGL = 5 V Tj = 25 °C Static path on-resistance RDS ON – – 320 mΩ RDS ON H + RDS ON L ISH = 1 A; Thermal Shutdown Temperature hysteresis Output Stages Leakage current of highside switch Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and the given supply voltage. Semiconductor Group 14 1999-01-07 BTS 775 G ΙS VS = 12 V CS 470 nF Ι FH1, 2 DHVS 5, 10, 19, 24 ST 8 Diagnosis GH2 9 VGH1 VDSH2 - VFL2 Biasing and Protection Driver IN OUT 0 0 L L 0 1 L H 1 0 H L 1 1 H H GH1 7 VST VSTL VSTZ R O1 VDSH1 - VFL1 20 SH2 Ι SH2 21 R O2 12, 14, 15, 18 DL2 Ι DL2 Ι LKL VGH2 GND 6 Ι GND Ι LKCL1, 2 VUVON VUVOFF VOVON VOVOFF 22, 23 SH1 Ι SH1 1, 3, DL1 Ι DL1 25, 28 Ι LKL Protection Gate Driver GL1 2 Protection VGL1 VGL(th)1 CL 100 µF VEO1 VDSL1 - VFL1 Gate Driver GL2 13 VGL2 VGL(th)2 26, 27 SL1 Ι SL1 VEO2 VDSL2 - VFL2 16, 17 SL2 Ι SL2 AES02677 Figure 3 Test Circuit HS-Source-Current Named during Short Circuit Named during Open Circuit Named during Leakage-Cond. ISH1,2 IOCD IHSLK Semiconductor Group ISCP 15 1999-01-07 BTS 775 G Watchdog Reset Q RQ 100 k Ω R VCC WD RS CQ 22 µF TLE 4278G D CD 47 nF I VS = 12 V DO1 1N4001 GND CS 10 µF DO1 Z39 DHVS 5, 10, 19, 24 ST 8 10 k Ω Diagnosis GH1 7 GH2 9 µP Driver IN OUT 0 0 L L 0 1 L H 1 0 H L 1 1 H H Biasing and Protection R O1 R O2 20 SH2 21 12, 14, 15, 18 DL2 22, 23 SH1 M GND 6 1, 3, DL1 25, 28 Protection GL1 2 Gate Driver Protection Gate Driver GL2 13 26, 27 SL1 GND Figure 4 16, 17 SL2 AES02678 Application Circuit Semiconductor Group 16 1999-01-07 BTS 775 G Package Outlines 0.35 x 45˚ 7.6 -0.2 1) 0.23 +0.0 9 8˚ ma x 2.65 max 2.45 -0.2 0.2 -0.1 P-DSO-28-9 (Plastic Dual Small Outline Package) 0.4 +0.8 1.27 0.35 +0.15 2) 0.1 0.2 28x 28 1 10.3 ±0.3 15 18.1 -0.4 1) 14 Index Marking 1) Does not include plastic or metal protrusions of 0.15 max rer side 2) Does not include dambar protrusion of 0.05 max per side Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 17 GPS05123 Dimensions in mm 1999-01-07