1 M × 1-Bit Dynamic RAM Low Power 1 M × 1-Bit Dynamic RAM HYB 511000BJ-50/-60/-70 HYB 511000BJL-50/-60/-70 Advanced Information 1 048 576 words by 1-bit organization Fast access and cycle time 50 ns access time 95 ns cycle time (-50 version) 60 ns access time 130 ns cycle time (-60 version) 70 ns access time 130 ns cycle time (-70 version) • Fast page mode cycle time 35 ns (-50 version) 40 ns (-60 version) 45 ns (-70 version) • Low power dissipation max. 495 mW active (-50 version) max. 440 mW active (-60 version) max. 385 mW active (-70 version) max. 5.5 mW standby max. 1.1 mW standby for L-version • • • • • • • • • Single + 5 V (± 10 %) supply with a built-in VBB generator Output unlatched at cycle end allows twodimensional chip selection Common I/O capability using “early write” operation Read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden-refresh, fast page mode capability and test mode capability All inputs, outputs and clocks TTL-compatible 512 refresh cycles/8 ms 512 refresh cycles/64 ms for L-version only Plastic Packages: P-SOJ-26/20-1 Ordering Information Type Ordering Code Package Description HYB 511000BJ-50 Q67100-Q1056 P-SOJ-26/20-1 DRAM (access time 50 ns) HYB 511000BJ-60 Q67100-Q518 P-SOJ-26/20-1 DRAM (access time 60 ns) HYB 511000BJ-70 Q67100-Q519 P-SOJ-26/20-1 DRAM (access time 70 ns) HYB 511000BJL-50 on request P-SOJ-26/20-1 DRAM (access time 50 ns) HYB 511000BJL-60 Q67100-Q526 P-SOJ-26/20-1 DRAM (access time 60 ns) HYB 511000BJL-70 Q67100-Q527 P-SOJ-26/20-1 DRAM (access time 70 ns) Semiconductor Group 33 01.95 HYB 511000BJ/BJL-50/-60/-70 1 M × 1-DRAM The HYB 511000BJ/BJL is the new generation dynamic RAM organized as 1 048 576 words by 1-bit. The HYB 511000BJ/BJL utilizes CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 511000BJ/BJL to be packaged in a standard plastic P-SOJ-26/20. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include single + 5 V (± 10 %) power supply, direct interfacing with high-performance logic device families such as Schottky TTL. “Test Mode” function is implemented. The HYB 511000BJL are specially selected for low power battery backup applications. Pin Definitions and Functions Pin No. Function A0-A9 Address Inputs RAS Row Address Strobe DI Data In DO Data Out CAS Column Address Strobe WE Read/Write Input VCC Power Supply (+ 5 V) VSS Ground (0 V) TF Test Function N.C. No Connection Semiconductor Group 34 HYB 511000BJ/BJL-50/-60/-70 1 M × 1-DRAM Pin Configuration (top view) SOJ-26/20-1 Semiconductor Group 35 HYB 511000BJ/BJL-50/-60/-70 1 M × 1-DRAM Block Diagram Semiconductor Group 36 HYB 511000BJ/BJL-50/-60/-70 1 M × 1-DRAM Absolute Maximum Ratings Operating temperature range .........................................................................................0 to + 70 ˚C Storage temperature range......................................................................................– 55 to + 150 ˚C Soldering temperature ............................................................................................................260 ˚C Soldering time .............................................................................................................................10 s Input/output voltage ........................................................................................................ – 1 to + 7 V Test Function Input voltage ....................................................................................... – 1 to + 10.5 V Power supply voltage...................................................................................................... – 1 to + 7 V Power dissipation..................................................................................................................... 0.6 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 ˚C; VSS = 0 V; VCC = 5 V ± 10 % Parameter Symbol Limit Values min. max. Unit Test Condition Input high voltage VIH 2.4 6.5 V 1) Input low voltage VIL – 1.0 0.8 V 1) Test enable input high voltage VIH(TF) VCC + 4.5 10.5 V 1) Test disable input low voltage VIL(TF) – 1.0 VCC + 1.0 V 1) Output high voltage (IOUT = – 5 mA) VOH 2.4 – V 1) Output low voltage (IOUT = 4.2 mA) VOL – 0.4 V 1) Input leakage current, any input except TF (0 V ≤ VIN ≤ 6.5 V, all other pins = 0 V) II(L) – 10 10 µA 1) Output leakage current (DO is disabled, 0 V ≤ VOUT ≤ 5.5 V) IO(L) – 10 10 µA 1) Average VCC supply current: -50 version -60 version -70 version (RAS, CAS, address cycling: tRC = tRC min.) ICC1 – – – 90 80 70 mA mA mA 2) 3) – 2 mA – Standby VCC supply current (RAS = CAS = VIH) ICC2 Semiconductor Group 37 2) 3) 2) 3) HYB 511000BJ/BJL-50/-60/-70 1 M × 1-DRAM DC Characteristics (cont’d) TA = 0 to 70 ˚C; VSS = 0 V; VCC = 5 V ± 10 % Parameter min. max. Unit Test Condition – – – 90 80 70 mA mA mA 2) – – – 70 60 50 mA mA mA 2) 3) – – 1 200 mA µA 1) – – – 90 80 70 mA mA mA 2) ICC7 – 300 µA 2) Input leakage current (only TF) (0 V ≤ VIN (TF) ≤ VCC + 0.5 V) All other pins not under test = 0 V IITF(L) – 10 + 10 µA 1) Test function input current (VCC + 4.5 ≤ VIN (TF) ≤ 10.5 V) ITF – 1 mA 1) Average VCC supply current during RAS only refresh cycles: -50 version -60 version -70 version Symbol Limit Values ICC3 2) 2) (RAS cycling: CAS = VIH : tRC = tRC min.) Average VCC supply current during fast page modes: -50 version -60 version -70 version (RAS = VIL , CAS, address cycling: tPC = tPC min.) ICC4 Standby VCC supply current L-Version (RAS = CAS = VCC – 0.2 V) ICC5 Average VCC supply current during CAS-before-RAS refresh mode: -50 version -60 version -70 version (RAS, CAS, address cycling: tRC = tRC min.) ICC6 For L-version only: Battery backup current: average power supply current, battery backup mode: (CAS = CAS before RAS cycling or 0.2 V, WE = VCC – 0.2 V or 0.2 V, A0 to A9 = VCC – 0.2 V or 0.2 V, DI = VCC – 0.2 V or 0.2 V open, tRC = 125 µs, tRAS = tRAS min. ~ 1 µs) Semiconductor Group 38 2) 3) 2) 3) 1) 2) 2) HYB 511000BJ/BJL-50/-60/-70 1 M × 1-DRAM AC Characteristics 4) 13) TA = 0 to 70 ˚C; VCC = 5 V ± 10 %; tT = 5 ns Parameter Symbol Limit Values -50 Unit -60 -70 min. max. min. max. min. max. Random read or write cycle time tRC 95 – 110 – 130 – ns Read-write cycle time tRWC 115 – 130 – 155 – ns Fast page mode cycle time tPC 35 – 40 – 45 – ns Fast page mode readwrite cycle time tPRWC 55 – 60 – 70 – ns Access time from RAS tRAC – 50 – 60 – 70 ns 6) 11) Access time from CAS tCAC – 15 – 15 – 20 ns 6) 11) Access time from column tAA 6) 12) address – 25 – 30 – 35 ns tCPA Access time from CAS 6) precharge – 30 – 35 – 40 ns CAS to output in low-Z 6) tCLZ 0 – 0 – 0 – ns tOFF 0 15 0 20 0 20 ns tT 3 50 3 50 3 50 ns RAS precharge time tRP 35 – 40 – 50 – ns RAS pulse width tRAS 50 10.000 60 10.000 70 10.000 ns RAS pulse width (fast page mode) tRASP 50 100.000 60 100.000 70 100.000 ns RAS hold time tRSH 15 – 15 – 20 – ns CAS hold time tCSH 50 – 60 – 70 – ns RAS hold time from CAS precharge (FPM) tRHCP 30 – 35 – 45 – ns CAS precharge to WE delay time (FPM RMW) tCPWD 30 – 35 – 45 – ns CAS pulse width tCAS 15 10.000 15 10.000 20 10.000 ns tRCD 20 35 20 45 20 50 ns Output buffer turn-off delay 7) Transition time (rise and fall) 5) RAS to CAS delay time Semiconductor Group 11) 39 HYB 511000BJ/BJL-50/-60/-70 1 M × 1-DRAM AC Characteristics (cont’d) 4) 13) TA = 0 to 70 ˚C; VCC = 5 V ± 10 %; tT = 5 ns Parameter Symbol Limit Values -50 RAS to column address tRAD 12) delay time tCRP CAS to RAS precharge time CAS precharge time (fast tCP page mode) Unit -60 -70 min. max. min. max. min. max. 15 25 15 30 15 35 ns 5 – 5 – 5 – ns 10 – 10 – 10 – ns Row address setup time tASR 0 – 0 – 0 – ns Row address hold time tRAH 10 – 10 – 10 – ns Column address setup time tASC 0 – 0 – 0 – ns Column address hold time tCAH 15 – 15 – 15 – ns Column address to RAS lead time tRAL 25 – 30 – 35 – ns Read command setup time tRCS 0 – 0 – 0 – ns tRCH 0 – 0 – 0 – ns Read command hold time tRRH 8) referenced to RAS 0 – 0 – 0 – ns Write command hold time tWCH 10 – 10 – 15 – ns Read command hold time 8) Write command pulse width tWP 10 – 10 – 15 – ns Write command to RAS lead time tRWL 15 – 15 – 20 – ns Write command to CAS lead time tCWL 15 – 15 – 20 – ns Data setup time 9) tDS 0 – 0 – 0 – ns Data hold time 9) tDH 10 – 15 – 15 – ns Refresh period tREF – 8 – 8 – 8 ms Refresh period for L-version only tREF – 64 – 64 – 64 ms Semiconductor Group 40 HYB 511000BJ/BJL-50/-60/-70 1 M × 1-DRAM AC Characteristics (cont’d) 4) 13) TA = 0 to 70 ˚C; VCC = 5 V ± 10 %; tT = 5 ns Parameter Symbol Limit Values -50 Unit -60 -70 min. max. min. max. min. max. 0 – 0 – 0 – ns tCWD 15 – 15 – 20 – ns RAS to WE delay time 10) tRWD 50 – 60 – 70 – ns Column address to WE tAWD 10) delay time 25 – 30 – 35 – ns Write command setup tWCS 10) time CAS to WE delay time 10) CAS setup time (CASbefore-RAS cycle) tCSR 5 – 5 – 5 – ns CAS hold time (CASbefore-RAS cycle) tCHR 10 – 15 – 15 – ns RAS to CAS precharge time tRPC 0 – 0 – 0 – ns CAS precharge time (CAS-before-RAS counter test cycle) tCPT 25 – 30 – 40 – ns Test mode enable setup time referenced to RAS tTES 0 – 0 – 0 – ns Test mode enable hold time referenced to RAS tTEHR 0 – 0 – 0 – ns Test mode enable hold time referenced to CAS tTEHC 0 – 0 – 0 – ns Capacitance TA = 0 to 70 ˚C; VCC = 5 V ± 10 %; f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A9, DI) CI1 – 5 pF Input capacitance (RAS, CAS, WE, TF) CI2 – 7 pF Output capacitance (DO) CO – 7 pF Semiconductor Group 41 HYB 511000BJ/BJL-50/-60/-70 1 M × 1-DRAM Notes : 1) All voltages are referenced to VSS . 2) ICC1 , ICC3 , ICC4, ICC6, ICC7 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 5) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL . 6) Measured with a load equivalent to 2 TTL loads and 100 pF. 7) tOFF (max.) defines the time at which the output achieves the open-circuit conditions and is not referenced to output voltage levels. 8) Either tRCH or tRRH must be satisfied for a read cycle. 9) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 10) tWCS , tRWD , tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD ≥ tRWD (min.), tCWD ≥ tCWD (min.) and tAWD ≥ tAWD (min.), the cycle is a read-write cycle and DO will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of DO (at access time) is indeterminate. 11) Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC . 12) Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA . 13) AC measurements assume tT = 5ns. Semiconductor Group 42 HYB 511000BJ/BJL-50/-60/-70 1 M × 1-DRAM Waveforms tRC tRAS RAS tRP V IH VIL tCSH V IH CAS VIL tRAD tASR A0 - A9 V IH VIL tASC tRAL tCAH tASR Column Address Row Address Row Address tRCH tRAH tRCS WE tRRH V IH VIL tAA tCAC tOFF tCLZ V OH DO (Output) V OL Hi Z Valid Data Out tRAC “H” or “L” Read Cycle Semiconductor Group tCRP tRSH tCAS tRCD 43 Hi Z HYB 511000BJ/BJL-50/-60/-70 1 M × 1-DRAM tRC tRAS RAS V IH VIL tCSH tRCD tRSH tCAS V IH CAS VIL tRAD tASR A0 - A9 V IH VIL tWCS VIL DO (Output) tCWL tWCH tRWL tDH V IH Valid Data In VIL V OH Hi Z VOL “H” or “L” Write Cycle (Early Write) Semiconductor Group 44 . Row Address t WP V IH tDS DI (Input) tASR Column Address Row Address tCRP tRAL tCAH tASC tRAH WE tRP HYB 511000BJ/BJL-50/-60/-70 1 M × 1-DRAM tRWC tRAS tRP RAS tCSH tRSH tCAS tRCD CAS V IH tCRP VIL tRAH V IH tASR A0 - A9 V IL tCAH tASR tASC Column Address Row Address Row Address tAWD tRAD tCWD tRWD tCWL tRWL tWP V IH WE VIL tAA tDS tRCS DI (Input) tDH V IH Valid Data in VIL tCLZ tCAC tOFF V OH DO (Output) VOL Data Out tRAC “H” or “L” Read-Write (Read-Modify-Write) Cycle Semiconductor Group 45 Semiconductor Group Fast Page Mode Read-Modify-Write Cycle 46 IH IH IH IH V V IL V V IL V V IL V V IL OL DO (Output) V V OH IH DI (Input) V IL WE A0-A9 CAS RAS V tASR tCAH tCAS tCAC tAWD tAA tCLZ tRWD tCWD Column Address tASC tRAC tRCS “H” or “L” Row Address tRAD tRAH tRCD tCSH Data Out tDS tDH Data In tWP tOFF tAWD tCLZ tCAC tAA tCPA tCWL tWP Data Out tDS tDH Data In tCAS tCPWD tCWD tCAH Column Address tASC tCP tPRWC tRASP tOFF tAWD tCPWD tCWD tCLZ tAA tCPA tCWL Column Address tASC tCAH tDH Data Out tDS tOFF tRWL tCWL tWP Data In tRAL tCAS tRSH tCRP Row Address tASR tRP HYB 511000BJ/BJL-50/-60/-70 1 M × 1-DRAM HYB 511000BJ/BJL-50/-60/-70 1 M × 1-DRAM tRASP tRP V IH RAS VIL tCP tCAS V IH CAS VIL tASR A0-A9 VIL tCAS tCAS tCRP tCSH tRAH V IH tRHCP tRSH tPC tRCD tCAH tASC Row Addr tASC Column Address tCAH tCAH tASR tASC Column Address Column Address tRAD Row Address tRCH tRCH tRCS tRCS tRCS tCPA tAA tCPA tAA V IH WE VIL tAA tCAC tCAC tRAC tOFF tCLZ V OH DO (Output) V OL “H” or “L” Fast Page Mode Read Cycle Semiconductor Group tCAC tOFF tCLZ Valid Data Out 47 tRRH tOFF tCLZ Valid Data Out Valid Data Out HYB 511000BJ/BJL-50/-60/-70 1 M × 1-DRAM tRASP tRP V IH RAS VIL tPC tCAS tRCD VIL tRAL tRAH tCAH tASC tASR A0-A9 V IH VIL Row Addr Column Address tASC tCAH Column Address tWCS tWCH tWP V IH tCAH Column Address tCWL tRWL tWCS tWCH tWP tWCH tWP tDH tDH VIL tDH tDS DI (Input) tASC tCWL tWCS tCWL tRAD WE tCRP tCP V IH CAS tRSH tCAS tCAS V IH VIL Valid Data In tDS Valid Data In DO V (Output) OH V Valid Data In HI-Z OL “H” or “L” Fast Page Mode Early Write Cycle Semiconductor Group tDS 48 tASR Row Address HYB 511000BJ/BJL-50/-60/-70 1 M × 1-DRAM tRC tRAS RAS tRP V IH VIL tCRP tRPC V IH CAS VIL tRAH tASR tASR A0-A9 V IH Row Address VIL Row Address V OH DO (Output) V OL HI-Z “H” or “L” RAS-Only Refresh Cycle Semiconductor Group 49 HYB 511000BJ/BJL-50/-60/-70 1 M × 1-DRAM tRC tRP RAS tRP tRAS V IH VIL tCRP tRPC tCSR CAS V IH VIL tRPC tCHR tCP tWRP tWRH WE V IH VIL V OH DO (Output) VOL HI-Z tOFF “H” or “L” CAS-Before-RAS Refresh Cycle Semiconductor Group 50 HYB 511000BJ/BJL-50/-60/-70 1 M × 1-DRAM tRC tRC RAS tRP tRAS V IH tRP tRAS VIL tRCD tRSH tCRP tCHR CAS V IH tRAD VIL tRAH tASC tASR A0-A9 V IH VIL tWRP Column Address Row Addr Row Address tRRH tRCS WE tASR tWRH tCAH V IH VIL tAA tOFF tCAC tCLZ tRAC V OH DO (Output) V OL Valid Data Out “H” or “L” Hidden Refresh Cycle (Read) Semiconductor Group 51 HI-Z HYB 511000BJ/BJL-50/-60/-70 1 M × 1-DRAM tRC tRC tRP RAS tRAS V IH WE tRSH VIL tCRP tRAD tRAH tASC tCAH V IH VIL Row Addr tASR Row Address Column Address tWCS tWCH tWP V IH VIL tDS DI (Input) tCHR V IH tASR A0-A9 tRP VIL tRCD CAS tRAS V IH tDH Valid Data V IL V OH DO (Output) V OL HI-Z “H” or “L” Hidden Refresh Cycle (Early Write) Semiconductor Group 52 HYB 511000BJ/BJL-50/-60/-70 1 M × 1-DRAM RAS V IH IL tCHR tCSR V CAS V V Read Cycle WE IL tASR Row Address Column Address IL V tRAL tCAH tASC IH tWRP V tRSH tCAS tCPT IH V A0-A9 tRP tRAS V tAA tCAC tRCS tWRH tRRH tRCH IH IL tOFF tCLZ DO (Output) V OH VOL Write Cycle tRWL tCWL tWRH V WE Valid Data Out tWCS tWRP V IH tWCH IL tDS DI (Input) DO (Output) V V IH V Read-Modify-Write Cycle V WE Valid Data In IL IH V IL V tDH tWRP HI-Z tRCS tWRH tCWL tRWL tAWD tCWD tWP tCAC IH IL tAA tDS tDH DI (Input) DO (Output) V V IH Data In IL V OH VOL Valid Data Out HI-Z HI-Z “H” or “L” CAS-Before-RAS Refresh Counter Test Cycle Semiconductor Group tOFF tCAC t CLZ 53 HYB 511000BJ/BJL-50/-60/-70 1 M × 1-DRAM Test Mode The HYB 511000B/BL is the RAM organized 1 048 576 words by 1-bit, it is internally organized 262 144 words by 4-bit. In “Test Mode”, data would be written into a number of sectors (4 sectors) in parallel and retrieved the same way. If upon reading, all bits are equal (all “H” or “L”), the data output pin indicates a same data as all bits. In this case, the data output pin indicates an expected data for good parts, the data output pin indicates a complementary data for bad parts. And also, if any of the bits differed, the data output pin would indicate a high impedance state for bad parts. The next figure shows the block diagram including its truth table when “Test Mode” is used. In test mode, 1M DRAM can be tested as if it were 256K DRAM by the following method. “Test Mode” function is performed on any of the timing cycles including fast page mode when “TF” pin is held on “super voltage (VCC + 4.5 V (VCC = 5 V ± 10 %), max. voltage = 10.5 V)” for the specified period (tTES , tTEHR and tTEHC ; see next figure). The address input of A9 is ignored in the “Test Mode”. On the other hand, normal operation requires the “TF” pin be connected to VIL(TF) level, or left unconnected on the printed wiring board. The “Test Mode” function reduces test times (1/4; in case of using N test pattern). RAS V IH VIL tTEHC CAS V IH VIL tTES TF tTEHR V IH,TF VIL,TF Test Mode Cycle Semiconductor Group 54