2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) with On-chip Noise Reduction Filter SDA 9254-2 Preliminary Data CMOS IC Features ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● Stores a complete video field (4:1:1) On chip adaptive recursive noise reduction filter (4:1:1) 4 noise reduction classes selectable Special noise reduction mode for 4:2:2 applications 212 × 64 × 16 × 12-bit organization Triple port architecture One 16 × 12-bit input shift register Two 16 × 12-bit output shift registers Shift registers independently and simultaneously accessible (one output shift register is used internally for noise reduction filtering) Continuous data flow even at maximum speed 40-MHz shift rate - 0.96-Gbit/s total data rate All inputs and outputs TTL-compatible Tristate outputs Random access of groups of 16 × 12 bits for a wide range of applications Refresh-free operation possible 5 V ± 10 % power supply 0 … 70 °C operating temperature range Low power dissipation: 700 mW active, 28 mW standby Suitable for all common TV standards Allows flicker and noise reduction simultaneously with only one field memory Applications: TV, VCR, image processing, video printers, data compressors, delay lines, time base correctors, HDTV P-MQFP-64-1 Type Ordering Code Package SDA 9254-2 on request P-MQFP-64-1 Semiconductor Group 1 1998-01-16 SDA 9254-2 Functional Description General The SDA 9254-2 is a combination of the TV-SAM SDA 9253 and an adaptive recursive filter to achieve a reduction of noise for video signals. To get a closed loop one of the two output ports of the triple port memory is connected internally to the noise reduction filter. External access to this port is not possible. The characteristic of the noise reduction filter is adjustable via three pins (CLASS2, CLASS1, CLASS0). SDC0 ... 11 12 Noise Reduction Filter BLN NR422 CLASS 12 3 Port C Field Memory 12 Port B Port A 12 SQA0 ... 11 UEB10379 Figure 1 Block Diagram The memory capacity of the SDA 9254-2 enables a field based filtering of 4:1:1 video signals (pin NR422 = ‘0’). 4:2:2 applications are supported by a special noise reduction mode (pin NR422 = ‘1’). In this mode filtering is applied only to the luminance signal, the chrominance signals are delayed by an internal delay line but remain unfiltered. For the storage of 4 bit planes of the chrominance signal a SDA 9251-2X is requested additionally. Semiconductor Group 2 1998-01-16 SDA 9254-2 V DD CLASS Y NR422 3 SDC4...11 4 UV 8 SQA4...11 8 8 4 SDA 9254-2 SQA0...3 SDC0...3 DLO0...3 Y 4 4 8 UV DLI0...3 SDC0...3 SDA 9251-2X SQA0...3 4 UEB10380 Figure 2 Noise Reduction with 4:2:2 Signals Adaptive Field Based Noise Reduction The reduction of noise is performed by recursive filtering. The filter has the following transfer function: K H ( z ) = ------------------------------------------–1 1 – 〈 1 – K〉 × z z = e jωT FLD , T FLD = fielddelay For K = 1 the transfer function is H(z) = 1, that means no filtering is performed and the input data remains unchanged. For K < 1 noise reduction filtering is activated. The input data and the delayed data from the memory are combined according H(z). Semiconductor Group 3 1998-01-16 SDA 9254-2 SDC0 ... 11 Video Input 12 DEMUX Input Luminance CLASS 3 8 8 Input Chrominance K Motion Detector 4 Recursive Filter 8 MUX 12 Memory Port C 8 delayed Luminance Memory Port B 12 8 8 delayed Chrominance Clock and Control DEMUX BLN SCB UEB10381 Figure 3 Block Diagram of the Noise Reduction Filtering To avoid artefacts in moving parts of the picture a motion detector is implemented to control the filter coefficient K according to detected changes between two adjacent fields. The motion detector performs a low pass filtering of the field differences and builds the absolute values. The results control the filter coefficient K by choosing one of 13 predefined values between 1/4 and 1. The characteristic of this assignment influences the amount of noise reduction and is adjustable via the CLASS-pins. The calculation of the filter coefficient is practised for each pixel of the field. Adjustment of the Characteristic of the Noise Reduction Filter CLASS2 CLASS1 CLASS0 Amount of Noise Reduction x 0 0 Low x 0 1 Low-mid 0 1 0 Mid-high 1 1 0 High x 1 1 Noise reduction off These four possible adjustments put a wide field of different intensities of noise reduction at user’s disposal. The recursive filter also enables a reduction of cross color interference because the Motion Detector exploits only luminance data. Semiconductor Group 4 1998-01-16 SDA 9254-2 The following diagram shows the requested data format for 4:1:1 signals at the input SDC0 … SDC11. The output data format at pins SQA0 … SQA11 corresponds to the input format. BLN 13.5 MHz SDC 4 ... 11 Y1 Y2 Y3 Y4 Y5 Y6 SDC 3 U1,7 U1,5 U1,3 U1,1 U2,7 U2,5 SDC 2 U1,6 U1,4 U1,2 U1,0 U2,6 U2,4 SDC 1 V1,7 V1,5 V1,3 V1,1 V2,7 V2,5 SDC 0 V1,6 V1,4 V1,2 V1,0 V2,6 V2,4 UED08600 Figure 4 Input Data Format (4:1:1) Memory The memory has a capacity of 2605056 bit. It is organized as 212 rows by 64 columns by 16 arrays by 12 bit and allows the storage of the active part of a complete 4:1:1-TV field using a 13.5 MHz sample rate. The memory is fabricated using the same CMOS technology used for 4-Mbit standard dynamic random access memories. The extremely high maximum data rate is achieved by three internal shift registers, each of 16-bit length and 12-bit width, which perform a serial to parallel conversion between the asynchronous input/output data streams and the memory array. The parallel data transfer from the 16 x 12-bit input shift register C to an addressed location of the memory array and from the memory array to one of the 16 x 12-bit output shift registers A or B is controlled by the serial row-(SAR) and column address (SAC) which contains the desired column address and an instruction code (mode bits) for transfer and refresh. Semiconductor Group 5 1998-01-16 SDA 9254-2 Circuit Description Memory Architecture As shown in the block diagram of the memory part (see figure 7), the TV-SAM comprises 192 memory arrays, which are accessed in parallel. Each memory array has a size of 212 rows by 64 columns. The rows and columns of the 192 arrays can be randomly addressed, reading or writing 16 x 12 bits at a time. To obtain the extremely high data rate at the 12-bit wide data input (port C) and outputs (port A and B), a parallel to serial conversion is done using shift registers of 16-bit length and 12-bit width. In this way the memory speed is increased by a factor of 16. (This is independent on the number of ports if the total data rate is regarded.) Independent operation of the serial input and the two serial outputs is guaranteed by using three shift registers. The decoupling from the common 16 x 12-bit memory data bus is done by three latches which allow a flexible memory timing and a flying real-time data transfer. A real-time data transfer is necessary to ensure a continuous data flow at the data pins even at maximum clock speed. To save pins without loosing speed, the TV-SAM is addressed serially using a serial 8-bit row address and a serial 8-bit column address which includes two mode control bits. The serial row and column addresses are converted to parallel addresses internally, then latched and fed to the row and column decoders. The internal memory controller is responsible for the timing of the memory read/write access and the refresh operation. Data Input (SDC, SCB) The data pins SDC are connected to the input of the recursive filter. The delay time from SDC to the memory port C caused by the filter amounts 8 periods of the clock SCB. The delay time is to be considered for the generation of the signal WT (see diagram 8). Data are shifted into the memory using the serial port C at the rising edge of the shift clock SCB. After 16 clock pulses the data have to be transferred from shift register C to latch C. If more than 16 clock pulses occur before latching the data, only the last sixteen 12-bit data values are accepted. Data Input (DLI), Data Output (DLO, OEDLO) In 4:2:2-mode 4 bitplanes of the chrominance signals are connected to an internal delay line via the pins DLI. After 8 periods of clock SCB the input data are supplied at the delay line output DLO. Via the output enable OEDLO the output buffers can be switched into tristate. In 4:1:1-mode the DLI pins should be connected to GND and pin OEDLO should be connected to VDD. Data Transfer from Shift Register C to Latch C (WT) The contents of the shift register C is transferred to latch C at the falling edge of the write transfer signal WT. If the timing restrictions between WT and the clock SCB are respected, a continuous data flow at input port C is possible without loosing data. This transfer operation may be asynchronous to all other transfer operations except for a small forbidden window conditioned by the latch C to memory transfer, see diagram 4. Semiconductor Group 6 1998-01-16 SDA 9254-2 Write Transfer from Latch C to Memory (RE) The data of latch C are transferred to the preaddressed location of the memory array at the rising edge of RE, if the mode bits were set to H (M1) and L (M0), see “Addressing and Mode Control.” Addressing and Mode Control (SAR, SAC, SCAD, RE) The serial 8-bit row address SAR and the 8-bit column address/mode code SAC are serially shifted into the TV-SAM (LSB first) at rising edge of the address clock SCAD. After 8 SCAD cycles, the falling edge of RE internally latches SAR and SAC. The column address itself needs only 6 bits. The last 2 bits of SAC are defined as mode bits and determine the read/write and refresh operation of the memory arrays to be triggered by the RE signal. Mode Bit M1 Mode Bit M0 Operation L L Read transfer from memory to latch A L H Read transfer from memory to latch B H L Write transfer from latch C to memory H H Refresh with internal row address Read Transfer from Memory to Latch A or B (RE) Memory data from a preaddressed location are transferred to latch A or B at the falling edge of RE, depending on the mode control bits, see “Addressing and Mode Control”. Data Transfer from Latch A to Shift Register A (RA) The data of latch A are transferred to shift register A at the falling edge of the read transfer signal RA. If the timing restrictions between RA and the shift clock SCA are taken into account, a continuous data flow at output SQA without interrupts is possible. This transfer operation is independent on all other transfer operations except for a small forbidden time window conditioned by the memory to latch A transfer. Data Transfer from Latch B to Shift Register B (RB) The data of latch B are transferred to shift register B at the falling edge of the read transfer signal RB. If the timing restrictions between RB and the shift clock SCB are taken into account, a continuous data flow at memory output port B without interrupts is possible. This transfer operation is independent on all other transfer operations except for a small forbidden time window conditioned by the memory to latch B transfer. For correct operation of the recursive filtering the memory output data at port B must be in phase with the input data SDC. This restriction forces a fixed space of time between RB and WT of 25 clock periods of SCB (see diagram 8). Semiconductor Group 7 1998-01-16 SDA 9254-2 Data Output A (SQA, SCA, OEA) Data is shifted out through the serial port A (SQA0 … SQA11) at the rising edge of the shift clock SCA. After 16 clock cycles new data have to be transferred from latch A to shift register A. Otherwise data values are cyclically repeated. Via the output enable OEA the output buffers can be switched into tristate. The shift clock SCA may be completely independent on the shift clock for port B and C (SCB). Memory Output (Port B, SCB) Data is shifted out through the serial port B at the rising edge of the shift clock SCB. After 16 clock cycles new data have to be transferred from latch B to shift register B. Otherwise data values are cyclically repeated. The shift clock SCB is also used for the input port C. Refresh Either 256 refresh cycles (refresh with external row address) or read/write cycles on 212 consecutive row addresses beginning with address 0 have to be executed within an 16 ms interval to maintain the data in the memory arrays. A refresh with internal row adress is determined by the mode control bits, see “Addressing and Mode Control”. In this refresh mode, the row and column addresses are ignored (see diagram 6a and 6b). Initialization The device incorporates an on-chip substrate bias generator as well as dynamic circuitry. Therefore an initial pause of 200 µs is required after power on, followed by eight RE-cycles before proper device operation is achieved. Typical Memory Cycle Sequence A typical application of the TV-SAM is a real-time noise reduction filtering combined with flicker reduction. This can be achieved, for example, by writing and reading with 13.5-MHz clock rate via port C and B and by simultaneously reading port A with 27-MHz double speed clock. A main cycle of 4 consecutive RE cycles of transfer is needed: 1st. RE-cycle: Read transfer from memory to latch A 2nd. RE-cycle: Read transfer from memory to latch B 3rd. RE-cycle: Same as 1st. RE cycle 4th. RE-cycle: Write transfer from latch C to memory Each transfer cycle is preceeded by an address cycle as shown in the diagram page 6: For the clock rates mentioned this means a serial cycle time of 74 ns at port B and C and 37 ns at port A. The addressing cycle time for each port is given by 16 times the serial data rate. Thus we have an addressing cycle time of approx. 1184 ns for port B and port C. The address for port A must be loaded every 592 ns. Since all addresses are shifted in sequentially, a RE cycle time of approx. 296 ns is necessary. Semiconductor Group 8 1998-01-16 SDA 9254-2 The beginning of a block of 16 serial data at port A or B is determined by RA and RB, respectively. The end of the serial input data block at port C is controlled by WT. Since RA, RB and WT can be independently chosen (except for small forbidden time windows when memory transfers are executed), the serial data streams can be shifted against each other without influencing the RE cycles. For activated noise reduction the timing restrictions for RB and WT must be considered (see Data Transfer from latch B to Shift Register B). Semiconductor Group 9 1998-01-16 Semiconductor Group 10 296 ns 1 Addressing B Read Transfer A 2 Read Transfer B RA Addressing A 3 Addressing C 16x74 ns 16 Serial Clock Cycles SCB Write Transfer C Serial Port B 4 1 4 UED02042 RE Cycle 2 Read Transfer B Serial Port A 3 WT RB Addressing B 16 Serial Clock Cycles SCA Serial Port C Write Transfer C RA 16 Serial Clock Cycles SCB Addressing C 16x37 ns 16 Serial Clock Cycles SCA Read Transfer A Functionally coherent blocks are emphasized The vertical arrows indicate the moment of the data transfer from a latch to the shift register, or vice versa Addressing A SDA 9254-2 Figure 5 Typical Memory Cycle Sequence 1998-01-16 SDA 9254-2 Pin Configuration (top view) SDC3 SDC2 SDC1 SDC0 BLN NR422 V DD2 V SS2 DLI0 DLI1 DLI2 DLI3 V DD2 V SS2 SQA0 SQA1 P-MQFP-64-1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 49 31 50 30 51 29 52 28 53 27 54 26 55 25 56 SDA 9254-2 24 57 23 58 22 59 21 60 20 61 19 62 18 63 64 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SDC8 SDC9 SDC10 SDC11 CLASS0 CLASS1 V DD2 V SS2 DLO0 DLO1 DLO2 DLO3 V DD2 V SS2 SQA11 SQA10 SDC4 SDC5 SCA SAR SAC SCAD RE V DD1 V SS1 RA RB WT CLASS2 SCB SDC6 SDC7 SQA2 SQA3 V DD2 V SS2 SQA4 SQA5 OEA V SS1 V DD1 OEDL0 SQA6 SQA7 V SS2 V DD2 SQA8 SQA9 UEP10382 Figure 6 Semiconductor Group 11 1998-01-16 SDA 9254-2 Pin Definitions and Functions Pin No. Symbol Input (I) Output (O) 15 . . 18 21 22 27 28 SQA11 . . SQA8 SQA7 SQA6 SQA5 SQA4 O . . . . . . O Serial data output port A (luminance signal) 31 32 33 34 SQA3 . . SQA0 O . . O Serial data output port A (chrominance signal) 51 SCA I Serial clock input for port A 58 RA I Read transfer control input (latch A to shift register A) 26 OEA I Output enable input for port A 62 SCB I Serial clock input for port B and C 59 RB I Read transfer control input (latch B to shift register B) 23 OEDLO I Output enable input for delay line output 4 . . 1 64 63 50 49 SDC11 . . SDC8 SDC7 SDC6 SDC5 SDC4 I . . . . . . I Serial data input port C (luminance signal) 48 47 46 45 SDC3 SDC2 SDC1 SDC0 I I I I Serial data input port C (chrominance signal) 60 WT I Write transfer control input (shift register C to latch C) 52 SAR I Serial row address input 53 SAC I Serial column address and mode control input 54 SCAD I Serial address clock input 55 RE I RAM-enable input (also latches the addresses) 5 6 CLASS0 CLASS1 I I Characteristic of the noise reduction filter Semiconductor Group Function 12 1998-01-16 SDA 9254-2 Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) Function 61 CLASS2 I (medium or strong) 12 11 10 9 DLO3 DLO2 DLO1 DLO0 O O O O Delay line output (for 4:2:2-mode) 37 38 39 40 DLI3 DLI2 DLI1 DLI0 I I I I Delay line input (for 4:2:2-mode) 43 NR422 I Noise reduction 4:2:2 44 BLN I Horizontal blanking input 7, 13, 19, 30, 36, 42 VDD2 Data output power supply (+ 5 V) 8, 14, 20, 29, 35, 41 VSS2 Data output power supply (GND) 24, 56 VDD1 Memory power supply (+ 5 V), must be connected to VDD2 25, 57 VSS1 Memory power supply (GND), must be connected to VSS2 Semiconductor Group 13 1998-01-16 SDA 9254-2 V DD1 V DD2 V SS1 V SS2 Port B 12 OEB SCB Port C SCA 12 Shift Register B Shift Register C 16 x 12 Shift Register A 16 x 12 Latch C Latch B 16 x 12 OEA SQA0 12 16 x 12 SQA11 Latch A 16 x 12 16 x 12 16 x 12 R o w D e c o d e r 16 x 12 Memory Cell Arrays 212 x 64 Bit 212 to Latches 64 8 Column Address Decoder 6 Internal Memory Controller RE TF WT RA RB SAC SAR SCAD UEB08602 Figure 7 Block Diagram of the Memory Semiconductor Group 14 1998-01-16 SDA 9254-2 Absolute Maximum Ratings Parameter Symbol Limit Values Unit min. max. – 55 125 °C Storage temperature Tstg Soldering temperature Tsold 260 °C Soldering time tsold 10 s Input/output voltage VI/Q –1 7 V Power supply voltage VDD –1 7 V Data out current (short circuit) IQ 10 mA Total power dissipation Ptot 1.2 W Power dissipation per output PQ 60 mW Remarks Operating Range Parameter Symbol Limit Values min. typ. max. Unit Supply voltage VDD1 4.5 5.0 5.5 V Supply voltage VDD2 4.5 5.0 5.5 V Supply voltage VSS1 0 V Supply voltage VSS2 0 V H-input voltage (except CLASS2) VIH 2.0 6.5 V L-input voltage (except CLASS2) VIL – 1.0 0.8 V H-input voltage (CLASS2) VIHC VDD – 0.5 5.5 V L-input voltage (CLASS2) VILC – 1.0 VSS + 0.5 V Ambient temperature TA 0 Semiconductor Group 15 25 70 °C 1998-01-16 SDA 9254-2 DC Characteristics VDD = 5 V ± 10 %; TA = 0 to 70 °C Parameter Symbol Limit Values min. typ. Unit Test Condition V IOUT = – 2.5 mA 0.4 V IOUT = 2.1 mA max. H-output voltage VQH L-output voltage VQL Input leakage current II (L) – 10 10 µA 0 V ≤ VI ≤ 6.5 V Output leakage current IQ (L) – 10 10 µA OEA = OEDLO = VIH Average supply current ICCa 200 mA (tSC port A = tSC min) (tSC port B = 2 tSC min) (tSC port C = 2 tSC min) (tRC = tRC min) ICCa depends on cycle rate and on output loading. Specified values are measured with open output. Standby supply current ICCb 5 mA (RE = OEA = OEDLO = VDD1) tSC (SCA, SCB, SCAD) = max. (tSC) Semiconductor Group 2.4 16 1998-01-16 SDA 9254-2 AC Characteristics VDD = 5 V ± 10 %; TA = 0 to 70 °C Parameter Symbol Limit Values min. typ. Unit Test Condition max. Memory read or write cycle time tRC 240 100000 ns Operation with tRC ≥ tRCmin ensures that 8-bit serial data are shifted out within one RE cycle taking tSC = tSCmin. See diagram 2, 3, 4, 6 RE low time tRE 100 100000 ns See diagram 2, 3, 4, 6 Serial port cycle time tSC 30 100000 ns See diagram 2 – 6 RE precharge time tRP 100 ns See diagram 2, 3, 4, 6 Address setup time tAS 5 ns See diagram 2, 3, 4, 6 Address hold time tAH 6 ns See diagram 2, 3, 4, 6 SCAD to RE set-up time tROS 3 ns See diagram 2, 3, 4, 6 RE to SCAD hold time tROH 10 ns See diagram 2, 3, 4, 6 RE to RA or RB delay time tRRD 90 ns tRRD and tRRL are restrictive operating parameters only in memory read transfer cycles. See diagram 2, 3 RA or RB to RE lead time tRRL – 30 ns See RE to RA or RB delay time. See diagram 2, 3 RA to SCA RB to SCB set-up time tRSS 0 ns See diagram 2, 3 RA or RB pulse width tRPW 10 ns See diagram 2, 3 RA to SCA RB to SCB hold time tRSH 15 ns See diagram 2, 3 Semiconductor Group 17 1998-01-16 SDA 9254-2 AC Characteristics (cont’d) VDD = 5 V ± 10 %; TA = 0 to 70 °C Parameter Symbol Limit Values min. WT to RE lead time tWRL typ. Unit Test Condition ns tWRL and tRWL are restrictive max. 30 operating parameters only in memory write transfer cycles. In that case tWRL applies if the write transfer from shifter C to latch C occurs before the rising edge of RE. Otherwise tRWL has to be satisfied. See diagram 4 RE to WT lead time tRWL 50 Output buffer turnoff delay tOFF 0 WT to SCB delay time tWTD WT to SCB lead time ns See WT to RE lead time ns tOFF (max) defines the time at which the output achieves the open-circuit condition and is not referenced to output voltages levels. 0 ns See diagram 4 tWTL 15 ns See diagram 4 WT pulse width tWTP 10 ns See diagram 4 OEA to output A access time tOAA 25 ns See diagram 2, 5 Access time from SCA tCAA 25 ns See diagram 2 Access time from SCB tCBA 25 ns See diagram 3, 7 Data input set-up time to SCB tDS 5 ns See diagram 5, 7 Data input hold time tDH to SCB 6 ns See diagram 5, 7 ns See diagram 7 OEDLO to output DLO access time Semiconductor Group 20 tODA 25 18 1998-01-16 SDA 9254-2 AC Characteristics (cont’d) VDD = 5 V ± 10 %; TA = 0 to 70 °C Parameter Symbol Limit Values min. typ. Unit Test Condition 16 ms Either 256 refresh cycles or read/write cycles on 212 consecutive row addresses have to be performed within the 16 ms interval to maintain data 10 ns Transition times are measured between VIH and VIL. See diagram 1 max. Refresh period tREF Transition time (rise/fall) tT 2 L-serial clock time tSCL 10 ns See diagram 2 H-serial clock time tSCH 10 ns See diagram 2 Hold time from SCA tCAH 6 ns See diagram 2 Hold time from SCB tCBH 6 ns See diagram 3, 7 Input capacitance (SCA, SCB) CI 1 7 pF f = 1 MHz Input capacitance (all other pins) CI 2 5 pF f = 1 MHz Output capacitance (SQA 0-11, DLO 0 ... 3) CQ 7 pF f = 1 MHz Semiconductor Group 19 1998-01-16 SDA 9254-2 Operation Truth Table RE Cycle N SCAD SAR RE Cycle N + n, n = 1, 2, 3 … SAC Mode M0 M1 OEA OEDLO SCA SCB RA RB WT Operation X X Read transfer from memory to shifter A X Read transfer from memory to shifter B RA0…RA 7 CA0…CA 5 L L X X X X RA0…RA 7 CA0…CA 5 H L X X X X X RA0…RA 7 CA0…CA 5 L H X X X X X X X X H H X X X X X X X Refresh with internal row address X X X X X L X X X X X Serial read port A X X X X X X L X X X X Data output DLO X X X X X X X X X X X Serial read port C Note: X = Don’t care Semiconductor Group Write transfer from shifter C to memory Row address, column address and mode bits have to be defined in RE cycle N in order to become effective in RE cycle N + 1 20 1998-01-16 SDA 9254-2 3V VIH VIL 0V tT Input conditions : VIH = 2.0 V VIL = 0.8 V t T = 3 ns VQH HIGH Z VQL Output conditions : VOH = 2.4 V VOL = 0.4 V Output loading: SQ 433 Ω 1.31 V 30 pF UED10454 Diagram 1 AC-Timing Measuring Conditions Semiconductor Group 21 1998-01-16 SDA 9254-2 t RC t RE t RP RE t ROH t ROS t SCH t SC SCAD t SCL t AH t AS SAR RA6 RA7 RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA0 RA1 SAC L L CA0 CA1 CA2 CA3 CA4 CA5 M0 M1 CA0 CA1 2 3 4 t RRD t RSS RA t RRL t RPW t RSH OEA t SCH t SC SCA t CAH t SCL SQA(0-11) 13 14 t OAA 15 16 1 UET07391 t CAA Diagram 2 Read Transfer Memory to Port A Semiconductor Group 22 1998-01-16 SDA 9254-2 t RC t RE t RP RE t ROH t ROS t SC SCAD t AH t AS SAR RA6 RA7 RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA0 RA1 SAC H L CA0 CA1 CA2 CA3 CA4 CA5 M0 M1 CA0 CA1 2 3 4 t RRD t RSS RB t RRL t RPW t SC t RSH SCB t CBH Port B 13 14 t CBA 15 16 1 UET08603 Diagram 3 Read Transfer Memory to Port B Semiconductor Group 23 1998-01-16 SDA 9254-2 t RC t RE t RP RE t ROH t ROS t SCH t SC SCAD t AH t SCL t AS SAR RA6 RA7 RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA0 RA1 SAC L H CA0 CA1 CA2 CA3 CA4 CA5 M0 M1 CA0 CA1 t WRL t RWL WT t WTD t WTD t WTP t WTP t WTL t WTL SCB t SC t SC t DH t DH t DS Port C 15 t DS 16 1 2 15 16 1 2 UET08604 Diagram 4 Write Transfer from Port C to Memory Semiconductor Group 24 1998-01-16 SDA 9254-2 Serial Read Operation Port A t SC t SCH SCA t CAA t CAH t SCL OEA t OAA SQA(0-11) t OFF Valid Data Valid Data Serial Read Operation Port B t SC Valid Data t SCH SCB t CBA t CBH t SCL OEB t OBA Port B t OFF Valid Data Valid Data Serial Write Operation Port C t SC Valid Data t SCH SCB t DH t SCL t DS Port C Valid Data Valid Data Valid Data UET08605 Diagram 5 Serial Read and Write Operations Semiconductor Group 25 1998-01-16 SDA 9254-2 t RC t RE t RP RE t ROH t ROS t SC SCAD t AH t AS SAC H H M0 M1 UED08620 Diagram 6a Refresh with Internal Row Address Semiconductor Group 26 1998-01-16 SDA 9254-2 t RC t RE t RP RE t ROH t ROS t SC SCAD t AH t AS SAR RA6 SAC LLH * *) RA7 ) LHL * RA0 RA1 RA2 RA3 RA4 ) RA5 RA6 RA7 CA5 M0 M1 RA0 RA1 UED08617 Mode bits arbitrary, except combination M0 = "H" and M1 = "H" *) Mode bits should toggle in successive cycles Diagram 6b Refresh with External Row Address Semiconductor Group 27 1998-01-16 SDA 9254-2 SCB BLN DLN t DS t DH OEDLO t CBH DLO t ODA t CBA UET08618 Diagram 7 Timing of BLN, DLI and DLO Semiconductor Group 28 1998-01-16 SDA 9254-2 t SC SCB 0 1 10 9 2 SDC Ι1 Ι2 Ι9 Ι 10 Port B B1 B2 B9 B10 C1 C2 Port C t RSS 25 24 C15 26 C16 Delay of recursive t RSH filter (8 t SC ) RB t WTD t RPW t WTL WT t RBWT 25 t SC t WTP UET08619 Diagram 8 RB, WT Timing Restrictions Semiconductor Group 29 1998-01-16 SDA 9254-2 Application Circuit For best performance and operation within the specified AC parameter limits it is mandatory to use separate decoupling capacitors for VSS1/VDD1 and VSS2/VDD2 with VSS1 shorted to VSS2 and VDD1 shorted to VDD2 on the board as shown in figure below. Decoupling capacitors C1 and C2 of low inductance multilayer type (at least 0.1 µF) should be used. To avoid malfunction or even permanent damage of the device it is strongly recommended not to use any other supply configuration. C 42 41 36 35 30 29 56 25 SDA 9254-2 57 C 24 C 20 19 7 8 61 13 14 V SS C V DD UES10383 Figure 8 Semiconductor Group 30 1998-01-16 SDA 9254-2 Application Information Digital Storage of a TV Field As standard for digital TV systems, CCIR recommendation 601 defines a field of 288 lines with 720 pixels per line. The sampling frequency is 13.5 MHz with a resolution of 8 bit per pixel. Information is stored in 3 different channels: one channel for luminance (Y), two channels for chrominance (U and V). The bandwidth ratio between the different channels is either Y:U:V = 4:1:1 or 4:2:2 depending on the coding method. The bus width for the 4:1:1 format is 12 bit, the 4:2:2 format requires 16 bit and a SDA 9251-2X memory device additionally. The SDA 9254-2 is designed for low cost large area flicker- and noise reduction systems. The following block diagram shows a typical application for 4:1:1 signals. 12 YIN UIN VIN SDA 9254-2 Triple ADC + CSG SDA 9206 YOUT UOUT VOUT Address SYNC CVBS Display Processor SDA 9280 12 MSC SDA 9220-5 SYNC To Deflection UEB08607 Figure 9 Low Cost Flicker- and Noise Reduction System with SDA 9254-2 Semiconductor Group 31 1998-01-16 SDA 9254-2 Package Outlines GPM05250 P-MQFP-64-1 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 32 Dimensions in mm 1998-01-16