INFINEON SDA9253

2.6 MBit Dynamic Sequential Access Memory
for Television Applications (TV-SAM)
SDA 9253
Preliminary Data
CMOS IC
Features
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212 × 64 × 16 × 12-bit organization
Triple port architecture
One 16 × 12-bit input shift register
Two 16 × 12-bit output shift registers
Shift registers independently and simultaneously
accessible
Continuous data flow even at maximum speed
40-MHz shift rate – 0.96-Gbit/s total data rate
All inputs and outputs TTL-compatible
Tristate outputs
Random access of groups of 16 × 12 bits for a wide range
of applications
Refresh-free operation possible
5 V ± 10 % power supply
0 … 70 °C operating temperature range
Low power dissipation: 700 mW active, 28 mW standby
Suitable for all common TV standards
Allows flicker and noise reduction simultaneously
with only one field memory
Applications: TV, VCR, image processing,
video printers, data compressors, delay lines,
time base correctors, HDTV
P-MQFP-64-1
Type
Ordering Code
Package
SDA 9253
Q67101-H5171
P-MQFP-64-1
Semiconductor Group
1
1998-01-30
SDA 9253
Functional Description
The SDA 9253 is a triple port 2605056 bit dynamic sequential-access memory for high-data-rate
video applications. It is organized as 212 rows by 64 columns by 16 arrays by 12 bit to allow for the
storage of 12-bit planes of a TV field (NTSC, PAL, SECAM, MAC) in standard or studio quality
(13.5-MHz basic sample rate) or 12-bit planes of parts of a HDTV field. The memory is fabricated
using the same CMOS technology used for 4-Mbit standard dynamic random access memories.
The extremely high maximum data rate is achieved by three internal shift registers, each of 16-bit
length and 12-bit width, which perform a serial to parallel conversion between the asynchronous
input/output data streams and the memory array. The parallel data transfer from the 16 × 12-bit
input shift register C to an addressed location of the memory array and from the memory array to
one of the 16 × 12-bit output shift registers A or B is controlled by the serial row-(SAR) and column
address (SAC) which contains the desired column address and an instruction code (mode bits) for
transfer and refresh.
Circuit Description
Memory Architecture
As shown in the block diagram, the TV-SAM comprises 192 memory arrays, which are accessed in
parallel. Each memory array has a size of 212 rows by 64 columns. The rows and columns of the
192 arrays can be randomly addressed, reading or writing 16 × 12 bits at a time. To obtain the
extremely high data rate at the 12-bit wide data input (SDC) and outputs (SQA, SQB), a parallel to
serial conversion is done using shift registers of 16-bit length and 12-bit width. In this way the
memory speed is increased by a factor of 16. (This is independent on the number of ports if the total
data rate is regarded.)
Independent operation of the serial input and the two serial outputs is guaranteed by using three
shift registers. The decoupling from the common 16 × 12-bit memory data bus is done by three
latches which allow a flexible memory timing and a flying real-time data transfer.
A real-time data transfer is necessary to ensure a continuous data flow at the data pins even at
maximum clock speed.
To save pins without loosing speed, the TV-SAM is addressed serially using a serial 8-bit row
address and a serial 8-bit column address which includes two mode control bits. The serial row and
column addresses are converted to parallel addresses internally, then latched and fed to the row
and column decoders. The internal memory controller is responsible for the timing of the memory
read/write access and the refresh operation.
Semiconductor Group
2
1998-01-30
SDA 9253
Data Input (SDC, SCB)
Data are shifted in through the serial port C (SDC0, …, SDC11) at the rising edge of the shift clock
SCB. After 16 clock pulses the data have to be transferred from shift register C to latch C. If more
than 16 clock pulses occur before latching the data, only the last sixteen 12-bit data values are
accepted.
Data Transfer from Shift Register C to Latch C (WT)
The contents of the shift register C are transferred to latch C at the falling edge of the write transfer
signal WT. If the timing restrictions between WT and the clock SCB are respected, a continuous
data flow at input SDC is possible without loosing data. This transfer operation may be
asynchronous to all other transfer operations except for a small forbidden window conditioned by
the latch C to memory transfer, see diagram 4.
Write Transfer from Latch C to Memory (RE)
The data of latch C are transferred to the preaddressed location of the memory array at the rising
edge of RE, if the mode bits were set to H (M1) and L (M0), see “Addressing and Mode Control.”
Addressing and Mode Control (SAR, SAC, SCAD, RE)
The serial 8-bit row address SAR and the 8-bit column address/mode code SAC are serially shifted
into the TV-SAM (LSB first) at rising edge of the address clock SCAD. After 8 SCAD cycles, the
falling edge of RE internally latches SAR and SAC. The column address itself needs only 6 bits. The
last 2 bits of SAC are defined as mode bits and determine the read/write and refresh operation of
the memory arrays to be triggered by the RE signal.
Mode Bit M1
Mode Bit M0
Operation
L
L
Read transfer from memory to latch A
L
H
Read transfer from memory to latch B
H
L
Write transfer from latch C to memory
H
H
Refresh with internal row address
Read Transfer from Memory to Latch A or B (RE)
Memory data from a preaddressed location are transferred to latch A or B at the falling edge of RE,
depending on the mode control bits, see “Addressing and Mode Control”.
Data Transfer from Latch A to Shift Register A (RA)
The contents of latch A are transferred to shift register A at the falling edge of the read transfer
signal RA. If the timing restrictions between RA and the shift clock SCA are taken into account, a
continuous data flow at output SQA without interrupts is possible. This transfer operation is
independent on all other transfer operations except for a small forbidden time window conditioned
by the memory to latch A transfer.
Semiconductor Group
3
1998-01-30
SDA 9253
Data Transfer from Latch B to Shift Register B (RB)
The contents of latch B are transferred to shift register B at the falling edge of the read transfer
signal RB. If the timing restrictions between RB and the shift clock SCB are taken into account, a
continuous data flow at output SQB without interrupts is possible. This transfer operation is
independent on all other transfer operations except for a small forbidden time window conditioned
by the memory to latch B transfer.
Data Output A (SQA, SCA, OEA)
Data is shifted out through the serial port A (SQA0 … SQA11) at the rising edge of the shift clock
SCA. After 16 clock cycles new data have to be transferred from latch A to shift register A.
Otherwise data values are cyclically repeated.
Via the output enable OEA the output buffers can be switched into tristate.
The shift clock SCA may be completely independent on the shift clock for port B and C (SCB).
Data Output B (SQB, SCB, OEB)
Data is shifted out through the serial port B (SQB0 … SQB11) at the rising edge of the shift clock
SCB. After 16 clock cycles new data have to be transferred from latch B to shift register B.
Otherwise data values are cyclically repeated. The shift clock SCB is also used for the input port C.
Via the output enable OEB the output buffers can be switched into tristate.
Refresh
Either 256 refresh cycles or read/write cycles on 212 consecutive row addresses beginning with
address 0 have to be executed within an 16 ms interval to maintain the data in the memory arrays.
A refresh cycle is determined by the mode control bits, see “Addressing and Mode Control”. In the
refresh mode, the row and column addresses are ignored.
Initialization
The device incorporates an on-chip substrate bias generator as well as dynamic circuitry. Therefore
an initial pause of 200 µs is required after power on, followed by eight RE-cycles before proper
device operation is achieved.
Semiconductor Group
4
1998-01-30
SDA 9253
Typical Memory Cycle Sequence
A typical application of the TV-SAM is a real-time interfield image processing combined with flicker
reduction. This can be achieved, for example, by writing and reading with 13.5-MHz clock rate via
port C and B and by simultaneously reading port A with 27-MHz double speed clock. A main cycle
of 4 consecutive RE cycles of transfer is needed:
1st.
RE-cycle:
Read transfer from memory to latch A
2nd.
RE-cycle:
Read transfer from memory to latch B
3rd.
RE-cycle:
Same as 1st. RE cycle
4th.
RE-cycle:
Write transfer from latch C to memory
Each transfer cycle is preceeded by an address cycle as shown in the diagram page 6:
For the clock rates mentioned this means a serial cycle time of 74 ns at port B and C and 37 ns at
port A. The addressing cycle time for each port is given by 16 times the serial data rate. Thus we
have an addressing cycle time of approx. 1184 ns for port B and port C. The address for port A must
be loaded every 592 ns. Since all addresses are shifted in sequentially, a RE cycle time of approx.
296 ns is necessary.
The beginning of a block of 16 serial data at port A or B is determined by RA and RB, respectively.
The end of the serial input data block at port C is controlled by WT. Since RA, RB and WT can be
independently chosen (except for small forbidden time windows when memory transfers are
executed), the serial data streams can be shifted against each other without influencing the RE
cycles.
Semiconductor Group
5
1998-01-30
Semiconductor Group
6
296 ns
1
Addressing
B
Read
Transfer A
2
Read
Transfer B
RA
Addressing
A
3
Addressing
C
16x74 ns
16 Serial Clock
Cycles SCB
Write
Transfer C
Serial
Port B
4
1
4
UED02042
RE
Cycle
2
Read
Transfer B
Serial
Port A
3
WT
RB
Addressing
B
16 Serial Clock
Cycles SCA
Serial
Port C
Write
Transfer C
RA
16 Serial Clock
Cycles SCB
Addressing
C
16x37 ns
16 Serial Clock
Cycles SCA
Read
Transfer A
Functionally coherent blocks are emphasized
The vertical arrows indicate the moment of the data transfer from a latch to the shift register, or vice versa
Addressing
A
SDA 9253
Figure 1
Typical Memory Cycle Sequence
1998-01-30
SDA 9253
SDC3
SDC2
SDC1
SDC0
SQB0
SQB1
VDD2
VSS2
SQB2
SQB3
SQA4
SQA5
VDD2
VSS2
SQA0
SQA1
Pin Configuration
(top view)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SDC4
SDC5
SCA
SAR
SAC
SCAD
RE
VDD1
VSS1
RA
RB
WT
OPM
SCB
SDC6
SDC7
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SDA 9253
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SQA2
SQA3
VDD2
VSS2
SQA4
SQA5
OEA
VSS1
VDD1
OEB
SQA6
SQA7
VSS2
VDD2
SQA8
SQA9
SDC8
SDC9
SDC10
SDC11
SQB6
SQB7
VDD2
VSS2
SQB8
SQB9
SQB10
SQB11
VDD2
VSS2
SQA11
SQA10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
UEP07388
Figure 2
Semiconductor Group
7
1998-01-30
SDA 9253
Pin Definitions and Functions
Pin No.
Symbol
Input (I)
Output (O)
34
33
16
15
SQA0
.
.
SQA11
O
O
O
O
51
SCA
I
Serial clock input for port A
58
RA
I
Read transfer control input (latch A to shift register A)
26
OEA
I
Output enable input for port A
44
43
11
12
SQB0
.
.
SQB11
O
O
O
O
Serial data output for port B
62
SCB
I
Serial clock input for port B and C
59
RB
I
Read transfer control input (latch B to shift register B)
23
OEB
I
Output enable input for port B
45
46
3
4
SDC0
.
.
SDC11
I
I
I
I
60
WT
I
Write transfer control input (shift register C to latch C)
52
SAR
I
Serial row address input
53
SAC
I
Serial column address and mode control input
54
SCAD
I
Serial address clock input
55
RE
I
RAM-enable input (also latches the addresses)
7, 13, 19,
30, 36, 42
VDD2
Data output power supply (+ 5 V)
8, 14, 20,
29, 35, 41
VSS2
Data output power supply (GND)
24, 56
VDD1
Memory power supply (+ 5 V), must be connected to VDD2
25, 57
VSS1
Memory power supply (GND), must be connected to VSS2
61
OPM
Test function (for factory use only)
Semiconductor Group
Function
Serial data output for port A
Serial data input for port C
8
1998-01-30
SDA 9253
VDD1
VDD2
VSS1
VSS2
SQB 0
12
SQB 11
OEB
SCB
SCA
12
SDC 0
Shift
Register C
Shift
Register B
16 x 12
16 x 12
SDC 11
Shift
Register A
16 x 12
Latch B
Latch C
16 x 12
OEA
SQA0
12
SQA11
Latch A
16 x 12
16 x 12
16 x 12
R
o
w
212
D
e
c
o
d
e
r
16 x 12
Memory Cell Arrays
212 x 64 Bit
to Latches
64
8
Column Address Decoder
6
Internal Memory Controller
RE
TF
WT
RB
RA
SAC
SAR SCAD
UEB07389
Figure 3
Block Diagram
Semiconductor Group
9
1998-01-30
SDA 9253
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
min.
max.
– 55
125
°C
Storage temperature
Tstg
Soldering temperature
Tsold
260
°C
Soldering time
tsold
10
s
Input/output voltage
VI/Q
–1
7
V
Test function input voltage
VI
–1
7
V
Power supply voltage
VDD
–1
7
V
Data out current (short circuit)
IQ
10
mA
Total power dissipation
Ptot
1.2
W
Power dissipation per output
PQ
60
mW
Remarks
For factory use only
Operating Range
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Supply voltage
VDD1
4.5
5.0
5.5
V
Supply voltage
VDD2
4.5
5.0
5.5
V
Supply voltage
VSS1
0
V
Supply voltage
VSS2
0
V
H-input voltage
VIH
2.0
6.5
V
L-input voltage
VIL
– 1.0
0.8
V
Ambient temperature
TA
0
70
°C
Semiconductor Group
25
10
1998-01-30
SDA 9253
DC Characteristics
VDD = 5 V ± 10 %; TA = 0 to 70 °C
Parameter
Symbol
Limit Values
min.
typ.
Unit
Test Condition
V
At normal operation the
pin OPM has to be
connected to 1/2 VDD1
OPM level or left
unconnected.
max.
Test enable input
high voltage
VIH OPM
Test disable input
low voltage
VIL OPM – 10 % 1/2 VDD1 + 10 % V
See test enable input high
voltage
H-output voltage
VQH
V
IOUT = – 2.5 mA
L-output voltage
VQL
0.4
V
IOUT = 2.1 mA
Input leakage current
II (L)
– 10
10
µA
0 V ≤ VI ≤ 6.5 V
– 10
10
µA
OEA = OEB = VIH
Average supply current ICCa
200
mA
(tSC port A = tSC min)
(tSC port B = 2 tSC min)
(tSC port C = 2 tSC min)
(tRC = tRC min)
ICCa depends on cycle rate
and on output loading.
Specified values are
measured with open
output.
Standby supply current ICCb
5
mA
(RE = OEA = OEB = VDD1)
tSC (SCA, SCB, SCAD) =
max. (tSC)
Output leakage current IQ (L)
Semiconductor Group
4.5
5.5
2.4
11
1998-01-30
SDA 9253
AC Characteristics
VDD = 5 V ± 10 %; TA = 0 to 70 °C
Parameter
Symbol
Limit Values
min.
typ.
Unit
Test Condition
max.
Memory read or
write cycle time
tRC
240
100000 ns
Operation with tRC ≥ tRCmin
ensures that 8-bit serial
data are shifted out within
one RE cycle taking
tSC = tSCmin.
See diagram 2, 3, 4, 6
RE low time
tRE
100
100000 ns
See diagram 2, 3, 4, 6
Serial port cycle
time
tSC
30
100000 ns
See diagram 2 – 6
RE precharge time
tRP
100
ns
See diagram 2, 3, 4, 6
Address setup time
tAS
5
ns
See diagram 2, 3, 4, 6
Address hold time
tAH
6
ns
See diagram 2, 3, 4, 6
SCAD to RE
set-up time
tROS
3
ns
See diagram 2, 3, 4, 6
RE to SCAD
hold time
tROH
10
ns
See diagram 2, 3, 4, 6
RE to RA or RB
delay time
tRRD
90
ns
tRRD and tRRL are restrictive
operating parameters only
in memory read transfer
cycles.
See diagram 2, 3
RA or RB to RE
lead time
tRRL
– 30
ns
See RE to RA or RB delay
time.
See diagram 2, 3
RA to SCA
RB to SCB
set-up time
tRSS
0
ns
See diagram 2, 3
RA or RB
pulse width
tRPW
10
ns
See diagram 2, 3
RA to SCA
RB to SCB
hold time
tRSH
15
ns
See diagram 2, 3
Semiconductor Group
12
1998-01-30
SDA 9253
AC Characteristics (cont’d)
VDD = 5 V ± 10 %; TA = 0 to 70 °C
Parameter
Symbol
Limit Values
min.
WT to RE lead time
tWRL
typ.
Unit
Test Condition
ns
tWRL and tRWL are restrictive
max.
30
operating parameters only
in memory write transfer
cycles. In that case tWRL
applies if the write transfer
from shifter C to latch C
occurs before the rising
edge of RE. Otherwise tRWL
has to be satisfied.
See diagram 4
RE to WT lead time
tRWL
50
Output buffer turnoff delay
tOFF
0
WT to SCB delay
time
tWTD
WT to SCB lead
time
ns
See WT to RE lead time
ns
tOFF (max) defines the time
at which the output
achieves the open-circuit
condition and is not
referenced to output
voltages levels.
0
ns
See diagram 4
tWTL
15
ns
See diagram 4
WT pulse width
tWTP
10
ns
See diagram 4
OEA to output A
access time
tOAA
25
ns
See diagram 2, 5
OEB to output B
access time
tOBA
25
ns
See diagram 3, 5
Access time from
SCA
tCAA
25
ns
See diagram 2
Access time from
SCB
tCBA
25
ns
See diagram 3
Data input set-up
time to SCB
tDS
5
ns
See diagram 5
Data input hold time tDH
to SCB
6
ns
See diagram 5
Semiconductor Group
20
13
1998-01-30
SDA 9253
AC Characteristics (cont’d)
VDD = 5 V ± 10 %; TA = 0 to 70 °C
Parameter
Symbol
Limit Values
min.
typ.
Unit
Test Condition
16
ms
Either 256 refresh cycles or
read/write cycles on 212
consecutive row addresses
have to be performed
within the 16 ms interval to
maintain data
10
ns
Transition times are
measured between VIH and
VIL.
See diagram 1
max.
Refresh period
tREF
Transition time
(rise/fall)
tT
2
L-serial clock time
tSCL
10
ns
See diagram 2
H-serial clock time
tSCH
10
ns
See diagram 2
Hold time from SCA tCAH
6
ns
See diagram 2
Hold time from SCB tCBH
6
ns
See diagram 3
Input capacitance
(SCA, SCB)
CI 1
7
pF
f = 1 MHz
Input capacitance
(all other pins)
CI 2
5
pF
f = 1 MHz
Output capacitance
(SQA 0-11,
SQB 0-11)
CQ
7
pF
f = 1 MHz
Semiconductor Group
14
1998-01-30
SDA 9253
Operation Truth Table
RE Cycle N
SCAD
SAR
RE Cycle N + n, n = 1, 2, 3 …
SAC
Mode
M0
M1
OEA
OEB
SCA
SCB
RA
RB
WT
Operation
X
X
Read transfer from
memory to shifter A
X
Read transfer from
memory to shifter B
RA0…RA
7
CA0…CA
5
L
L
X
X
X
X
RA0…RA
7
CA0…CA
5
H
L
X
X
X
X
X
RA0…RA
7
CA0…CA
5
L
H
X
X
X
X
X
X
X
X
H
H
X
X
X
X
X
X
X
Refresh with
internal row address
X
X
X
X
X
L
X
X
X
X
X
Serial read port A
X
X
X
X
X
X
L
X
X
X
X
Serial read port B
X
X
X
X
X
X
X
X
X
X
X
Serial read port C
Write transfer from
shifter C to memory
Note: X = Don’t care
Row address, column address and mode bits have to be
V(TF)= 1/2 VDD1 (TF) or not connected defined in RE cycle N in order to become effective in RE
cycle N + 1
Semiconductor Group
15
1998-01-30
SDA 9253
3V
VIH
VIL
0V
tT
Input conditions : VIH = 2.0 V
VIL = 0.8 V
t T = 3 ns
VQH
HIGH Z
VQL
Output conditions : VOH = 2.4 V
VOL = 0.4 V
Output loading:
SQ
433 Ω
1.31 V
30 pF
UED10454
Diagram 1
AC-Timing Measuring Conditions
Semiconductor Group
16
1998-01-30
SDA 9253
t RC
t RE
t RP
RE
t ROH
t ROS
t SCH
t SC
SCAD
t SCL
t AH
t AS
SAR
RA6
RA7
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA0
RA1
SAC
L
L
CA0
CA1
CA2
CA3
CA4
CA5
M0
M1
CA0
CA1
2
3
4
t RRD
t RSS
RA
t RRL
t RPW
t RSH
OEA
t SCH
t SC
SCA
t CAH
t SCL
SQA(0-11)
13
14
t OAA
15
16
1
UET07391
t CAA
Diagram 2
Read Transfer Memory to Port A
Semiconductor Group
17
1998-01-30
SDA 9253
t RC
t RE
t RP
RE
t ROH
t ROS
t SC
SCAD
t AH
t AS
SAR
RA6
RA7
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA0
RA1
SAC
H
L
CA0
CA1
CA2
CA3
CA4
CA5
M0
M1
CA0
CA1
1
2
3
4
t RRD
t RSS
RB
t RRL
t RPW
t RSH
OEB
t SC
SCB
t CBH
SQA(0 - 11)
13
14
t OBA
15
16
UET07392
t CBA
Diagram 3
Read Transfer Memory to Port B
Semiconductor Group
18
1998-01-30
SDA 9253
t RC
t RE
t RP
RE
t ROH
t ROS
t SCH
t SC
SCAD
t SCL
t AH
t AS
SAR
RA6
RA7
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA0
RA1
SAC
L
H
CA0
CA1
CA2
CA3
CA4
CA5
M0
M1
CA0
CA1
t WRL
t RWL
WT
t WTD
t WTD
t WTP
t WTP
t WTL
t WTL
SCB
t SC
t SC
t DH
t DH
t DS
t DS
SDC(0 - 11)
15
16
1
15
2
16
1
2
UET07393
Diagram 4
Write Transfer from Port C to Memory
Semiconductor Group
19
1998-01-30
SDA 9253
Serial Read Operation Port A
t SC
t SCH
SCA
t CAA
t CAH
t SCL
OEA
t OAA
SQA(0 - 11)
t OFF
Valid Data
Valid Data
Serial Read Operation Port B
t SC
Valid Data
t SCH
SCB
t CBA
t SCL
t CBH
OEB
t OBA
SQB(0 - 11)
t OFF
Valid Data
Valid Data
Serial Write Operation Port C
t SC
Valid Data
t SCH
SCB
t DS
SDC(0 - 11)
t DH
t SCL
Valid Data
Valid Data
Valid Data
UET07394
Diagram 5
Semiconductor Group
20
1998-01-30
SDA 9253
t RC
t RE
t RP
RE
t ROH
t ROS
t SC
SCAD
t AH
t AS
SAR
RA6
RA7
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA0
RA1
SAC
H
H
CA0
CA1
CA2
CA3
CA4
CA5
M0
M1
CA0
CA1
UED02050
Diagram 6
Refresh with External Row Address
Semiconductor Group
21
1998-01-30
SDA 9253
Application Circuit
For best performance and operation within the specified AC parameter limits it is mandatory to use
separate decoupling capacitors for VSS1/VDD1 and VSS2/VDD2 with VSS1 shorted to VSS2 and VDD1
shorted to VDD2 on the board as shown in figure below.
Decoupling capacitors C1 and C2 of low inductance multilayer type (at least 0.1 µF) should be used.
To avoid malfunction or even permanent damage of the device it is strongly recommended not to
use any other supply configuration.
C
42 41
36 35
30
29
C
56
57
25
24
SDA 9253
C
20
19
7 8
13 14
VSS
C
VDD
UES07395
Figure 4
Semiconductor Group
22
1998-01-30
SDA 9253
Application Information
Digital Storage of a TV Field
As standard for digital TV systems, CCIR recommendation 601 defines a field of 288 lines with 720
pixels per line. The sampling frequency is 13.5 MHz with a resolution of 8 bit per pixel.
Information is stored in 3 different channels: one channel for luminance (Y), two channels for
chrominance (U and V).
The bandwidth ratio between the different channels is either Y:U:V = 4:1:1, 4:2:2 or 4:4:4 depending
on the coding method.
The following table shows the memory requirements for the field buffer and the number of memory
chips when the SDA 9253 and the SDA 9251 are used.
Table 1
Memory Requirements and Number of Memory Chips for a Digital TV-Field Buffer
Y:U:V
Clock Rate
13.5 MHz
Number of Required
Memory Devices
Bus Width
4:1:1
2.37 Mbit
1 SDA 9253
12 bit
4:2:2
3.16 bit
1 SDA 9253 +
1 SDA 9251
16 bit
4:4:4
4.75 bit
2 SDA 9253
24 bit
A typical application for the SDA 9253 is as field memory device in the Siemens MEGAVISION
system. The memory capacity of the SDA 9253 is 3 times that of SDA 9251 and therefore able to
substitute 3 SDA 9251. For a 4:1:1 sampling format there is need for 1 device in an application
without Line Flicker Reduction and 2 devices for an application with Line Flicker Reduction (see
figure).
Semiconductor Group
23
1998-01-30
SDA 9253
4
SDA9251X
YOUT
Y IN
3ADC
+
CSG
12
Picture
Processor 2
SDA 9253
Display
Processor
Field Mixer
16
16
U OUT
U IN
12
SDA 9206
SDA 9290
SDA 9253
SDA 9270
V IN
SDA 9280
VOUT
4
SDA 9251X
SYNC
SYNC
MSC3
SDA 9220
SYNC OUT
UEB07396
Figure 5
MEGAVISION Block Diagram of Line Flicker Reduction
Semiconductor Group
24
1998-01-30
SDA 9253
Package Outlines
GPM05250
P-MQFP-64-1
(Plastic Metric Quad Flat Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
25
Dimensions in mm
1998-01-30