IRF IRFIB7N50LPBF

PD - 95750
IRFIB7N50LPbF
SMPS MOSFET
Applications
• Zero Voltage Switching SMPS
• Telecom and Server Power Supplies
• Uninterruptible Power Supplies
• Motor Control applications
• Lead-Free
HEXFET® Power MOSFET
VDSS RDS(on) typ. Trr typ. ID
500V
85ns
320mΩ
Features and Benefits
• SuperFast body diode eliminates the need for external
diodes in ZVS applications.
• Lower Gate charge results in simpler drive requirements.
• Enhanced dv/dt capabilities offer improved ruggedness.
• Higher Gate voltage threshold offers improved noise
immunity.
6.8A
TO-220 Full-Pak
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V
Max.
6.8
Units
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
4.3
A
IDM
27
Pulsed Drain Current
PD @TC = 25°C Power Dissipation
c
VGS
Linear Derating Factor
Gate-to-Source Voltage
dv/dt
TJ
Peak Diode Recovery dv/dt
Operating Junction and
TSTG
Storage Temperature Range
e
46
W
0.37
±30
W/°C
V
24
-55 to + 150
V/ns
°C
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
300 (1.6mm from case )
10lb in (1.1N m)
x
Diode Characteristics
Symbol
Parameter
x
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
6.8
ISM
(Body Diode)
Pulsed Source Current
–––
–––
27
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
1.5
V
trr
Reverse Recovery Time
–––
85
130
ns
–––
130
200
c
Conditions
MOSFET symbol
A
showing the
integral reverse
D
G
p-n junction diode.
TJ = 25°C, IS = 6.8A, VGS = 0V
TJ = 25°C, IF = 6.8A
TJ = 125°C, di/dt = 100A/µs
f
Qrr
Reverse Recovery Charge
–––
280
420
–––
570
860
nC TJ = 25°C, IS = 6.8A, VGS = 0V
TJ = 125°C, di/dt = 100A/µs
IRRM
Reverse Recovery Current
–––
5.9
8.9
A
ton
Forward Turn-On Time
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f
f
S
f
TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
1
8/23/04
IRFIB7N50LPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
V(BR)DSS
∆V(BR)DSS/∆TJ
RDS(on)
VGS(th)
IDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
RG
500
–––
–––
3.0
–––
–––
–––
–––
–––
–––
0.44
0.32
–––
–––
–––
–––
–––
0.88
–––
–––
0.38
5.0
50
2.0
100
-100
–––
Conditions
V
VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
VGS = 10V, ID = 4.1A
Ω
V
VDS = VGS, ID = 250µA
µA VDS = 500V, VGS = 0V
mA VDS = 400V, VGS = 0V, TJ = 125°C
nA VGS = 30V
VGS = -30V
f = 1MHz, open drain
Ω
f
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Coss eff. (ER)
Parameter
Min. Typ. Max. Units
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
Effective Output Capacitance
4.7
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
23
36
47
19
2220
230
23
2780
63
140
100
–––
92
24
44
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
nC
ns
Conditions
VDS = 50V, ID = 4.1A
ID = 6.8A
VDS = 400V
VGS = 10V, See Fig. 7 & 16
VDD = 250V
ID = 6.8A
RG = 9.0Ω
VGS = 10V, See Fig. 11a & 11b
VGS = 0V
VDS = 25V
ƒ = 1.0MHz, See Fig. 5
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 400V, ƒ = 1.0MHz
f
f
pF
VGS = 0V,VDS = 0V to 400V
g
(Energy Related)
Avalanche Characteristics
Symbol
EAS
IAR
EAR
Parameter
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
c
d
c
Typ.
–––
–––
–––
Max.
550
6.8
4.6
Units
mJ
A
mJ
Typ.
Max.
Units
–––
–––
2.69
65
°C/W
Thermal Resistance
Symbol
RθJC
RθJA
Parameter
Junction-to-Case
Junction-to-Ambient
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 12).
‚ Starting TJ = 25°C, L = 24mH, RG = 25Ω,
IAS = 6.8A, (See Figure 14).
ƒ ISD ≤ 6.8, di/dt ≤ 650A/µs, VDD ≤ V(BR)DSS,
dv/dt = 24V/ns, TJ ≤ 150°C.
2
„ Pulse width ≤ 300µs; duty cycle ≤ 2%.
… Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff.(ER) is a fixed capacitance that stores the same energy
as C oss while VDS is rising from 0 to 80% VDSS.
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IRFIB7N50LPbF
100
100
10
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
5.0V
1
5.0V
0.1
10
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
5.0V
5.0V
1
≤60µs PULSE WIDTH
≤60µs PULSE WIDTH
Tj = 150°C
Tj = 25°C
0.01
0.1
0.1
1
10
100
0.1
V DS, Drain-to-Source Voltage (V)
10
100
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (Α)
1
TJ = 175°C
10
T J = 25°C
1
VDS = 50V
≤60µs PULSE WIDTH
0.1
2.5
ID = 6.8A
VGS = 10V
2.0
1.5
1.0
0.5
0.0
3
4
5
6
7
8
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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-60 -40 -20
0
20
40
60
80 100 120 140 160
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
vs. Temperature
3
IRFIB7N50LPbF
100000
10
C oss = C ds + C gd
10000
8
Energy (µJ)
C, Capacitance(pF)
12
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
Ciss
1000
Coss
6
4
100
2
Crss
0
10
1
10
100
0
1000
VDS, Drain-to-Source Voltage (V)
50 100 150 200 250 300 350 400 450 500 550
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 6. Typ. Output Capacitance
Stored Energy vs. VDS
12.0
100.00
VDS= 400V
10.0
ISD, Reverse Drain Current (A)
VGS, Gate-to-Source Voltage (V)
ID= 6.8A
8.0
6.0
4.0
2.0
10.00
T J = 150°C
1.00
T J = 25°C
0.10
VGS = 0V
0.0
0.01
0
10
20
30
40
50
60
QG Total Gate Charge (nC)
Fig 7. Typical Gate Charge vs.
Gate-to-Source Voltage
4
70
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VSD, Source-to-Drain Voltage (V)
Fig 8. Typical Source-Drain Diode
Forward Voltage
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IRFIB7N50LPbF
7
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
6
10
100µsec
ID, Drain Current (A)
ID, Drain-to-Source Current (A)
100
1
DC
0.1
5
4
3
2
1msec
Tc = 25°C
Tj = 150°C
Single Pulse
1
10msec
0
0.01
1
10
100
1000
10000
25
VDS, Drain-to-Source Voltage (V)
VGS
RG
100
125
150
Fig 10. Maximum Drain Current vs.
Case Temperature
RD
VDS
90%
D.U.T.
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 11a. Switching Time Test Circuit
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75
T C , Case Temperature (°C)
Fig 9. Maximum Safe Operating Area
V DS
50
10%
VGS
td(on)
tr
t d(off)
tf
Fig 11b. Switching Time Waveforms
5
IRFIB7N50LPbF
Thermal Response ( Z thJC )
10
1
D = 0.50
0.20
0.10
0.05
0.1
0.02
0.01
τJ
0.01
τJ
τ1
R2
R2
τ2
τ1
R3
R3
τ3
τ2
τC
τ
τ3
Ci= τi/Ri
Ci= i/Ri
SINGLE PULSE
( THERMAL RESPONSE )
0.001
R1
R1
Ri (°C/W)
0.2965
τi (sec)
0.001144
0.9847
1.4118
0.151939
1.705500
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
Fig 12. Maximum Effective Transient Thermal Impedance, Junction-to-Case
VGS(th) Gate threshold Voltage (V)
5.0
4.0
ID = 250µA
3.0
2.0
1.0
-75
-50
-25
0
25
50
75
100
125
150
T J , Temperature ( °C )
Fig 13. Threshold Voltage vs.Temperature
6
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IRFIB7N50LPbF
EAS , Single Pulse Avalanche Energy (mJ)
2500
ID
TOP
1.4A
1.7A
BOTTOM 6.8A
2000
1500
1000
500
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 14. Maximum Avalanche Energy
vs. Drain Current
15V
V(BR)DSS
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
20V
tp
tp
0.01Ω
A
I AS
Fig 15a. Unclamped Inductive Test Circuit
Fig 15b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
50KΩ
12V
10 V
.2µF
.3µF
D.U.T.
QGS
+
V
- DS
QGD
VG
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 16a. Gate Charge Test Circuit
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Charge
Fig 16b. Basic Gate Charge Waveform
7
IRFIB7N50LPbF
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
ƒ
+
‚
-
-
„
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 17. For N-Channel HEXFET® Power MOSFETs
8
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IRFIB7N50LPbF
TO-220 Full-Pak Package Outline
Dimensions are shown in millimeters (inches)
TO-220 Full-Pak Part Marking Information
E XAMP L E :
T H IS IS AN IR F I840 G
WIT H AS S E MB L Y
L OT COD E 3 43 2
AS S E MB L E D ON WW 24 199 9
IN T H E AS S E MB L Y L IN E "K "
P AR T N U MB E R
IN T E R N AT IONAL
R E CT IF IE R
L OGO
IR F I840G
924K
34
Note: "P" in assembly line
position indicates "Lead-Free"
AS S E MB L Y
L OT CODE
32
D AT E COD E
Y E AR 9 = 199 9
WE E K 24
L IN E K
TO-220AB FullPak package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.08/04
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