PHILIPS 74LVC00AD

INTEGRATED CIRCUITS
74LVC00A
Quad 2-input NAND gate
Product specification
Supersedes data of 1997 Aug 11
IC24 Data Handbook
1998 Apr 28
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74LVC00A
FEATURES
DESCRIPTION
• Wide supply range of 1.2V to 3.6V
• Complies with JEDEC standard no. 8-1A
• Inputs accept voltages up to 5.5V
• CMOS low power consumption
• Direct interface with TTL levels
• 5-volt tolerant inputs, for interfacing with 5-volt logic
The 74LVC00A is a high-performance, low power, low-voltage,
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature
allows the use of these devices as translators in a mixed 3.3 V/5 V
environment.
Schmitt-trigger action at all inputs makes the circuit tolerant for
slower input rise and fall times.
The 74LVC00A provides the 2-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr =tf 2.5 ns
SYMBOL
PARAMETER
tPHL
tPLH
Propagation delay
nA, nB to nY
CI
Input capacitance
CPD
CONDITIONS
CL = 50 pF;
VCC = 3.3 V
Power dissipation capacitance per gate
VI = GND to VCC1
TYPICAL
UNIT
3.0
ns
5.0
pF
28
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD VCC2 x fi (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL VCC2 fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
14-Pin Plastic SO
–40°C to +85°C
74LVC00A D
74LVC00A D
SOT108-1
14-Pin Plastic SSOP Type II
–40°C to +85°C
74LVC00A DB
74LVC00A DB
SOT337-1
14-Pin Plastic TSSOP Type I
–40°C to +85°C
74LVC00A PW
74LVC00APW DH
SOT402-1
PIN CONFIGURATION
LOGIC SYMBOL
1A
1
14
VCC
1B
2
13
4B
1Y
3
12
4A
2A
4
11
4Y
2B
5
10
3B
2Y
6
9
3A
GND
7
8
3Y
1
2
1A
1B
1Y
3
4
5
2A
2B
2Y
6
9
10
3A
3B
3Y
8
12
13
4A
4B
4Y
11
SY00035
SY00034
PIN DESCRIPTION
LOGIC SYMBOL (IEEE/IEC)
1
2
&
4
5
&
9
10
&
12
13
3
6
8
&
PIN
NUMBER
SYMBOL
NAME AND FUNCTION
1, 4, 9, 12
1A – 4A
2, 5, 10, 13
1B – 4B
3, 6, 8, 11
1Y – 4Y
Data outputs
7
GND
Ground (0 V)
14
VCC
Positive supply voltage
Data inputs
11
SV00378
1998 Apr 28
2
853-2017 19310
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74LVC00A
LOGIC DIAGRAM (ONE GATE)
FUNCTION TABLE
INPUTS
OUTPUTS
A
nA
Y
B
SV00379
nB
nY
L
L
H
L
H
H
H
L
H
H
H
L
NOTES:
H = HIGH voltage level
L = LOW voltage level
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
MAX
VCC
DC supply voltage (for max. speed performance)
2.7
3.6
V
VCC
DC supply voltage (for low-voltage applications)
1.2
3.6
V
VI
DC Input voltage range
0
5.5
V
VO
DC output voltage range
0
VCC
V
–40
+85
°C
0
0
20
10
ns/V
Tamb
Operating ambient temperature range in free-air
tr, tf
Input rise and fall times
VCC = 1.2 to 2.7V
VCC = 2.7 to 3.6V
ABSOLUTE MAXIMUM RATINGS1
Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
VCC
PARAMETER
CONDITIONS
DC supply voltage (for max. speed
performance)
RATING
UNIT
–0.5 to +6.5
V
mA
IIK
DC input diode current
VI 0
–50
–0.5 to +5.5
V
50
mA
–0.5 to VCC + 0.5
V
VI
DC input voltage
Note 2
IOK
DC output diode current
VO VCC or VO 0
VO
DC output voltage
Note 2
IO
DC output source or sink current
VO = 0 to VCC
IGND, ICC
Tstg
PTOT
DC VCC or GND current
Storage temperature range
Power dissipation per package
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
50
mA
100
mA
–65 to +150
°C
500
500
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Apr 28
3
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74LVC00A
DC CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
TYP1
MIN
VIH
HIGH level Input voltage
VIL
LOW level Input voltage
VCC = 1.2V
VCC
VCC = 2.7 to 3.6V
2.0
V
VCC = 1.2V
GND
V
VCC = 2.7 to 3.6V
VOH
O
HIGH level output voltage
VOL
LOW level output voltage
II
ICC
∆ICC
UNIT
MAX
0.8
VCC = 2.7V; VI = VIH or VIL; IO = –12mA
VCC*0.5
VCC = 3.0V; VI = VIH or VIL; IO = –100µA
VCC*0.2
VCC = 3.0V; VI = VIH or VIL; IO = –18mA
VCC*0.6
VCC = 3.0V; VI = VIH or VIL; IO = –24mA
VCC*0.8
VCC
V
VCC = 2.7V; VI = VIH or VIL; IO = 12mA
0.40
VCC = 3.0V; VI = VIH or VIL; IO = 100µA
0.20
VCC = 3.0V; VI = VIH or VIL; IO = 24mA
0.55
Input leakage current
VCC = 3
3.6V;
6V; VI = 5
5.5V
5V or GND
Quiescent supply current
VCC = 3.6V; VI = VCC or GND; IO = 0
Additional quiescent supply current
per input pin
VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0
V
"0 1
"0.1
"5
µA
0.1
10
µA
5
500
µA
NOTES:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
AC CHARACTERISTICS
GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF
LIMITS
SYMBOL
PARAMETER
tPHL/
tPLH
VCC = 3.3V ±0.3V
WAVEFORM
Propagation delay
nA, nB to nY
1, 2
VCC = 2.7V
VCC = 1.2V
MIN
TYP1
MAX
MIN
TYP
MAX
TYP
1.5
3.0
5.0
1.5
3.4
5.8
11
UNIT
ns
NOTE:
1. These typical values are at VCC = 3.3V and Tamb = 25°C.
AC WAVEFORMS
TEST CIRCUIT
VM = 1.5 V at VCC w 2.7 V
VM = 0.5 VCC at VCC < 2.7 V
VOL and VOH are the typical output voltage drop that occur with the
output load.
PULSE
GENERATOR
VI
nA, nB INPUT
S1
VCC
500Ω
VO
VI
2 < VCC
Open
GND
D.U.T.
RT
VM
CL
50pF
500Ω
GND
tPHL
tPLH
VOH
nY OUTPUT
VCC
VI
t 2.7V
VCC
2.7V – 3.6V
2.7V
Test
S1
tPLH/tPHL
Open
VM
SY00077
VOL
Waveform 2. Load circuitry for switching times.
SV00377
Waveform 1. Input (nA) to output (nY) propagation delays.
1998 Apr 28
4
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74LVC00A
SO14: plastic small outline package; 14 leads; body width 3.9 mm
1998 Apr 28
5
SOT108-1
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74LVC00A
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
1998 Apr 28
6
SOT337-1
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74LVC00A
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
1998 Apr 28
7
SOT402-1
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74LVC00A
DEFINITIONS
Data Sheet Identification
Product Status
Definition
Objective Specification
Formative or in Design
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Preliminary Specification
Preproduction Product
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Product Specification
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
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Date of release: 05-96
9397-750-04476