Stereo Decoder/Noise Blanker 1 Overview 1.1 Features TDA 4340X • Internal reference voltage source • Adjustment free oscillator with ceramic resonator 456 kHz • Pilot dependent mono/stereo switching with hysteresis P-DSO-20-1 • Stereo indicator output • Analogue control of mono/stereo change over (stereo noise control, SNC) • Pilot canceller (19 kHz) • Adjacent channel noise suppression (114 kHz) • MUTE facility • Analogue control of deemphasis (high cut control, HCC). • Stereo inputs for additional signal source at output amplifiers • Interference noise detector with integrated high-pass filter • (IF level signal or MPX input) • MPX input low-pass filter • Noise blanking at MPX demodulator outputs • Input and output level adjustable (resistor values) Type Ordering Code Package TDA 4340X Q67000-A5058 P-DSO-20-1 1.2 Application The TDA 4340X is an integrated circuit providing the stereo decoder function and noise blanking for FM car radio applications. Semiconductor Group 1 04.96 TDA 4340X 1.3 Pin Configuration (top view) P-DSO-20-1 Figure 1 Semiconductor Group 2 04.96 TDA 4340X 1.4 Pin Definitions and Functions Pin No. Function 1 Phase detector output, PLL loop filter 2 Oscillator pin (456 kHz) 3 Ground 4 Reference current pin, external reference resistor 5 Positive supply voltage 6 Interference detector input, noise detector input 7 Timing capacitor for monoflop (gate time) Low voltage applied turns off oscillator, phase detector, pilot detector, SNC and changes the time constant for HCC, noise gate monoflop 8 Hold capacitor for noise detector average level Low voltage applied mutes the stereo decoder output, noise level capacitor 9 Auxiliary input left, output amplifier left 10 Audio signal output left 11 Audio signal output right 12 Auxiliary input right, output amplifier right 13 HCC timing/hold capacitor, deemphasis right 14 HCC timing/hold capacitor, deemphasis left 15 Input for HCC voltage 16 Input for SNC voltage 17 Input for reference level control voltage (HCC and SNC) 18 Pilot indicator output, open collector, active low 19 Pilot detector output Low voltage applied switches the stereodecoder to mono state 20 Input for MPX signal Semiconductor Group 3 04.96 TDA 4340X 1.5 Functional Block Diagram Figure 2 Block Diagram Semiconductor Group 4 04.96 TDA 4340X 2 Circuit Description Power Supply, Reference Current A temperature stable, low noise reference voltage generator is used for better ripple rejection and for the generation of a reference current. This current is used as a time base for the deemphasis, the gate time of the pulse former, and the pilot cancellation, avoiding temperature and tolerance effects. MPX Input, MPX Filter Adjusting the value of the input resistor, the MPX input can be adapted to the output level of the FM demodulator. A 4-pole low-pass filter determines the bandwidth of the MPX signal. Voltage Controlled Oscillator, Phase Detector The 456 kHz oscillator and the frequency dividers are used as walsh function generators (suppression of 3rd order harmonics) for: – 38 kHz for the stereo decoder – 19 kHz inphase for phase detector and pilot cancellation – 19 kHz quadrature for the phase detector. The phase detector locks the on-chip 19 kHz signal to the pilot tone in the MPX signal at 90° phase. Pilot Detector, Pilot Indicator, Pilot Cancellation The voltage at the pilot detector output is proportional to the pilot tone input level. If that level is high enough, the pilot indicator output is activated and the pilot Cancellation turned on: a 19 kHz signal proportional to the voltage at the pilot detector output is added to the MPX signal with inverse polarity, cancelling the 19 kHz pilot tone. Interference Detector, Noise Detector, Pulse Former The signal from the interference input (MPX or field strength signal) passes a 4-pole high-pass to the noise blanking circuitry. The average noise level is stored on an external capacitor. The interference detector compares the actual noise level with that stored on the capacitor and triggers the pulse former if there is a significant difference. The pulse former generates a gate pulse for the HCC block. During that pulse time the outputs of the deemphasis circuit are switched to hold mode. Semiconductor Group 5 04.96 TDA 4340X 3 Electrical Characteristics 3.1 Absolute Maximum Ratings TA = – 40 °C to 85 °C Parameter PLL loopfilter Oscillator Reference current Supply voltage Noise detector input Noise gate monoflop Noise level capacitor Output amplifier left AF output left AF output right Output amplifier right Deemphasis right Deemphasis left HCC voltage SNC voltage Reference level voltage Pilot indicator output Pilot detector output MPX input Junction temperature Storage temperature Thermal resistance ESD voltage, HBM Symbol V1 I2 I4 V5 V6 V7 V8 V9 I10 I11 V12 V13 V14 V15 V16 V17 I18 V19 V20 Tj TS RthSA VESD Limit Values Unit min. max. 0 5 V –1 0.1 mA –1 0 mA 0 13.2 V 0 5 V 0 V 0 V5 V5 – 1.5 V 0 6 V –1 0.3 mA –1 0.3 mA 0 6 V 0 5 V 0 5 V 0 13.2 V 0 13.2 V 0 13.2 V 0 2 mA 0 V5 – 1.5 V 0 6 V – 40 150 °C – 40 125 °C 95 K/W 4 kV –4 Remarks 100 pF, 1500 Ω Note: Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Semiconductor Group 6 04.96 TDA 4340X 3.2 Operating Range Parameter Symbol VS TA Supply voltage Ambient temperature Limit Values Unit min. max. 7.5 13.2 V – 40 85 °C Note: In the operating range the functions given in the circuit description are fulfilled. 3.3 AC/DC Characteristics VS = 10 V, TA = 25 °C Parameter Symbol Limit Values min. typ. max. Unit Test Condition Supply current IS 15 20 mA Osc. ON Supply current IS 10 15 mA Osc. OFF, V7 = 1 V Total harmonic distortion THD 0.1 0.3 % f = 1 kHz Signal to noise ratio S/N 74 80 dB 20 Hz … 16 kHz, Stereo Channel separation 32 40 dB f = 1 kHz 1.7 Vpp 8 dB 660 mVrms f = 1 kHz, Stereo dB MPX input level Overdrive margin of input 4 AF output voltage Overdrive margin of output 6 9 AF output DC voltage 2.6 3 Difference of output voltage levels 3.4 V 1 dB Muting depth 80 100 DC offset at MUTE – 50 0 50 mV DC offset stereo ON/OFF – 30 0 30 mV Semiconductor Group dB 7 THD = 1 % THD = 1 % f = 1 kHz 04.96 TDA 4340X 3.3 AC/DC Characteristics (cont’d) VS = 10 V, TA = 25 °C Parameter Symbol Limit Values min. typ. Unit Test Condition max. Carrier and Harmonic Suppression a19 a38 a571) a761) 44 50 dB f = 19 kHz 44 50 dB f = 38 kHz 50 60 dB f = 57 kHz 50 60 dB f = 76 kHz fmod = 10 kHz a21) 60 65 dB fS = 2 × 10 kHz … 19 kHz fmod = 13 kHz a31) 60 a571) 70 Pilotsignal subcarrier Intermodulation 91 % Mono, 9 % pilot, ƒS = 1 kHz 75 dB fS = 3 × 13 kHz … 38 kHz 91 % Mono, 9 % pilot, ƒS = 1 kHz Traffic Radio f = 57 kHz dB fS = 1 kHz ± 23 Hz 91 % Mono, 9 % pilot, fm = 1 kHz, 5 % Traffic Radio Carrier (f = 57 kHz, fm = 23 Hz AM, m = 60 %) SCA (subsidiary communications authorization) f = 67 kHz a671) 70 dB fS = 9 kHz 81 % Mono, 9 % pilot, fm = 1 kHz, 10 % SCA carrier ACI (adjacent channel interference) f = 119 kHz f = 190 kHz Ripple rejection 1) a1141) a1901) 1) 60 80 dB 70 dB 70 dB V5 = 10 V, 100 mVrms, f = 1 kHz No subject of production testing. Semiconductor Group 8 04.96 TDA 4340X 3.3 AC/DC Characteristics (cont’d) VS = 10 V, TA = 25 °C Parameter Symbol Limit Values min. typ. max. 20 30 Unit Test Condition Mono/Stereo Control Pilot threshold voltage: – for Stereo ON – for Stereo OFF – hysteresis Stereo indicator output: – Pilot OFF – Pilot ON VPIL on VPIL off 5 1.5 14 3 V18 off I18 on mVrms mVrms dB VPIL on/VPIL off 0.5 10 V µA I18 = 1 mA V18 = 13.2 V External Control Voltages (active low) Threshold voltage for external mono control (pin 19) V19 thr 1 1.2 V Threshold voltage for MUTE (pin 8) V8 thr 1 1.5 V Threshold voltage V7 thr for VCO OFF (pin 7) 1 1.5 V Deemphasis Reference voltage V17 0.5 τmin 45 4.5 V Reference level 100 Hz 55 µs V17 = 3 V, V15 = 6 V, Control Range Minimum 50 Cdeemph = 6.8 nF Maximum τmax τdeemph = τnom V15 τdeemph = 1.5 × τnom V15 τdeemph = 2.7 × τnom V15 Semiconductor Group 135 150 165 µs V17 = 3 V, V15 = 0 V mV Cdeemph = 6.8 nF V17 = 3 V, Cdeemph = 6.8 nF V17 = 3 V, Cdeemph = 6.8 nF mV V17 = 3 V, Cdeemph = 6.8 nF V17 V17 – V17 – V17 – 220 170 120 V17 – V17 – V17 – 400 300 200 9 04.96 TDA 4340X 3.3 AC/DC Characteristics (cont’d) VS = 10 V, TA = 25 °C Parameter Symbol Limit Values min. typ. max. 13 15 17 Unit Test Condition µs V17 = 3 V, V15 = 6 V, V7 = 1 V Control Range (osc. OFF) Minimum τAM min Cdeemph = 6.8 nF Maximum τAM max 35 40 45 µs V17 = 3 V, V15 = 0 V, V7 = 1 V Cdeemph = 6.8 nF Stereo/Mono Blend Control Channel separation V16 Channel separation V16 Reference voltage V17 V17 – V17 – V17 – 140 115 90 V17 – V17 – V17 – 190 170 150 0.5 mV 15 dB sep. mV 6 dB sep. 4.5 V Oscillator Max. osc. frequency fosc max 0.7 1.0 2.0 % 100% × (fmax/456 kHz – 1) Min. osc. frequency fosc min – 2.0 – 1.0 – 0.7 % 100% × (fmin/456 kHz – 1) VCO gain ∆f/∆V1 – 13 – 10 –7 kHz/V Oscillator voltage V2 DC 3 4 5 V Oscillator swing V2 AC 800 1100 1400 mVpp ∆i/∆Φ1) 5 7.0 9 µA/rad R6 75 100 135 kΩ 80 100 120 kHz PLL PD gain Vpilot = 54 mVrms Noise Detector Input resistance Input high-pass filter fin, 6 – 3 dB Trigger threshold V6 min 10 mVrms V8 = V8 (V6 mean = 0), f6 = 200 kHz Trigger threshold V6 dyn 160 mVrms V8 = V8 (V6 mean = 50 mVrms), f6 = 200 kHz Maximum noise mean value V6maxmean 80 mVrms f6 = 200 kHz Semiconductor Group 10 04.96 TDA 4340X 3.3 AC/DC Characteristics (cont’d) VS = 10 V, TA = 25 °C Parameter Symbol Limit Values min. Suppression pulse duration I13, I141) Pulse threshold V6 burst1) – 50 Test Condition max. µs 40 Input offset current 1) typ. Unit 0 50 nA 130 200 mVpp 100 kHz single burst repetition rate 100 Hz both polarities Cin, 6 = 1 nF No subject of production testing. Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and the given supply voltage. Semiconductor Group 11 04.96 TDA 4340X Figure 3 Test Circuit Semiconductor Group 12 04.96 TDA 4340X Figure 4 Application Circuit Semiconductor Group 13 04.96 TDA 4340X Diagrams Figure 5 Definition of Phase Detector Gain Figure 6 Phase Detector Gain Semiconductor Group 14 04.96 TDA 4340X 4 Package Outlines GPS05094 P-DSO-20-1 (Plastic Dual Small Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 15 Dimensions in mm 04.96