Supertex inc.
Application Note
Low-Threshold TN/TP Series MOSFETs:
Structure, Performance and Applications
Since an increasing amount of attention is being focused
on system interface from low-level logic, the need for higher
current and/or low on-resistance at drive levels of only 3.0
- 5.0V has become a major concern. Supertex has always
known of the importance of the gate drive consideration
and has been offering N-channel low-threshold devices with
threshold voltages of 2.4 and 1.6V for many years. Additionally, standard and low-threshold versions of P-channel
DMOS devices are available. To understand the reasons
that low-threshold processing requires very specialized
techniques, one needs to understand the DMOS structure.
DMOS Structure
Most double-diffused MOS (DMOS) structures have very
similar cross-section characteristics, as shown in Figure 1.
For conduction to occur, a channel of electrons is needed
between the gate and the source. This potential produces an
inversion layer called the channel. The depth of this layer is
the limiting factor in allowing current flow between the drain
and source terminal. The greater the voltage applied, the
deeper the induced channel; resulting in more current flow.
The voltage needed to invert the channel region is called the
threshold voltage VGS(th). However, when examining most
manufacturers’ databooks, one finds VGS(th) defined as the
voltage needed to produce a specified drain current (ID).
This differs from the theoretical definition of knowing when
a channel is produced, which is of little interest to MOSFET
users. Comparing VGS(th) at the same ID simplifies the analysis of databook parametric guarantees, allowing the designer to compare the product to actual needs.
n+ p+
Figure 1: Double Diffused MOS (DMOS)
The control of the threshold voltage is dependent on many
factors, such as dopant concentration, gate-to-silicon work
function and surface change. The greater the body dopant
concentration, the larger the applied voltage needed to produce a channel, which translates to a higher threshold volt-
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age. One method of reducing threshold voltage is to reduce
the body dopant concentration until the required VGS(th) is
met. This technique by itself is dangerous because it degrades other device parameters. The first and most important of these is drain-source breakdown (BVDSS), which is a
result of certain conditions, most commonly punch-through.
Punch-through is defined as the drain voltage needed to
create an electric field connecting the drain and source, as
shown in Figure 2, at voltages less than the actual BVDSS
Electric Field
Figure 2: Electric Field Connecting Drain and Source
The susceptibility to punch-through increases dramatically
as the body dopant concentration is lowered. There is an optimum body dopant level that is needed in order to stay away
from the punch-through mechanism, but this concentration
is too high for low thresholds. This is one of the reasons why
P-channel devices typically have higher thresholds, because
the optimum body dosage is higher than N-channel FETs.
Another technique, used by some manufacturers, is to lower
threshold by reducing the gate oxide thickness. Again, there
are trade-offs using this method: (1) The input capacitance
increases which will effect the switching speed efficiency
and (2) the maximum gate voltage rating is decreased, making it more susceptible to input voltage spikes.
Supertex has developed a proprietary technique to successfully lower threshold voltage without these major trade-offs.
This method mainly depends on modifying the diffusion
profile and altering the charge distribution to produce lowthreshold N- and P-channel devices. This process, which
makes use of Supertex’s interdigitated design structure, allows typical thresholds of 1.1V for N-channel and 1.8V for
P-channel, DMOS devices.
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VGS(th) - Gate threshold voltage
VDS = VGS, ID = 250µA
VDS = VGS, ID = 10mA
ID(ON) - On-state drain current
VDS > ID(ON) x RDS(ON) max
VGS = 10V
VDS = 25V, VGS = 10V
VDS = 25V, VGS = 5.0V
RDS(ON) - Drain-to-source
VGS = 10V, ID = 4.0A
VGS = 10V, ID = 4.0A
VGS = 5.0V, ID = 1.0A
Table 1. Comparison between MOSFET and standard threshold Supertex device
An added benefit of Supertex’s design is the lower input
capacitance achieved by the interdigitated geometry, rather than the more conventional closed cell approach. Less
charge is needed to control the device input. Therefore, it
can be concluded that a lower threshold device will start
conducting earlier for a given gate drive and allow control of
larger drain current than a higher threshold device.
the threshold voltage value because quiescent gate voltage
conditions are usually at least a few volts above the VGS(th)
value. Figure 3 shows the transfer characteristics of a standard-threshold and a low-threshold device. For example, if
the drain current requirement is 100mA, TN2524N8 will typically need VGS = 1.75V and VN2224N3 will require 2.4V to
achieve this value. In case a 2.4V drive is not available, as
in many applications, a VN2224N3 will be incapable of functioning in the circuit. In spite of the TN2524N3 die being 3.6
times smaller than the VN2224, the TN2524N8 performance
is far superior at low gate to source voltages.
The availability of such low-threshold DMOS devices insures
the performance needed to be driven by low level logic systems, in which the maximum voltage available is only 3-5V.
Performance Advantages
With the first device shipped in 1982, Supertex was the
pioneer in low-threshold DMOS FET technology and still
maintains a performance edge over other manufacturers.
Supertex currently supplies the lowest threshold MOSFETs
in the industry. A threshold voltage of 1.0V for N-channel as
well as for P-channel clearly supports this claim.
ID (mA)
Supertex measures threshold voltages at ID = 1.0mA, 2.5mA,
and 10mA for small, medium and large-sized devices, respectively. Although some manufacturers use test conditions as
low as ID = 250µA for large devices, Supertex devices, in comparison, still have lower values of threshold voltages at higher
values of ID. See Table 1 for a comparison between a popular
MOSFET and a standard-threshold Supertex device.
VGS (volts)
Figure 3: Typical Transfer Characteristics
A true comparison can be made by normalizing the value of
the ID test condition. The threshold voltage for VN2210N3
will be lower than 2.4V (max) when it is tested at ID = 250µA.
Supertex’s test conditions therefore portray a realistic picture of the device’s capabilities at low VGS conditions.
When confronted by low gate drive voltage, a designer basically has two choices:
Approach 1:
Use a large industry-standard-threshold device to obtain
the required low RDS(ON), maximum and ID(ON), minimum
values. ID(ON) can be obtained from the transfer characteristics and RDS(ON) values will be read off the typical
saturation or output characteristics.
The threshold voltage is an important indicator of performance at low VGS conditions because a device that starts
conducting at a very low bias will exhibit good characteristics
under such conditions. In fact, RDS(ON) (max) and ID(ON) (min)
at low VGS conditions are much more important than just
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Power Supply/
Battery Charger
with Float
Equalize Mode
VGS = 9.3V Max
6.0V Min
Control Circuit
Figure 4: Motor of a Fluid Injection Pump
Approach 2:
Compared to the device used in Approach 1, use a relatively small (die size), low-threshold device to achieve
the desired ID(ON) and RDS(ON) at the given minimum gateto-source voltage.
The combined effect of low-threshold voltage and low-input
capacitance is ease of drive, which is a key consideration
in most circuits employing MOSFETs. What better trait can
a designer expect than a small amount of charge controlling high voltages and large currents? These low-threshold
FETs from Supertex are ideally suited to interface low-voltage logic to the outside world.
Comparison of Approach 1 and 2
1. Large die always have larger parasitic capacitance and
consequently slower switching speeds. This could pose
a restriction in many applications, where limited gate
drive charging current is available.
Low-threshold MOSFETs play a key role in circuit design
whenever there is a low gate-to-source voltage situation.
Conventional devices are often very inefficient and sometimes unusable in some applications as follows:
2. Large die must be accommodated in large packages,
and this may result in unnecessary waste of board
space. For example, the total volume occupied by a TO220 package including stand off could be 8 to 10 times
more than a TO-92 package.
►► Handheld, battery-operated equipment requiring satisfactory operation at low/end-of-discharge voltages.
This is necessary for complete utilization of battery
energy. Inadequate turn-on of a FET can cause two
problems: A) loss of control signal or data; or B) loss of
power due to resistive losses. Supertex TN/TP series
devices are being used for a variety of data acquisition
and remote-control applications.
3. A judicious choice using smaller die in a smaller package can result in considerable cost savings. With more
silicon and several times the raw material content for
packaging, a low-threshold TO-92 will definitely be a
much more cost-effective alternative.
►► Medical equipment with battery backup is another
popular application. Figure 4 shows the motor of a
fluid injection pump powered by the utility supply and
backed by a NiCad battery. The VGS = 6.0V condition
demands careful attention, because the RDS(ON) has to
be low in order to ensure a low drain to source voltage drop. A large voltage drop can: A) affect motor
performance, and B) cause high I2R losses, reducing
system efficiency and battery back-up time.
Supertex publishes RDS(ON), maximum, and ID(ON) minimum,
specifications at VGS = 5.0V (see Table 1). This data is very
useful to a designer because it is always desirable to rely on
guaranteed values instead of typical curves. Typical curves
are based on a high statistical probability of the majority of
devices closely meeting values on the curves. They do not
100% guarantee performance of all devices. Manufacturing
tolerances and some variations from one fabrication lot to
another are likely to cause lower than expected values of
these parameters. Depending entirely on curves tends to be
risky for production runs even if prototypes built earlier perform satisfactorily.
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►► Solid-state relays utilize optically-isolated drive
schemes for isolation purposes. Figure 5 shows a
commonly-used photovoltaic drive scheme. Usually a
low voltage is available to turn on the FET to meet the
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relay’s assured RDS(ON) specifications. Precautions are
taken to avoid excessive drive since the charge applied during turn-on must be quickly discharged during
turn-off. Turn-off circuitry is not shown in this simplified
►► Figure 6 shows a simple charge pump converting 5.0
to 12VDC. The key parameter for efficient functioning
of this circuit is RDS(ON) at VGS = 5.0V.
Diode Stack
12 VDC
Figure 6: Charge Pump Converting 5.0 to 12VDC
Figure 5: Photovoltaic Drive Scheme
Advances in low-threshold MOSFET technology offer several useful choices to a designer. Circuit designs for many
applications are simplified and use of components is minimized. Consequently, system complexity is reduced and reliability enhanced. All these benefits, combined with the costeffectiveness of the devices, make the low-threshold FETs
an excellent choice.
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//
Supertex inc.
©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
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