Supertex inc. VN10K N-Channel Enhancement-Mode Vertical DMOS FET Features ►► ►► ►► ►► ►► ►► ►► General Description Free from secondary breakdown Low power drive requirement Ease of paralleling Low CISS and fast switching speeds Excellent thermal stability Integral source-drain diode High input impedance and high gain This enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Applications ►► ►► ►► ►► ►► ►► Motor controls Converters Amplifiers Switches Power supply circuits Drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.) Ordering Information Product Summary Part Number Package Option Packing VN10KN3-G VN10KN3-G P002 TO-92 1000/Bag TO-92 2000/Reel BVDSS/BVDGS 60V VN10KN3-G P003 VN10KN3-G P005 Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. RDS(ON) IDSS (max) (min) 5.0Ω 750mA Pin Configuration VN10KN3-G P013 VN10KN3-G P014 -G denotes a lead (Pb)-free / RoHS compliant package. Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant. DRAIN SOURCE Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Gate-to-source voltage ±30V Operating and storage temperature -55 C to +150 C O O Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Typical Thermal Resistance Package θja TO-92 132OC/W Doc.# DSFP-VN10K B031411 GATE TO-92 Product Marking SiVN 1 0 K YYWW YY = Year Sealed WW = Week Sealed = “Green” Packaging Package may or may not include the following marks: Si or TO-92 Supertex inc. www.supertex.com VN10K Thermal Characteristics Package (continuous)† (pulsed) ID Power Dissipation @TC = 25OC IDR† IDRM 310mA 1.0A 1.0W 310mA 1.0A TO-92 ID Notes: † ID (continuous) is limited by max rated Tj . (VN0106N3 can be used if an ID (continuous) of 500mA is needed.) Electrical Characteristics (T A Sym Parameter BVDSS VGS(th) ΔVGS(th) IGSS = 25OC unless otherwise specified) Min Typ Max Units Drain-to-source breakdown voltage 60 - - V VGS = 0V, ID = 100µA Gate threshold voltage 0.8 - 2.5 V VGS = VDS, ID= 1.0mA Change in VGS(th) with temperature - -3.8 - Gate body leakage - - 100 - - 10 - - 500 0.75 - - - - 7.5 - - 5.0 - 0.7 - %/OC 100 - - mmho VDS = 10V, ID = 500mA IDSS Zero gate voltage drain current ID(ON) On-state drain current RDS(ON) ΔRDS(ON) Static drain-to-source on-state resistance Change in RDS(ON) with temperature GFS Forward transductance CISS Input capacitance - 48 60 COSS Common source output capacitance - 16 25 CRSS Reverse transfer capacitance - 2.0 5.0 t(ON) Turn-on time - - 10 t(OFF) Turn-off time - - 10 VSD Diode forward voltage drop - 0.8 Reverse recovery time - 160 trr Conditions mV/ C VGS = VDS, ID= 1.0mA O nA VGS = 15V, VDS = 0V VGS = 0V, VDS = 45V µA VGS = 0V, VDS = 45V, TA = 125°C A VGS = 10V, VDS = 10V Ω VGS = 5.0V, ID = 200mA VGS = 10V, ID = 500mA VGS = 10V, ID = 500mA pF VGS = 0V, VDS = 25V, f = 1.0MHz ns VDD = 15V, ID = 600mA, RGEN = 25Ω - V VGS = 0V, ISD = 500mA - ns VGS = 0V, ISD = 500mA Notes: 1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. Switching Waveforms and Test Circuit 10V INPUT 0V Pulse Generator 10% t(ON) td(ON) VDD OUTPUT 0V Doc.# DSFP-VN10K B031411 VDD 90% t(OFF) tr td(OFF) OUTPUT RGEN tf 10% 10% 90% RL INPUT D.U.T. 90% 2 Supertex inc. www.supertex.com VN10K Typical Performance Curves On-Resistance vs. Gate-to-Source Voltage BVDSS Variation with Temperature 100 VDS = 0.1V RDS(ON) (ohms) BVDSS (normalized) 1.1 1.0 10 0.9 -50 0 50 100 1.0 1.0 150 10 1.0 Output Conductance vs Drain Current Transfer Characteristics 1.0 VDS = 10V 300µs, 2% Duty Cycle, Pulse Test 0.6 GFS (mhos) ID (amperes) 0.8 100 VGS (volts) Tj (OC) 0.4 VDS = 25V 80µs, 1% Duty Cycle, Pulse Test Reduction Due to Heating 0.1 0.2 0 0 2.0 4.0 6.0 8.0 0.01 0.01 10 0.1 1.0 VGS (volts) ID (amperes) Capacitance vs. Drain-to-Source Voltage Transconductance vs Gate-Source Voltage 50 250 200 30 150 Gfs (m ) 40 Ω C (picofarads) CISS 20 COSS 10 VDS = 10V 3000µs, 2% Duty Cycle Pulse Test 100 50 CRSS 0 0 10 20 30 40 0 0 50 VDS (volts) Doc.# DSFP-VN10K B031411 2.0 4.0 6.0 8.0 10 VGS (volts) 3 Supertex inc. www.supertex.com VN10K Typical Performance Curves (cont.) Output Characteristics 1.0 VGS = 10V 8V Saturation Characteristics 1.0 7V 0.8 VGS = 10V 0.8 8V ID (amperes) ID (amperes) 6V 0.6 5V 0.4 7V 9V 6V 0.6 5V 0.4 4V 0.2 4V 0.2 3V 3V 2V 0 0 10 20 30 2V 40 0 50 0 2.0 4.0 6.0 8.0 10 VDS (volts) VDS (volts) Transconductance vs. Drain Current Power Dissipation vs. Case Temperature 2.0 250 200 PD (watts) Ω GFS (m ) 150 100 VDS = 10V 300µs, 2% Duty Cycle, Pulse Test 50 0 0 200 400 600 800 ID (mA) 0 1000 0 25 50 75 100 125 150 TC (OC) Maximum Rated Safe Operating Area 10 Switching Waveform Output Voltage (volts) 10 TC = 25OC 1.0 5.0 0 TO-92 (DC) Input Voltage (volts) ID (amperes) TO-92 1.0 0.1 0.01 1.0 Doc.# DSFP-VN10K B031411 10 VDS (volts) 100 15 10 5.0 0 0 1000 10 20 30 40 50 t – Time (ns) 4 Supertex inc. www.supertex.com VN10K 3-Lead TO-92 Package Outline (N3) D A Seating Plane 1 2 3 L c b e1 e Side View Front View E1 E 1 3 2 Bottom View Symbol Dimensions (inches) A b c D E E1 e e1 L MIN .170 .014† .014† .175 .125 .080 .095 .045 .500 NOM - - - - - - - - - MAX .210 .022† .022† .205 .165 .105 .105 .055 .610* JEDEC Registration TO-92. * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc.#: DSPD-3TO92N3, Version E041009. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-VN10K B031411 5 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com