PHP55N03LTA;PHB55N03LTA; PHD55N03LTA N-channel enhancement mode field-effect transistor Rev. 02 — 2 August 2001 Product data 1. Description N-channel logic level field-effect power transistor in a plastic package using TrenchMOS™1 technology. Product availability: PHP55N03LTA in a SOT78 (TO-220AB) PHB55N03LTA in a SOT404 (D2-PAK) PHD55N03LTA in a SOT428 (D-PAK). 2. Features ■ Low on-state resistance ■ Fast switching. 3. Applications ■ Computer motherboard high frequency DC to DC converters. 4. Pinning information Table 1: Pinning - SOT78, SOT404, SOT428 simplified outline and symbol Pin Description 1 gate (g) 2 drain (d) 3 source (s) mb mounting base, connected to drain (d) Simplified outline Symbol mb mb d mb [1] g MBB076 2 2 1 1 3 MBK116 Top view 3 MBK091 MBK106 1 2 3 SOT78 (TO-220AB) SOT404 (D2-PAK) [1] It is not possible to make connection to pin 2 of the SOT404 and SOT428 packages. 1. TrenchMOS is a trademark of Royal Phillips Electronics. SOT428 (D-PAK) s PHP55N03LTA series Philips Semiconductors N-channel enhancement mode field-effect transistor 5. Quick reference data Table 2: Quick reference data Symbol Parameter Conditions Typ Max Unit VDS drain-source voltage (DC) Tj = 25 to 175 °C - 25 V ID drain current (DC) Tmb = 25 °C; VGS = 5 V - 55 A Ptot total power dissipation Tmb = 25 °C - 85 W Tj junction temperature - 175 °C RDSon drain-source on-state resistance VGS = 10 V; ID = 25 A; Tj = 25 °C 11 14 mΩ VGS = 5 V; ID = 25 A; Tj = 25 °C 15 18 mΩ Min Max Unit 6. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VDS drain-source voltage (DC) Tj = 25 to 175 °C - 25 V VDGR drain-gate voltage (DC) Tj = 25 to 175 °C; RGS = 20 kΩ - 25 V VGS gate-source voltage (DC) - ±15 V VGSM gate-source voltage tp ≤ 50 µs pulsed; duty cycle 25%; Tj ≤ 150 °C - ±20 V ID drain current (DC) Tmb = 25 °C; VGS = 5 V; Figure 2 and 3 - 55 A Tmb = 100 °C; VGS = 5 V; Figure 2 - 38 A IDM peak drain current Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 - 220 A Tmb = 25 °C; Figure 1 Ptot total power dissipation - 85 W Tstg storage temperature −55 +175 °C Tj operating junction temperature −55 +175 °C Source-drain diode IS source (diode forward) current (DC) Tmb = 25 °C - 55 A ISM peak source (diode forward) current Tmb = 25 °C; pulsed; tp ≤ 10 µs - 220 A Avalanche ruggedness EAS non-repetitive avalanche energy unclamped inductive load; ID = 55 A; tp = 0.1 ms; VDD = 15 V; RGS = 50 Ω; VGS = 5V; starting Tj = 25 °C - 60 mJ IAS non-repetitive avalanche current unclamped inductive load; VDD = 15 V; RGS = 50 Ω; VGS = 5 V; starting Tj = 25 °C - 55 A © Koninklijke Philips Electronics N.V. 2001. All rights reserved. 9397 750 08642 Product data Rev. 02 — 2 August 2001 2 of 14 PHP55N03LTA series Philips Semiconductors N-channel enhancement mode field-effect transistor 03aa16 120 03aa24 120 I der Pder (%) (%) 80 80 40 40 0 0 0 50 200 150 Tmb (oC) 100 0 P tot P der = ---------------------- × 100% P ° 50 100 150 200 o Tmb ( C) ID I der = ------------------- × 100% I ° tot ( 25 C ) D ( 25 C ) Fig 1. Normalized total power dissipation as a function of mounting base temperature. Fig 2. Normalized continuous drain current as a function of mounting base temperature. 03ae64 103 ID (A) RDSon = VDS / ID tp = 10 µs 102 100 µs 10 δ= P tp T 1 ms D.C. 10 ms 100 ms t tp T 1 1 102 10 VDS (V) Tmb = 25 °C; IDM is single pulse. Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. © Koninklijke Philips Electronics N.V. 2001. All rights reserved. 9397 750 08642 Product data Rev. 02 — 2 August 2001 3 of 14 PHP55N03LTA series Philips Semiconductors N-channel enhancement mode field-effect transistor 7. Thermal characteristics Table 4: Thermal characteristics Symbol Parameter Conditions Value Unit Rth(j-mb) thermal resistance from junction to mounting base Figure 4 1.75 K/W Rth(j-a) thermal resistance from junction to ambient vertical in still air; SOT78 package 60 K/W mounted on a printed circuit board; minimum footprint; SOT404 and SOT428 packages 50 K/W 7.1 Transient thermal impedance 03ae63 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 0.1 10-1 0.05 δ= P 0.02 t tp single pulse tp T T 10-2 10-5 10-4 10-3 10-2 10-1 1 tp (s) Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration. © Koninklijke Philips Electronics N.V. 2001. All rights reserved. 9397 750 08642 Product data Rev. 02 — 2 August 2001 4 of 14 PHP55N03LTA series Philips Semiconductors N-channel enhancement mode field-effect transistor 8. Characteristics Table 5: Characteristics Tj = 25 °C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source breakdown voltage VGS(th) gate-source threshold voltage ID = 0.25 mA; VGS = 0 V Tj = 25 °C 25 - - V Tj = −55 °C 22 - - V 1 1.5 2 V ID = 1 mA; VDS = VGS; Figure 9 Tj = 25 °C IDSS drain-source leakage current Tj = 175 °C 0.5 - - V Tj = −55 °C - - 2.3 V - 0.05 10 µA VDS = 25 V; VGS = 0 V Tj = 25 °C Tj = 175 °C - - 500 µA - 10 100 nA Tj = 25 °C - 15 18 mΩ Tj = 175 °C - 25.5 30.6 mΩ - 11 14 mΩ IGSS gate-source leakage current VGS = ±5 V; VDS = 0 V RDSon drain-source on-state resistance VGS = 5 V; ID = 25 A; Figure 7 and 8 VGS = 10 V; ID = 25 A Tj = 25 °C Dynamic characteristics gfs forward transconductance VDS = 25 V; ID = 25 A - 32 - S Qg(tot) total gate charge - 20 - nC Qgs gate-source charge ID = 55 A; VDD = 15 V; VGS = 5 V; Figure 13 - 8 - nC Qgd gate-drain (Miller) charge - 7 - nC Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 11 VDD = 15 V; ID = 55 A; VGS = 10 V; RG = 5 Ω; resistive load - 950 - pF - 340 - pF - 230 - pF - 8 15 ns tr turn-on rise time - 45 80 ns td(off) turn-off delay time - 45 80 ns tf turn-off fall time - 40 60 ns Source-drain diode VSD source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12 - 0.95 1.2 V IS = 55 A; VGS = 0 V - 1.2 - V © Koninklijke Philips Electronics N.V. 2001. All rights reserved. 9397 750 08642 Product data Rev. 02 — 2 August 2001 5 of 14 PHP55N03LTA series Philips Semiconductors N-channel enhancement mode field-effect transistor 03ae67 03ae65 60 60 10 V Tj = 25 ºC ID (A) 5 V 4.5 V VDS > ID x RDSon ID (A) 4V 45 45 Tj = 25 ºC 3.5 V 30 15 30 15 3V VGS = 2.5 V 0 0 0.4 0.8 1.2 0 0 1.6 2 VDS (V) Tj = 25 °C 1 2 3 4 5 VGS (V) Tj = 25 °C and 175 °C; VDS > ID x RDSon Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values. 03ae66 Tj = 25 ºC 03ad57 2 0.03 RDSon 175 ºC VGS = 4 V a 1.6 (Ω) 4.5 V 0.02 1.2 5V 0.8 10 V 0.01 0.4 0 0 0 15 30 45 ID (A) 60 -60 Tj = 25 °C 60 120 Tj (ºC) 180 R DSon a = --------------------------R DSon ( 25 °C ) Fig 7. Drain-source on-state resistance as a function of drain current; typical values. Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature. © Koninklijke Philips Electronics N.V. 2001. All rights reserved. 9397 750 08642 Product data 0 Rev. 02 — 2 August 2001 6 of 14 PHP55N03LTA series Philips Semiconductors N-channel enhancement mode field-effect transistor 03aa33 2.5 (V) 03aa36 10-1 ID (A) 10-2 VGS(th) max 2 typ 10-3 1.5 min min 1 typ max 10-4 10-5 0.5 10-6 0 -60 0 60 120 o 180 0 0.5 1 Tj ( C) 1.5 2 2.5 3 VGS (V) Tj = 25 °C; VDS = 5 V ID = 1 mA; VDS = VGS Fig 9. Gate-source threshold voltage as a function of junction temperature. Fig 10. Sub-threshold drain current as a function of gate-source voltage. 03ae70 104 Ciss Coss Crss (pF) 103 Ciss Coss Crss 102 10-1 1 10 VDS (V) 102 VGS = 0 V; f = 1 MHz Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. © Koninklijke Philips Electronics N.V. 2001. All rights reserved. 9397 750 08642 Product data Rev. 02 — 2 August 2001 7 of 14 PHP55N03LTA series Philips Semiconductors N-channel enhancement mode field-effect transistor 03ae69 03ae71 10 60 VGS VGS = 0 V IS (A) ID = 55 A (V) Tj = 25 ºC 8 45 VDD = 15 V 6 30 4 15 175 ºC 2 Tj = 25 ºC 0 0 0 0.4 0.8 0 1.2 10 VSD (V) Tj = 25 °C and 175 °C; VGS = 0 V 30 QG (nC) 40 ID = 55 A; VDD = 15 V Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. Fig 13. Gate-source voltage as a function of gate charge; typical values. © Koninklijke Philips Electronics N.V. 2001. All rights reserved. 9397 750 08642 Product data 20 Rev. 02 — 2 August 2001 8 of 14 PHP55N03LTA series Philips Semiconductors N-channel enhancement mode field-effect transistor 9. Package outline Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB E SOT78 A A1 p q mounting base D1 D L2 L1(1) Q b1 L 1 2 3 b c e e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1 c D D1 E e L L1(1) L2 max. p q Q mm 4.5 4.1 1.39 1.27 0.9 0.7 1.3 1.0 0.7 0.4 15.8 15.2 6.4 5.9 10.3 9.7 2.54 15.0 13.5 3.30 2.79 3.0 3.8 3.6 3.0 2.7 2.6 2.2 Note 1. Terminals in this zone are not tinned. OUTLINE VERSION REFERENCES IEC SOT78 JEDEC EIAJ 3-lead TO-220AB SC-46 EUROPEAN PROJECTION ISSUE DATE 00-09-07 01-02-16 Fig 14. SOT78 (TO-220AB). © Koninklijke Philips Electronics N.V. 2001. All rights reserved. 9397 750 08642 Product data Rev. 02 — 2 August 2001 9 of 14 PHP55N03LTA series Philips Semiconductors N-channel enhancement mode field-effect transistor Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404 A A1 E mounting base D1 D HD 2 Lp 1 3 c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c D max. D1 E e Lp HD Q mm 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 11 1.60 1.20 10.30 9.70 2.54 2.90 2.10 15.80 14.80 2.60 2.20 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 99-06-25 01-02-12 SOT404 Fig 15. SOT404 (D2-PAK) © Koninklijke Philips Electronics N.V. 2001. All rights reserved. 9397 750 08642 Product data Rev. 02 — 2 August 2001 10 of 14 PHP55N03LTA series Philips Semiconductors N-channel enhancement mode field-effect transistor Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads (one lead cropped) SOT428 seating plane y A E A2 A A1 b2 D1 mounting base E1 D HE L2 2 L1 L 1 3 b1 w M A b c e e1 0 10 20 mm scale DIMENSIONS (mm are the original dimensions) A UNIT max. 2.38 2.22 mm A1(1) A2 b b1 max. b2 c 0.65 0.45 0.89 0.71 0.89 0.71 1.1 0.9 5.36 5.26 0.4 0.2 D1 E D max. max. max. E1 min. 6.22 5.98 4.0 6.73 6.47 4.81 4.45 e e1 2.285 4.57 HE max. L L1 min. L2 w y max. 10.4 9.6 2.95 2.55 0.5 0.7 0.5 0.2 0.2 Note 1. Measured from heatsink back to lead. OUTLINE VERSION SOT428 REFERENCES IEC JEDEC EIAJ TO-252 SC-63 EUROPEAN PROJECTION ISSUE DATE 98-04-07 99-09-13 Fig 16. SOT428 (D-PAK) © Koninklijke Philips Electronics N.V. 2001. All rights reserved. 9397 750 08642 Product data Rev. 02 — 2 August 2001 11 of 14 PHP55N03LTA series Philips Semiconductors N-channel enhancement mode field-effect transistor 10. Revision history Table 6: Revision history Rev Date CPCN Description 02 20010802 - Product data; Addition of SOT428 package 01 20010330 - Product data; initial version © Koninklijke Philips Electronics N.V. 2001. All rights reserved. 9397 750 08642 Product data Rev. 02 — 2 August 2001 12 of 14 PHP55N03LTA series Philips Semiconductors N-channel enhancement mode field-effect transistor 11. Data sheet status Data sheet status[1] Product status[2] Definition Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] [2] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 12. Definitions 13. Disclaimers Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: [email protected]. Product data Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. 9397 750 08642 Rev. 02 — 2 August 2001 13 of 14 Philips Semiconductors PHP55N03LTA series N-channel enhancement mode field-effect transistor Contents 1 2 3 4 5 6 7 7.1 8 9 10 11 12 13 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Transient thermal impedance . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 © Koninklijke Philips Electronics N.V. 2001. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 2 August 2001 Document order number: 9397 750 08642