INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT563 Octal D-type transparent latch; 3-state; inverting Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state; inverting FEATURES • 3-state inverting outputs for bus oriented applications TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. • ICC category: MSI The 74HC/HCT563 are octal D-type transparent latches featuring separate D-type inputs for each latch and inverting 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches. GENERAL DESCRIPTION The “563” is functionally identical to the “573”, but has inverted outputs. The 74HC/HCT563 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky The “563” consists of eight D-type transparent latches with 3-state inverting outputs. The LE and OE are • Inputs and outputs on opposite sides of package allowing easy interface with microprocessor • Common 3-state output enable input • Output capability: bus driver 74HC/HCT563 common to all latches. When LE is HIGH, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER tPHL/ tPLH propagation delay Dn, LE to Qn CI input capacitance CPD power dissipation capacitance per latch CONDITIONS CL = 15 pF; VCC = 5 V notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC for HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 2 UNIT HC HCT 14 16 ns 3.5 3.5 pF 19 19 pF Philips Semiconductors Product specification Octal D-type transparent latch; 3-state; inverting 74HC/HCT563 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 2, 3, 4, 5, 6, 7, 8, 9 D0 to D7 data inputs 11 LE latch enable input (active HIGH) 1 OE 3-state output enable input (active LOW) 10 GND ground (0 V) 19, 18, 17, 16, 15, 14, 13, 12 Q0 to Q7 3-state latch outputs 20 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification Octal D-type transparent latch; 3-state; inverting 74HC/HCT563 FUNCTION TABLE INPUTS OE LE OUTPUTS Dn INTERNAL LATCHES Q0 to Q7 OPERATING MODES enable and read register L L H H L H L H H L latch and read register L L L L l h L H H L latch register and disable outputs H H L L l h L H Z Z Notes 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition Z = high impedance OFF-state Fig.4 Functional diagram. Fig.5 Logic diagram. December 1990 4 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state; inverting 74HC/HCT563 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. −40 to +85 min. max. −40 to +125 min. UNIT V CC WAVEFORMS (V) typ. max. max. tPHL/ tPLH propagation delay Dn to Qn 47 17 14 145 29 25 180 36 31 220 44 38 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay LE to Qn 47 17 14 145 29 25 180 36 31 220 44 38 ns 2.0 4.5 6.0 Fig.7 tPZH/ tPZL 3-state output enable time OE to Qn 47 17 14 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.8 tPHZ/ tPLZ 3-state output disable time OE to Qn 50 18 14 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.8 tTHL/ tTLH output transition time 14 5 4 60 12 10 75 15 13 90 18 15 ns 2.0 4.5 6.0 Fig.6 tW enable pulse width HIGH 80 16 14 14 5 4 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.7 tsu set-up time Dn to LE 50 10 9 11 4 3 65 13 11 75 15 13 ns 2.0 4.5 6.0 Fig.9 th hold time Dn to LE 4 4 4 −6 −2 −2 4 4 4 4 4 4 ns 2.0 4.5 6.0 Fig.9 December 1990 5 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state; inverting 74HC/HCT563 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT Dn LE OE 0.35 0.65 1.25 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. −40 to +85 typ. max. min. max. −40 to +125 min. UNIT V CC WAVEFORMS (V) max. tPHL/ tPLH propagation delay Dn to Qn 18 30 38 45 ns 4.5 Fig.6 tPHL/ tPLH propagation delay LE to Qn 19 35 44 53 ns 4.5 Fig.7 tPZH/ tPZL 3-state output enable time OE to Qn 20 35 44 53 ns 4.5 Fig.8 tPHZ/ tPLZ 3-state output disable time OE to Qn 22 35 44 53 ns 4.5 Fig.8 tTHL/ tTLH output transition time 5 12 15 18 ns 4.5 Fig.6 tW enable pulse width HIGH 16 5 20 24 ns 4.5 Fig.7 tsu set-up time Dn to LE 10 3 13 15 ns 4.5 Fig.9 th hold time Dn to LE 5 −1 5 5 ns 4.5 Fig.9 December 1990 6 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state; inverting 74HC/HCT563 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Fig.7 Waveforms showing the data input (Dn) to output (Qn) propagation delays and the output transition times. Waveforms showing the latch enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays and the output transition times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the data set-up and hold times for Dn input to LE input PACKAGE OUTLINES (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. Waveforms showing the 3-state enable and disable times. December 1990 7