INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT648 Octal bus transceiver/register; 3-state; inverting Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Octal bus transceiver/register; 3-state; inverting 74HC/HCT648 bus will be clocked into the registers as the appropriate clock (CPAB and CPBA) goes to a HIGH logic level. Output enable (OE) and direction (DIR) inputs are provided to control the transceiver function. In the transceiver mode, data present at the high-impedance port may be stored in either the “A” or “B” register, or in both. The select source inputs (SAB and SBA) can multiplex stored and real-time (transparent mode) data. The direction (DIR) input determines which bus will receive data when OE is active (LOW). In the isolation mode (OE = HIGH), “A” data may be stored in the “B” register and/or “B” data may be stored in the “A” register. FEATURES • Independent register for A and B buses • Multiplexed real-time and stored data • Output capability: bus driver • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT648 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. The 74HC/HCT648 consist of bus transceiver circuits with 3-state inverting outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the internal registers. Data on the “A” or “B” The “648” is functionally identical to the “646”, but has inverting data paths. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER tPHL/ tPLH propagation delay An, Bn to Bn, An fmax maximum clock frequency CI input capacitance CPD power dissipation capacitance per channel CONDITIONS CL = 15 pF; VCC = 5 V notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 2 UNIT HC HCT 11 11 ns 75 88 MHz 3.5 3.5 pF 30 31 pF Philips Semiconductors Product specification Octal bus transceiver/register; 3-state; inverting 74HC/HCT648 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 CPAB A to B clock input (LOW-to-HIGH, edge-triggered) 2 SAB select A to B source input 3 DIR direction control input 4, 5, 6, 7, 8, 9, 10, 11 A0 to A7 A data inputs/outputs 12 GND ground (0 V) 20, 19, 18, 17, 16, 15, 14, 13 B0 to B7 B data inputs/outputs 21 OE output enable input (active LOW) 22 SBA select B to A source input 23 CPBA B to A clock input (LOW-to-HIGH, edge-triggered) 24 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification Octal bus transceiver/register; 3-state; inverting 74HC/HCT648 Fig.4 Functional diagram. FUNCTION TABLE INPUTS (1) DATA I/O (2) FUNCTION OE DIR CPAB CPBA SAB SBA A0 TO A7 B0 TO B7 H H X X H or L ↑ H or L ↑ X X X X input input isolation store A and B data L L L L X X X H or L X X L H output input real-time B data to A bus stored B data to A bus L L H H X H or L X X L H X X input output real-time A data to B bus stored A data to B bus Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care ↑ = LOW-to-HIGH level transition 2. The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock inputs. December 1990 4 Philips Semiconductors Product specification Octal bus transceiver/register; 3-state; inverting Fig.5 Logic diagram. December 1990 5 74HC/HCT648 Philips Semiconductors Product specification Octal bus transceiver/register; 3-state; inverting 74HC/HCT648 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. typ. max. −40 to +85 −40 to +125 min. min. max. UNIT VCC (V) WAVEFORMS max. tPHL/ tPLH propagation delay An, Bn to Bn, An 39 14 11 135 27 23 170 34 29 205 41 35 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay CPAB, CPBA to Bn, An 74 27 22 230 46 39 290 58 49 345 69 59 ns 2.0 4.5 6.0 Fig.7 tPHL/ tPLH propagation delay SAB, SBA to Bn, An 55 20 16 190 38 32 240 48 41 285 57 48 ns 2.0 4.5 6.0 Fig.8 tPZH/ tPZL 3-state output enable time OE to An, Bn 52 19 15 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 Fig.9 tPHZ/ tPLZ 3-state output disable time OE to An, Bn 61 22 18 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 Fig.9 tPZH/ tPZL 3-state output enable time DIR to An, Bn 52 19 15 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 Fig.10 tPHZ/ tPLZ 3-state output disable time DIR to An, Bn 55 20 16 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 Fig.10 tTHL/ tTLH output transition time 14 5 4 60 12 10 75 15 13 90 18 15 ns 2.0 4.5 6.0 Fig.6 and Fig.8 tW clock pulse width HIGH or LOW CPAB or CPBA ns 2.0 4.5 6.0 Fig.7 80 16 14 25 9 7 100 20 17 120 24 20 tsu 60 set-up time 12 An, Bn to CPAB, CPBA 10 0 0 0 75 15 13 90 18 15 ns 2.0 4.5 6.0 Fig.7 th 35 hold time 7 An, Bn to CPAB, CPBA 6 6 2 2 45 9 8 55 11 9 ns 2.0 4.5 6.0 Fig.7 fmax maximum clock pulse frequency 22 68 81 4.8 24 28 4.0 20 24 MHz 2.0 4.5 6.0 Fig.7 December 1990 6.0 30 35 6 Philips Semiconductors Product specification Octal bus transceiver/register; 3-state; inverting 74HC/HCT648 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT SAB, SBA A0 to A7; and B0 to B7; INPUT CPAB; CPBA; OE DIR December 1990 UNIT LOAD COEFFICIENT 0.60 0.75 UNIT LOAD COEFFICIENT 1.50 1.50 1.25 7 Philips Semiconductors Product specification Octal bus transceiver/register; 3-state; inverting 74HC/HCT648 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. typ. max. −40 to +85 −40 to +125 min. max. min. UNIT VCC (V) WAVEFORMS max. tPHL/ tPLH propagation delay An, Bn to Bn, An 14 27 34 41 ns 4.5 Fig.6 tPHL/ tPLH propagation delay CPAB, CPBA to Bn, An 25 46 58 69 ns 4.5 Fig.7 tPHL/ tPLH propagation delay SAB, SBA to Bn, An 20 38 48 57 ns 4.5 Fig.8 tPZH/ tPZL 3-state output enable time OE to An, Bn 21 40 50 60 ns 4.5 Fig.9 tPHZ/ tPLZ 3-state output disable time OE to An, Bn 20 35 44 53 ns 4.5 Fig.9 tPZH/ tPZL 3-state output enable time DIR to An, Bn 20 40 50 60 ns 4.5 Fig.10 tPHZ/ tPLZ 3-state output disable time DIR to An, Bn 21 35 44 53 ns 4.5 Fig.10 tTHL/ tTLH output transition time 5 12 15 18 ns 4.5 Fig.6 and Fig.8 tW clock pulse width HIGH or LOW CPAB or CPBA 16 7 20 24 ns 4.5 Fig.7 tsu set-up time An, Bn to CPAB, CPBA 12 2 15 18 ns 4.5 Fig.7 th hold time An, Bn to CPAB, CPBA 5 0 5 5 ns 4.5 Fig.7 fmax maximum clock pulse frequency 30 80 24 20 ns MHz Fig.7 December 1990 8 Philips Semiconductors Product specification Octal bus transceiver/register; 3-state; inverting 74HC/HCT648 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the input An, Bn to output Bn, An propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 (1) Waveforms showing the An, Bn to CPAB, CPBA set-up and hold times, clock CPAB, CPBA pulse width, maximum clock pulse frequency and the CPAB, CPBA to output Bn, An propagation delays. HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the input SAB, SBA to output Bn, An propagation delays and output transition times. December 1990 9 Philips Semiconductors Product specification Octal bus transceiver/register; 3-state; inverting (1) 74HC/HCT648 HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the input OE to output An, Bn 3-state enable and disable times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the input DIR to output An, Bn 3-state enable and disable times. December 1990 10 Philips Semiconductors Product specification Octal bus transceiver/register; 3-state; inverting APPLICATION INFORMATION Fig.11 Data storage from A and/or B bus. Fig.12 Real-time transfer from bus A to bus B. Fig.13 Real-time transfer from bus B to bus A. December 1990 11 74HC/HCT648 Philips Semiconductors Product specification Octal bus transceiver/register; 3-state; inverting PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 12 74HC/HCT648