INTEGRATED CIRCUITS
DATA SHEET
SAA4970T
Economical video processing IC
(ECOBENDIC)
Preliminary specification
File under Integrated Circuits, IC02
1996 Oct 25
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
FEATURES
GENERAL DESCRIPTION
• Digital horizontal PLL
The ECOBENDIC is an economical video processing IC
(Economical Back End IC) for double scan conversion.
It consists of sync/memory control, video enhancing
features and D/A conversion. The IC is designed to
cooperate with an 83C654 type of microcontroller,
Texas Instruments TMS4C2970/2971 memories plus a
4 : 1 : 1 A/D converter TDA8755/8753A.
• Digital CTI (DCTI)
• Digital luminance peaking
• Digital phase compensation filter
• D/A conversion
• Simple multi picture processing
• Coloured frame generation
• Memory/sync processing.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
digital supply voltage
4.5
5.5
V
VCC
analog supply voltage
4.75
5.25
V
Tamb
operating ambient temperature
0
70
°C
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA4970T
1996 Oct 25
VSO56
DESCRIPTION
plastic very small outline package; 56 leads
2
VERSION
SOT190-1
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
BLOCK DIAGRAM
handbook, full pagewidth
SAA4970T
UVIN3
to UVIN0
47 to
50
4
8
D
3
REFORMATTER
UP-SAMPLING
DCTI
8
D
5
A
YIN7
to YIN0
HA, VA
37 to 41,
44 to 46
8
UO
A
PHASE COMPENSATION
FILTER
9
PEAKING
D
7
A
VO
YO
22, 23
XtalO 55
56
2
19
MICROCONTROLLER
INTERFACE
PLL
SYNC PROCESSING
MEMORY CONTROL
18
XtalI
HD
VD
8
29 to 36
24 27 28
14
CK1 CK2 microcontroller
parallel bus
AD7 to AD0
ALE
RDN
WRN
CLMP
53
51
address line
microcontroller
command
microcontroller parallel bits
Fig.1 Block diagram.
1996 Oct 25
3
3
15 to 17
IE, WE, RE
MGE092
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
PINNING
SYMBOL
PIN
TYPE
DESCRIPTION
TEST2
1
input
test control
Pmirref
2
input
decoupling P-mirror reference
UO
3
output
analog U output
VSSA
4
ground
analog ground (0 V)
VO
5
output
analog V output
VCC
6
supply
analog supply voltage (+5 V)
YO
7
output
analog Y output
Vref
8
supply
analog supply voltage reference D/A ladder HIGH
Iref
9
supply
reference current
VrefH
10
supply
D/A decoupling capacitor
R1
11
I/O
reset acquisition horizontal counter
R2
12
I/O
reset display horizontal counter
PIP
13
input
PIP related input 0
CLMP
14
output
clamping control
IE
15
output
field memory input enable
WE
16
output
field memory write enable
RE
17
output
field memory read enable
VD
18
I/O
display vertical pulse
HD
19
output
display horizontal pulse
RESET
20
output
watchdog output (microcontroller reset)
BONE
21
input
watchdog input (microcontroller bone)
HA
22
I/O
acquisition horizontal pulse
VA
23
I/O
acquisition vertical pulse
ALE
24
input
address latch enable
IT1
25
output
acquisition related interrupt
IT2
26
output
display related interrupt
WRN
27
input
write not pulse
RDN
28
input
read not pulse
AD7
29
I/O
programmable signal positioner (psp) data bus bit 7 (MSB)
AD6
30
I/O
psp data bus bit 6
AD5
31
I/O
psp data bus bit 5
AD4
32
I/O
psp data bus bit 4
AD3
33
I/O
psp data bus bit 3
AD2
34
I/O
psp data bus bit 2
AD1
35
I/O
psp data bus bit 1
AD0
36
I/O
psp data bus bit 0 (LSB)
YIN7
37
input
Y input bus bit 7 (MSB)
YIN6
38
input
Y input bus bit 6
YIN5
39
input
Y input bus bit 5
YIN4
40
input
Y input bus bit 4
1996 Oct 25
4
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SYMBOL
PIN
SAA4970T
TYPE
DESCRIPTION
YIN3
41
input
Y input bus bit 3
VDD
42
supply
digital supply voltage (+5 V)
VSS
43
ground
digital ground (0 V)
YIN2
44
input
Y input bus bit 2
YIN1
45
input
Y input bus bit 1
YIN0
46
input
Y input bus bit 0 (LSB)
UVIN3
47
input
UV input bus bit 3 (MSB)
UVIN2
48
input
UV input bus bit 2
UVIN1
49
input
UV input bus bit 1
UVIN0
50
input
UV input bus bit 0 (LSB)
CK2
51
I/O
display clock
VSS
52
ground
digital ground (0 V)
CK1
53
I/O
acquisition clock
TEST1
54
input
test control
XtalO
55
output
external crystal output (12 MHz)
XtalI
56
input
PLL crystal input (12 MHz)
1996 Oct 25
5
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
FUNCTIONAL DESCRIPTION
ECO data path
The data path performs the DCTI, peaking, phase
compensation, framing and blanking functions plus colour
reformatting and variable delay of Y to UV at the input and
output of the data path.
handbook, halfpage
TEST2
1
56 XtalI
Pmirref
2
55 XtalO
UO
3
54 TEST1
VSSA
4
53 CK1
VO
5
52 VSS
VCC
6
51 CK2
YO
7
50 UVIN0
Vref
8
49 UVIN1
Iref
9
48 UVIN2
VrefH 10
47 UVIN3
R1 11
46 YIN0
R2 12
45 YIN1
PIP 13
44 YIN2
CLMP 14
SAA4970T
DCTI
DCTI is implemented to get a dynamic interpolation of the
low bandwidth U and V signals. First a 2 : 1 linear
interpolation is done, to go from a 4 : 1 : 1 format to a
4 : 2 : 2 format. A second interpolation is done in which the
data path delay is varied on the basis of a function of the
second derivative of the U and V signal (or more precise:
d dU
{
+ dV } ). The effect at an edge is that during the
dt dt
dt
first half the data path delay is higher than nominal and in
the second half it is lower than nominal. This will make the
edge much steeper. As this second interpolation is done
with the resolution equal to that of the Y samples and also
with a zero DCTI gain a 2 : 1 interpolation is performed, a
4 : 4 : 4 format is obtained.
43 VSS
IE 15
42 VDD
WE 16
41 YIN3
RE 17
40 YIN4
VD 18
39 YIN5
HD 19
38 YIN6
RESET 20
37 YIN7
BONE 21
36 AD0
HA 22
35 AD1
VA 23
34 AD2
ALE 24
33 AD3
IT1 25
32 AD4
IT2 26
31 AD5
WRN 27
30 AD6
RDN 28
29 AD7
The DCTI function can be controlled by setting the range
to ±12, ±8, ±6 or ±4 pixels (see Fig.3) or by adjusting the
gain to 0, 1⁄4, 1⁄2 or 1.
An artefact of this processing exists when two edges are
close together in the video. During the second half of the
first edge a delay is chosen that will collect video data
where the second edge is already active. The same is valid
for the second edge. The result of this processing on a
video pulse, which is looking like a hill, is that of a hill with
one or two bumps in it. To prevent this from happening, the
positions where the first derivatives in U and V change
sign, are marked and used to limit the range of the relative
delay. This function is called ‘over the hill protection’. It can
be turned on and off. Figures 5 and 6 show the effect of
the DCTI function with and without ‘over the hill protection’
when applied to a hill-shaped video pulse.
MGE091
Fig.2 Pin configuration.
1996 Oct 25
6
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
MGE093
120
handbook, full pagewidth
digital
signal
amplitude
100
80
(1)
(2)
(3)
60
1
5
10
15
20
25
30
35
40
(1) input signal.
(2) range = 4.
(3) range = 12.
samples
45
Gain = 1⁄2.
Fig.3 DCTI with variation of k range.
MGE094
120
handbook, full pagewidth
digital
signal
amplitude
100
80
(1)
(2)
(3)
(4)
60
1
(1) input signal.
(2) gain = 0.25.
5
10
15
20
25
30
(3) gain = 0.5.
(4) gain = 1.
Fig.4 DCTI with variation of k gain.
1996 Oct 25
7
35
Range = 12.
40
samples
45
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
MGE095
120
handbook, full pagewidth
digital
signal
amplitude
(1)
100
80
(2)
60
20
30
40
50
60
70
80
samples
90
Gain = 1⁄2.
Range = ±12.
Hill protection = on.
(1) output.
(2) input.
Fig.5 DCTI with ‘over the hill protection’.
MGE096
120
handbook, full pagewidth
digital
signal
amplitude
(1)
100
80
(2)
60
20
30
40
50
60
70
80
Gain = 1⁄2.
Range = ±12.
Hill protection = off.
(1) output.
(2) input.
Fig.6 DCTI without ‘over the hill protection’.
1996 Oct 25
8
samples
90
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
The band-passed and high-passed signals are weighted
with factors 0, 1⁄8, 1⁄4 and 1⁄2. The impulse response
becomes [−α, −β, 1 + 2α + 2β, −β, −α], where α is the
band-pass weighting factor and β the high-pass weighting
factor.
PEAKING
Peaking is implemented to obtain a higher gain in the
middle and upper ranges of the luminance bandwidth.
The filtering is an addition of:
• the original signal
Coring is added to obtain no gain for low amplitudes in the
(high-pass + band-pass) signal, which is then considered
to be noise. Coring levels can be programmed as 0 (off),
+1/−2, +3/−4 and +7/−8 LSB at 10-bit word.
• the original signal band-passed with centre
frequency = 1⁄4fs
• the original signal high-passed with maximum gain at
frequency = 1⁄2fs.
A limiter brings back the 11-bit range to a 9-bit range with
a clipping function on the lower and upper side.
MGE097
12
MGE098
12
handbook, halfpage
handbook, halfpage
(1)
10
10
(1)
IH_PeakingI
(dB)
8
IH_PeakingI
(dB)
8
(2)
(3)
(2)
6
(4)
6
(3)
4
4
(4)
2
2
0
0
0
1/4fs
0
1/2fs
(1) β = 1⁄2.
(2) β = 1⁄4.
(1)
(2)
(3)
(4)
(3) β = 1⁄8.
(4) β = 0.
Fig.7
Peaking transfer function with variation of β
(α = 1⁄8).
1996 Oct 25
1/2fs
β = 1⁄2.
β = 1⁄4.
β = 1⁄8.
β = 0.
Fig.8
9
1/4fs
Peaking transfer function with variation of β
(α = 1⁄4).
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
MGE099
16
MGE100
12
handbook, halfpage
handbook, halfpage
14
IH_PeakingI
(dB)
12
10
IH_PeakingI
(dB)
8
(1)
(1)
10
(2)
8
6
(3)
(2)
6
(4)
4
4
(3)
2
2
0
0
0
(1)
(2)
(3)
(4)
1/4fs
0
1/2fs
β = 1⁄2.
β = 1⁄4.
β = 1⁄8.
β = 0.
1/2fs
(1) β = 1⁄2.
(2) β = 1⁄4.
(3) β = 1⁄8.
Peaking transfer function with variation of β
(α = 1⁄2).
Fig.9
1/4fs
Fig.10 Peaking transfer function with variation of β
(α = 0).
To compensate for a non-linear phase characteristic
before the A/D converter, this filter will compensate such
behaviour with a pulse response of [−λ, 1 + λ]. λ can be
programmed for the values 0, 1⁄8, 1⁄4 and 1⁄2.
PHASE COMPENSATION
MGE101
0
handbook, halfpage
An 8-bit word width is re-obtained by means of clipping at
0 and 255.
(1)
(2)
(3)
(4)
Φnlp
(f/fs)
FRAMING AND BLANKING
Blanking is done with switching Y to value 16 and UV to
value 0 (in twos complement) on command of the BL
signal.
−1/2π
Framing is done by switching Y and the higher nibble of U
and V to certain programmable values (frame Y and
frame UV) on command of the signal KAD.
−π
(1)
(2)
(3)
(4)
0
0.125
0.25
0.375
f/fs
If the pixel repetition function is chosen the last values from
the video remain repeated instead of the fixed values.
0.5
λ = 0.
λ = 1⁄8.
λ = 1⁄4.
λ = 1⁄2.
The range of the output signal YO can be selected between
8 and 9 bits. In case of 8 bits for the nominal signal there
is room left for under and overshoot (adding up to a total of
9 bits); in case of selecting all 9 bits of the luminance D/A
converter for the nominal signal any under or overshoot
will be clipped.
Fig.11 Phase spectrum of NLP filter transfer
function.
1996 Oct 25
10
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
VARIABLE INPUT AND OUTPUT DELAYS
HORIZONTAL AND ACQUISITION BLOCK
To obtain flexibility, a programmable delay difference
between Y and UV can be made at both input and output.
CNT_A is an 8-bit counter, which counts up to
256 positions per acquisition video line. The cycle length
of the counter is determined by either:
At the input an almost symmetrical range of Y to UV delay
can be made: −3 to +4 clock pulses.
an external reset (rising edge of R1) on every line or
an internal reset, generated at a certain value of the
counter itself.
At the output a range of Y to UV delay from −5 to +2 clock
pulses can be made. When using e.g. scavenge circuitry,
which has an additional external delay, the lower delays in
Y are able to compensate this.
For operation with the internal reset only, a value N in the
‘reset CNT_A’ register will result in an N + 1 length cycle.
The R1 signal, generated by the ECO-PLL, should then be
kept at a constant level. This however has not been
foreseen in the ECO-PLL, so this mode of operation is not
implied.
COLOUR REFORMATTING
The reformatter changes the DMSD 4 : 1 : 1 format UV
signals into a sequential 8-bit U and V format according to
the following scheme:
For operation with the external reset only, the ‘reset
CNT_A’ register must be loaded with a value above the
maximum line length. A value of FFH is suggested.
input:
U7, U5, U3, U1, U7, U5...etc.
The VI1 input signal is monitored on its rising edge, with
regard to the CNT_A momentary value. By reading out
MUXA the positions of the edge becomes available for the
microcontroller. If VI1 is the video field pulse, the position
of the active edge within a video line becomes available.
This indicates the interlace situation of the acquisition
video signal. A window for discrimination of undesired VI1
edges is used. This window is made in the vertical
acquisition block.
U6, U4, U2, U0, U6, U4...etc.
V7, V5, V3, V1, V7, V5...etc.
V6, V4, V2, V0, V6, V4...etc.
output:
U7, V7, U7, V7...etc.
U6, V6, U6, V6...etc.
U5, V5, U5, V5...etc.
If a write to ‘SAMPLE AQUI and DISPL’ is done, MUXA will
be loaded with the momentary CNT_A contents.
U4, V4, U4, V4...etc.
U3, V3, U3, V3...etc.
The PIP input signal is monitored on its edges, with regard
to the CNT_A momentary values. If the PIP interrupt is
enabled, an occurring rising edge will generate acquisition
interrupt. By reading out MUXF and MUXG, the positions
of the rising and falling edges become available for the
microcontroller.
U2, V2, U2, V2...etc.
U1, V1, U1, V1...etc.
U0, V0, U0, V0...etc.
If the master clock frequency in the IC is 27 MHz then the
data rate of the reformatter output is 13.5 MHz.
The internal acquisition gate pulses GA1, GA2 and GA3
(routed to CLMP, WE and IE) are set and reset at
selectable CNT_A values. The sets of GA2 and GA3 have
to be enabled by the vertical acquisition block. If the set
and reset registers have equal contents, the signal will
remain reset (reset overruling set).
The signals UVbin and UV8bit, supplied by the
microcontroller interface, select binary/twos complement
mode and 8-bit/7-bit operation.
Economy Controller - Programmable Signal
Positioner (ECO-PSP) control/microcontroller
interface and sync processing
The internal acquisition horizontal pulse HI is HIGH when
the CNT_A contents are equal to a programmable value in
the HI position register.
The control/microcontroller interface and sync processing
part is designed as a separate unit called the ECO-PSP.
1996 Oct 25
11
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
For operation with the external reset only, the ‘reset
CNT_F’ register must be loaded with a value above the
maximum line length. A value of FFH is suggested.
VERTICAL ACQUISITION BLOCK
CNT_B is a 9-bit counter, which counts to up to 512 lines
per acquisition video field. The cycle length of the counter
is determined by either:
Whenever CNT_F is reset, the internal display horizontal
pulse HU is generated.
an external reset (rising edge of VI1) on every field or
The signals BL, H2, KAD and internally GD (which
becomes RE in the gates block) have programmable sets
and resets, and can therefore have rising and falling edges
at any desired CNT_F value. If the set and reset registers
have equal contents, the signal will remain reset (reset
overruling set). To keep the signals set, the reset register
should remain above the maximum CNT_A value, while
the set value is within the CNT_A cycle range. The GD has
two pairs of set/reset registers, and can generate 4 edges
per line instead of 2. The KAD has three pairs of set/reset
registers, and can generate 6 edges per line instead of 2.
The GD pulse has a programmable fine shift of 0, 1, 2 or
3 CK2 pulses on both of its edges.
an internal reset, generated at a certain value of the
counter itself, at the moment that the window is closed,
without a VI1 rising edge having occurred during the
window.
The counter value of CNT_B is monitored at the moment
the VI1 rising edge is detected and can be read out from
MUXB by the microcontroller. This value then indicates the
number of lines in a video field. If the window is closed,
without a VI1 rising edge having occurred during the
window, MUXB will also be filled with the momentary
contents of CNT_B.
If a write to ‘SAMPLE AQUI and DISPL’ is done, MUXB will
be loaded with the momentary CNT_B contents.
All the horizontal display output signals have enables on
the sets and resets. These enables will be effectively
changed only at the occurrence of the internal horizontal
HU pulse. Therefore it is possible to set up various signal
edges slowly by the microcontroller and effectuate them all
at once in a certain video line.
An interrupt can be generated on a pre-defined acquisition
line (Counter B-interrupt-Acquisition-b) by writing its line
number to the ‘set CB_intAb’ register. If the interrupt is not
desired, the register should be filled with a value above the
‘reset window’ register contents. The value 1FFH is
suggested. Otherwise the interrupt may be disabled by
bit 1 of the PLL control register (address 3D).
The VI2 input/output signal is monitored on its rising edge,
with regard to the CNT_F momentary value. By reading
out MUXD, the position of the edge becomes available for
the microcontroller. If VI2 is the video field pulse, the
position of the active edge within a video line becomes
available. This indicates the interlace situation of the
display video signal.
CNT_C is a 9-bit counter that resets to 0 at a pre-defined
state of CNT_B. The internal ‘Gate Enable’ signal is then
also set. ‘Gate Enable’ is reset at a pre-defined value of
CNT_C. At that moment also an interrupt can be
generated. If the interrupt is not desired, it can be disabled
by bit 3 in the PLL control register.
If a write to ‘SAMPLE AQUI and DISPL’ is done, MUXD will
be loaded with the momentary CNT_F contents.
HORIZONTAL DISPLAY BLOCK
If VI2 is used as an output, the ‘VHU register/comparator’
generates a line frequent pulse that is used in the vertical
display block for the timing of the VI2 edges within the
lines.
CNT_F is an 8-bit counter, which counts up to
256 positions per display video line. The cycle length of the
counter is determined by either:
an external reset or a reset from the ECO-PLL (rising
edge of R2) on every line or
VERTICAL DISPLAY BLOCK
an internal reset, generated at a certain value of the
counter itself.
CNT_D is a 9-bit counter, which counts to maximum
512 lines per display video field. The cycle length of the
counter is determined by a reset action from the
microcontroller, i.e. writing to address 14H.
For operation with the internal reset only, a value N in the
‘reset CNT_F’ register will result in an N + 1 length cycle.
The R2 input should now be kept HIGH or LOW. This
means in the ECOBENDIC the R2 output from the
ECO-PLL 3-state and the R2 signal will externally be kept
HIGH or LOW.
1996 Oct 25
The counter value of CNT_D is monitored at the moment
the VI2 rising edge is detected and can be read out from
MUXE by the microcontroller. This value then indicates the
number of lines in a video field.
12
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
The interrupts are grouped into two output signals: IT1 is a
combination of all acquisition related interrupts, while IT2
is the only display related interrupt.
If a write to ‘SAMPLE AQUI and DISPL’ is done, MUXE will
be loaded with the momentary CNT_D contents.
An interrupt can be generated on a pre-defined display line
(Counter D-interrupt-Display-b) by writing its line number
to the ‘set CD_intDb’ register. If the interrupt is not desired,
the register should be filled with a value above the
maximum number of display lines. The value 1FFH is
suggested.
ACQUISITION AND DISPLAY CLOCK BLOCKS
The CK1 and CK2 input clock signals are divided into div1
or div4 signals (internal clock signals), where div1 in only
meant for testing purposes. The divided clocks are
multiplexed to MC1 and MC2.
If VI2 is used as an output, the falling edge can be
activated by addressing the ‘start flyback’ register and the
rising edge by addressing the ‘start scan’ register. In the
‘horizontal display block’ a pulse is generated with the
‘VHU register/comparator’. This pulse is used for the
timing of the edges within the lines. This gives the ability to
determine the interlace of the display and is continuously
variable. It is useful to use the display interrupt to trigger
the microcontroller for issuing the flyback and scan edges
in a certain display line.
The multiplexer select states for MC1 and MC2 are
programmed in the internal control register.
MICROCONTROLLER INTERFACE BLOCK
The microcontroller interface consists of an addressing, a
read and a write part.
The addressing is performed with an address latch, that
latches the address/data bus while ‘address latch enable’
is active (HIGH).
GATES BLOCK
Writing data to any destination in the ECO-PSP consists
of two activities:
The internal signals ‘Gate Acquisition 1’ (GA1), ‘Gate
Acquisition 2’ (GA2), ‘Gate Acquisition 3’ (GA3) and ‘Gate
Display’ (GD) are fed through shift stages, which are
programmed to shift the rising and falling edges 0, 1, 2 or
3 input clock periods. For GA1, GA2 and GA3 the shift is
in CK1 periods; for GD the shift is in CK2 periods.
1. The address in the address latch is converted to an
enable signal for the destination in question. This
enable is activated while WRN is active (LOW).
2. The 8-bit data on the address/data bus is merged with
a 9th bit, which is the highest bit (bit 7) of the address
latch. This resulting 9-bit data is sent to registers in the
various blocks. Most registers only use 8 bits of data,
in that case the 9th bit is a ‘don’t care’.
The construction of the shifts makes it possible to generate
the gate outputs with higher resolution than the other
signals. If MC1 = 1⁄4CK1 and MC2 = 1⁄4CK2, any position
of the edges is possible with a resolution of CK1 and CK2
clock period.
Writing to 7 addresses simultaneously is possible by
supplying an address in the range of 00H to 07H. All the
destinations in the column of that address in the write table
are then supplied with the same data.
ACQUISITION AND DISPLAY INTERRUPTS BLOCKS
As described in the acquisition and display vertical blocks,
on programmed positions of CNT_B, CNT_C and CNT_D
interrupts are generated. Also, as described in the
horizontal acquisition block, an interrupt may be generated
on a rising edge of the PIP signal.
The destinations in the ECO-PSP may be: 9-bit registers,
8-bit registers, counter resets, interrupt resets, gate output
selects and the acquisition and display function.
Reading data from one of the 7 readable registers also
consists of two activities:
The PIP related interrupt and the ‘gate input, CNT_C’
related interrupt can be enabled or disabled by bits in the
PLL control register.
1. The address in the address latch is converted to a
multiplexer setting for the source in question.
The status of each interrupt is separately held in a flip-flop.
The interrupt status flip-flops can all be monitored by
reading MUXC.
2. The 8-bit data from the source 3-state enabled to the
address/data bus. If a 9-bit register is read out, the
highest bit (bit 8) is coded in the MUXC source.
To reset any of the interrupts, the flip-flops can be reset
individually by addressing their reset interrupt address.
The seven sources in the ECO-PSP are described in the
read table.
1996 Oct 25
13
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
The win_PLL signal from the PSP part of the ECOBENDIC
windows the part of the picture where a VCR phase
disturbance might occur. This is normally part of the
vertical blanking period, but with the double scan
conversion and a single acquisition/display clock system,
it would become visible in the lower part of the picture as
bottom flutter. Therefore, with win_PLL active, the
frequencies generated by the PLL remain fixed at the last
frequencies during lock.
ECO-PLL
In the PLL block, 3 functions are performed with the
following sub-blocks:
• Crystal oscillator
• PLL core
• Clock and R1 divider for multi picture.
CRYSTAL OSCILLATOR
When the control bit ‘free run’ is active, a fixed frequency
will be produced, determined by the setting of PLL_div.
PLL_div = 0 gives 32 MHz, PLL_div = 1 gives 27 MHz,
PLL_div = 2 gives 24 MHz and PLL_div = 3 gives
20.25 MHz on the display clock CK2.
The crystal oscillator should drive an external 12 MHz
crystal used in the watchdog and externally by e.g. the
microcontroller.
PLL CORE
CLOCK AND R1 DIVIDER FOR MULTI PICTURE
In the PLL core, line locked clocks are made for both the
acquisition and display sides of the double scan
conversion circuits. The PLL can lock its outputs to an
externally applied Hs 16 kHz line pulse. The outputs are:
To make simple multi picture processing, it is possible to
reduce the clock rate at the acquisition side by a
factor 2 or 3.
• CK2, the display clock
Suppose, a factor of 3 is chosen. Then, 1⁄3 of the memory
data that is normally written by 1 line of video will now be
written by 3 lines of the input video. If writing to the
memory is only enabled for a chosen 1⁄3 of this period, a
desired part of the video line to be displayed is updated
with a compressed line of input video. After a cycle of
3 input lines, the write pointer of the memory is located on
a position, that will be displayed exactly 1 line below. For
this essential cycle of 3 input lines, also the 16 kHz RL1
pulse must be frequency divided by 3.
• CL1, the (basic) acquisition clock
• R2, the display 32 kHz line frequent pulse
• RL1, the (basic) 16 kHz line frequent pulse.
The CK2 frequency relates to the Hs frequency with a
factor determined by PLL_div:
PLL_div = 0 → CK2 = 2 × 1024 × Hs (nominal 32 MHz)
PLL_div = 1 → CK2 = 2 × 864 × Hs (nominal 27 MHz)
PLL_div = 2 → CK2 = 2 × 768 × Hs (nominal 24 MHz)
PLL_div = 3 → CK2 = 2 × 648 × Hs
(nominal 20.25 MHz).
USE OF INTERNAL AND EXTERNAL PLL CIRCUITS
The ECOBENDIC is designed primarily for use with its
internal (ECO)PLL circuit, providing a one clock system for
acquisition and display. It is however possible to use
external PLL circuits for either the acquisition or the display
side or both. E.g. for use in a 16 : 9 TV-set, at least one
external PLL circuit is necessary to perform horizontal
compression of any 4 : 3 program material.
The Cp and Ci settings in the PLL2 control byte correspond
to coefficients in the proportional and integrating parts of
the PLL control loop.
The actual proportional coefficient is 2−(Cp + 1). With Cp
ranging from 0 to 7, 2−(Cp + 1) ranges from 1⁄2 to 1⁄256.
The actual integrating coefficient is 2−(Ci + 2). With Ci
ranging from 0 to 15, 2−(Ci + 2) ranges from 1⁄4 to 1⁄131072.
To assist any external PLL function, use can be made of
the clock to line pulse dividers in the ECO-PSP and 3-state
switching on the output of such pulse, switching by the HA
input. This may provide a VCO control voltage, if combined
with an RC filter.
The PLL core itself is driven by the 12 MHz signal from the
crystal oscillator.
The PLL can be set to lock upon the Hs signal, or to run
free at a fixed frequency or at the last frequency during
lock.
In normal operation the PLL locks to the Hs signal.
1996 Oct 25
14
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
The watchdog will keep quiet as long as this toggling
interval is not longer than the duration of the watchdogs
“bone-edge to reset” time. The reset pulse is designed to
be long enough (32 XtalUP cycles) for the microcontroller
to reset, but must not remain active (HIGH) indefinitely.
Otherwise the microcontroller would be hung up in its reset
operation.
ECO-WATCHDOG
The function of the watchdog is to reset the microcontroller
if it is not running the application properly. For this
purpose, the microcontroller program checks upon correct
operation and in case this is OK, it will periodically
generate a toggle of the BONE signal.
Control facilities
Table 1
Registers of the ECOBENDIC
REGISTER
BIT
NAME
FUNCTION
Registers 00H to 07H (column set)
00H
0 to 7
set all registers of columns 0XH and 8XH
01H
0 to 7
set all registers of columns 1XH and 9XH
02H
0 to 7
set all registers of columns 2XH and AXH
03H
0 to 7
set all registers of columns 3XH and BXH
04H
0 to 7
set all registers of columns 4XH and CXH
05H
0 to 7
set all registers of columns 5XH and DXH
06H
0 to 7
set all registers of columns 6XH and EXH
07H
0 to 7
set all registers of columns 7XH and FXH
Registers 08H and 09H (blanking)
08H
0 to 7
set blanking
sets rising edge of signal BL when register data = CNT_F
09H
0 to 7
reset blanking
sets falling edge of signal BL when register data = CNT_F
Registers 0AH and 0BH (interrupt)
0AH
0 to 8
set CB_intAb
CNT_B value when Acquisition B Interrupt (CB_intAb) is triggered
0BH
0 to 8
set CD_intDb
CNT_D value when Display Interrupt (CD_intDb) is triggered
Register 0CH (YUV control)
0CH
0
phase compensation
λ value for phase compensation filter, bit 0
1
λ value for phase compensation filter, bit 1
2
not used
3
Y OUT
Y clipping, 0 = off, 1 = on
4
inv_UV
inverts UV signals after UV processing;
0 = no inversion, 1 = inversion
5
UVbin
reformatter; 1 = binary, 0 = twos complement
6
UV8bit
reformatter; 1 = 8-bit quantization, 0 = 7-bit quantization
7
Sel_PixRep
1 = pixel repetition, 0 = constant colour for framing
Registers 0DH and 0EH (H2 generation)
0DH
no data update start scan
after addressing rising edge of H2 is set
0EH
no data update start flyback
after addressing falling edge of H2 is set
1996 Oct 25
15
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
REGISTER
BIT
SAA4970T
NAME
FUNCTION
Register 0FH (internal control register)
0FH
0
not used
1
VI1_Hs output enable
enables internal generation of VI1 and Hs signals (= 1)
2
MC1_select
selects clock rate of MC1; 1: MC1 = 1⁄4CK1; 0: MC1 = CK1
3
MC2_select
selects clock rate of MC2; 1: MC2 = 1⁄4CK2; 0: MC2 = CK2
4
VI2 output enable
enables internal generation of VI2 (= 1)
5
0
6
0
7
CNT_D reset enable
enables reset of CNT_D by VI2 (= 1)
Registers 10H and 11H (H2)
10H
0 to 7
set H2
CNT_F value when rising edge of signal H2 occurs
11H
0 to 7
reset H2
CNT_F value when falling edge of signal H2 occurs
Register 12H (reset CNT_C)
12H
0 to 8
reset CNT_C
resets CNT_C when register data = CNT_B
Register 13H (peaking)
13H
0
Alpha
α, bit 1; see Table 2
1
2
Beta
β, bit 0; see Table 3
β, bit 1; see Table 3
3
4
α, bit 0; see Table 2
Coring
coring value, bit 0; see Table 4
5
coring value, bit 1; see Table 4
6
not used
7
not used
Register 14H (reset CNT_D)
14H
no data reset CNT_D
resets CNT_D when address 14H is sent
Register 15H (DCTI)
15H
0
DCTI range
1
2
DCTI gain
3
4
K range, bit 0; see Table 5
K range, bit 1; see Table 5
K gain, bit 0; see Table 6
K gain, bit 1; see Table 6
hill_protect
over the hill protection; 1 = on, 0 = off
5
not used
6
not used
7
not used
Register 16H (frame Y)
16H
1996 Oct 25
0 to 7
frame Y
frame grey level = 128 + register data (128 to 383)
16
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
REGISTER
BIT
SAA4970T
NAME
FUNCTION
Register 17H (RE EN’s SR)
17H
0
enable set 1
enables setting of rising edge 1 of RE
1
enable set 2
enables setting of rising edge 2 of RE
2
enable reset 1
enables setting of falling edge 1 of RE
3
enable reset 2
enables setting of falling edge 2 of RE
4
not used
5
not used
6
not used
7
not used
Registers 18H and 19H (KADer)
18H
0 to 7
set 3 KAD
sets third rising edge of KAD signal when register data = CNT_F
19H
0 to 7
reset 3 KAD
sets third falling edge of KAD signal when register data = CNT_F
Register 1AH (update Len GE)
1AH
0 to 8
update Len GE
sets rising edge of GE signal when register data = CNT_C
Register 1BH (reset CNT_F)
1BH
0 to 7
reset CNT_F
resets CNT_F when register data = CNT_F
Register 1DH (frame UV)
1DH
0
frame U
frame U level (0 to 15), bit 0
1
frame U level (0 to 15), bit 1
2
frame U level (0 to 15), bit 2
3
4
frame U level (0 to 15), bit 3
frame V
frame V level (0 to 15), bit 0
5
frame V level (0 to 15), bit 1
6
frame V level (0 to 15), bit 2
7
frame V level (0 to 15), bit 3
Register 1EH (delay)
1EH
0
MC2_PROC module
1
2
OUT_DELAY module
delay of UV against Y signal, bit 0; see Table 8
3
delay of UV against Y signal, bit 1; see Table 8
4
delay of UV against Y signal, bit 2; see Table 8
5
1996 Oct 25
delay of MC2, bit 0
delay of MC2, bit 1
IN_DELAY module
delay of Y signal against UV signals, bit 0; see Table 9
6
delay of Y signal against UV signals, bit 1; see Table 9
7
delay of Y signal against UV signals, bit 2; see Table 9
17
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
REGISTER
BIT
SAA4970T
NAME
FUNCTION
Register 1FH (BL, H2 EN’s SR)
1FH
0
enable set BL
enables rising edge of BL
1
enable reset BL
enables falling edge of BL
2
enable set H2
enables rising edge of H2
3
enable reset H2
enables falling edge of H2
4
not used
5
not used
6
not used
7
not used
Registers 20H and 21H (PLL)
20H
0
PLL_CORE control
1 = free-run mode: not line-locked CK1/2 generation
0 = locked mode: CK1/CK2 generation is line-locked by Hs
1
if free-run mode (else don’t care):
1 = last frequency: generates last frequency in locked mode
0 = fixed frequency: CK1/CK2 rate is determined by PLL_div
2
PLL_div, bit 0; see Table 10
3
PLL_div, bit 1; see Table 10
4
5
0 (test bit)
DIV123 control
6
21H
MPIP processing; specifies dividing of CK1 and R1;
CK1PLL_CORE = 1⁄2CK2; CK1 = div × CK1PLL_CORE;
R1 = div × 16 kHz (RL1); bit 0; see Table 7
MPIP processing; specifies dividing of CK1 and R1;
CK1PLL_CORE = 1⁄2CK2; CK1 = div × CK1PLL_CORE;
R1 = div × 16 kHz (RL1); bit 1; see Table 7
7
VI1 synchronized
R1 is synchronized by VI1 (= 1); no synchronisation (= 0)
0
n
coefficient n of PI filter (Cp = 2−(n + 1)), bit 0
1
coefficient n of PI filter (Cp = 2−(n + 1)), bit 1
2
coefficient n of PI filter (Cp = 2−(n + 1)), bit 2
3
m
coefficient m of PI filter (Ci = 2−(m + 2)), bit 0
4
coefficient m of PI filter (Ci = 2−(m + 2)), bit 1
5
coefficient m of PI filter (Ci = 2−(m + 2)), bit 2
6
coefficient m of PI filter (Ci = 2−(m + 2)), bit 3
7
1
Register 22H (update HI pos)
22H
0 to 7
update HI pos
when register data = CNT_A then signal HI is set and CNT_B and
CNT_C are incremented
Register 23H (reset CNT_A)
23H
0 to 7
reset CNT_A
resets CNT_A when register data = CNT_A; generation of R1 output
signal, if en_R1_out = 1 and oe_CK1 = 0
Register 24H (reset GI_intAa)
24H
1996 Oct 25
0 to 7
reset GI_intAa
resets Blanking-Acquisition-Interrupt
18
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
REGISTER
BIT
SAA4970T
NAME
FUNCTION
Register 25H (update G_shifts1)
25H
0
fine shift CLMP
1
2
fine shift WE
3
4
fine shift of WE, bit 0
fine shift of WE, bit 1
fine shift IE
5
6
fine shift of CLMP, bit 0
fine shift of CLMP, bit 1
fine shift of IE, bit 0
fine shift of IE, bit 1
fine shift RE
7
fine shift of RE, bit 0
fine shift of RE, bit 1
Register 26H (SAMPLE AQUI and DISPL)
26H
0 to 7
SAMPLE AQUI and
DISPL
fills current value of CNT_A, CNT_B, CNT_D and CNT_F into
MUXA, MUXB, MUXE and MUXD (9th bit (MSB, bit 8) of CNT_B
into bit 4 of MUXC, 9th bit (MSB, bit 8) of CNT_D into bit 6 of
MUXC) when address 26H is sent
Register 27H (KADer EN’s SR)
27H
0
enable set 1
enables first rising edge of KAD signal
1
enable set 2
enables first falling edge of KAD signal
2
enable reset 1
enables second rising edge of KAD signal
3
enable reset 2
enables second falling edge of KAD signal
4
enable set 3
enables third rising edge of KAD signal
5
enable reset 3
enables third falling edge of KAD signal
6
not used
7
not used
Registers 28H, 29H, 2AH and 2BH (KADer)
28H
0 to 7
set 1
sets first rising edge of KAD signal when register data = CNT_F
29H
0 to 7
reset 1
sets first falling edge of KAD signal when register data = CNT_F
2AH
0 to 7
set 2
sets second rising edge of KAD signal when register data = CNT_F
2BH
0 to 7
reset 2
sets second falling edge of KAD signal when register data = CNT_F
Registers 2CH and 2DH (resets)
2CH
no data reset CB_intAb
resets interrupt CB_intAb when address 2C is sent
2DH
no data reset PIP_intAc
resets interrupt PIP_intAc when address 2D is sent
Registers 2EH and 2FH (window)
2EH
0 to 8
set window
sets rising edge of WINDOW signal when register data = CNT_B
2FH
0 to 8
reset window
sets falling edge of WINDOW signal when register data = CNT_B
Registers 30H, 31H, 32H and 33H (RE)
30H
0 to 7
set 1
sets first rising edge of RE signal when register data = CNT_F
31H
0 to 7
reset 1
sets first falling edge of RE signal when register data = CNT_F
32H
0 to 7
set 2
sets second rising edge of RE signal when register data = CNT_F
33H
0 to 7
reset 2
sets second falling edge of RE signal when register data = CNT_F
1996 Oct 25
19
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
REGISTER
BIT
SAA4970T
NAME
FUNCTION
Register 34H (reset CD_intDb)
34H
0 to 7
reset CD_intDb
resets interrupt CD_intDb when address 34H is sent
set IE
sets rising edge of IE signal when register data = CNT_A
Register 35H (set IE)
35H
0 to 7
Registers 36H and 37H (win_PLL)
36H
0 to 8
set win_PLL
sets rising edge of win_PLL signal when register data = CNT_D
37H
0 to 8
reset win_PLL
sets falling edge of win_PLL signal when register data = CNT_D
Registers 38H and 39H (WE)
38H
0 to 7
set WE
sets rising edge of WE signal when register data = CNT_A
39H
0 to 7
reset WE
sets falling edge of WE signal when register data = CNT_A
Register 3AH (reset IE)
3AH
0 to 7
reset IE
sets falling edge of IE signal when register data = CNT_A
Register 3BH (update VHU register)
3BH
0 to 7
update VHU register
sets rising or falling edge of VI2 when register data = CNT_F and
address 0DH or 0EH is sent
Register 3DH (interrupt + R1R2_cntr)
3DH
0
1
0
Interrupt Control (IT1)
enables interrupt CB_intAb
2
enables interrupt PIP_intAc
3
enables interrupt Gi_intAa
4
en_R1_out
output enable R1
5
oe_CK1
output enable CK1
6
en_R2_out
output enable R2
7
oe_CK2
output enable CK2
Registers 3EH and 3FH (CLMP)
3EH
0 to 7
set CLMP
sets rising edge of CLMP signal when register data = CNT_A
3FH
0 to 7
reset CLMP
sets falling edge of CLMP signal when register data = CNT_A
Table 2
α value
Table 3
β value
α VALUE
BIT 1
BIT 0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1⁄
8
1⁄
4
1⁄
2
1
1
1⁄
8
1⁄
4
1⁄
2
BIT 1
BIT 0
0
1996 Oct 25
20
β VALUE
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
Table 4
Coring value
Table 9
BIT 1
BIT 0
CORING
RANGE
0
0
+1 to −2
0
1
+3 to −4
1
0
+7 to −8
Table 5
SAA4970T
K range
Y delay
BIT 2
BIT 1
BIT 0
DELAY
0
0
0
−3
0
0
1
−2
0
1
0
−1
0
1
1
0
1
0
0
1
1
0
1
2
BIT 1
BIT 0
RANGE
1
1
0
3
0
0
±4
1
1
1
4
0
1
±6
1
0
±8
1
±12(1)
1
Table 10 PLL_div
Note
1. Not useful for PAL.
Table 6
K gain
BIT 1
BIT 0
0
0
0
0
1
1
0
1⁄
4
1⁄
2
1
1
1
Table 7
BIT 0
0
0
CK2 = 2 × 1024 × Hs
(32 MHz)
0
1
CK2 = 2 × 864 × Hs
(27 MHz)
1
0
CK2 = 2 × 768 × Hs
(24 MHz)
1
1
CK2 = 2 × 648 × Hs
(20.25 MHz)
GAIN
Read table
DIV123 control
BIT 1
BIT 0
DIV
0
0
1
0
1
1
0
1
1
1⁄
2
1⁄
3
1⁄
3
Table 8
PIXEL PER LINE TO
OBTAIN DISPLAY
CLOCK CK2 FROM Hs
BIT 1
DETECTION OF ACQUISITION POSITION
MUXB/MUXA are filled with current counter values of
CNT_B/CNT_A (horizontal and vertical acquisition
position) by a positive edge of VI1 or using ‘SAMPLE AQUI
and DISPL’ register. Thus, it is possible to detect the
location of VI1 within one line by reading MUXB (CNT_B)
after VI1 has occurred.
address XXXX XX11 (03H) MUXA sampled CNT_A
value
UV delay
BIT 2
BIT 1
BIT 0
UV DELAY
0
0
0
−2
0
0
1
−1
0
1
0
0
0
1
1
1
1
0
0
2
1
0
1
3
1
1
0
4
1
1
1
5
address XXXX XX10 (02H) MUXB sampled CNT_B
value
address XXXX XX01 (01H) MUXC bit 4:
9th-bit (MSB) of sampled CNT_B.
MUXF/MUXG are filled with current counter values of
CNT_A (horizontal acquisition position) if positive/negative
edge of PIP signal occurs.
address XXXX 1000 (08H) MUXF sampled CNT_A
value by rising PIP edge
address XXXX 1100 (0CH) MUXG sampled CNT_A
value by falling PIP edge.
1996 Oct 25
21
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
DETECTION OF DISPLAY POSITION
INTERRUPT STATUS
MUXD/MUXE are filled with current counter values of
CNT_F/CNT_D (horizontal and vertical display position)
by a positive edge of VI2 or using the ‘SAMPLE AQUI and
DISPL’ register. Thus, it is possible to detect the location
of VI2 within one line by reading MUXD (CNT_F) after VI2
has occurred.
address XXXX XX01 (01H) MUXC IT1 bit 0:
status of CB_intAb (1 = active)
address XXXX XX01 (01H) MUXC bit 1:
status of GI_intAa
address XXXX XX01 (01H) MUXC bit 2:
status of PIP_intAc
address XXXX 0000 (00H) MUXD sampled CNT_F
value
address XXXX XX01 (01H) MUXC IT2 bit 3:
status of CD_intDb.
address XXXX 0100 (04H) MUXE sampled CNT_D
value
GATE ENABLE (GE) STATUS
address XXXX XX01 (01H) MUXC bit 6:
9th bit (MSB) of sampled CNT_D.
address XXXX XX01 (01H) MUXC bit 5:
status of GE (1 = enabled).
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VI
input voltage protection range
−0.5
+7
V
VDD
digital supply voltage (pin 42 versus pins 43 and 52)
−
5.5
V
VCC
supply voltage analog buffer (pins 6 and 10 versus pin 4)
−
5.5
V
Vref
supply voltage analog reference (pins 6 and 9 versus pin 4)
−
5.25
V
IO
output current
pins 51 and 53 versus pins 43 and 52
−
16
mA
pins 29 to 36, 11, 12, 19, 20, 25 and 26 versus pins 43 and 52
−
4
mA
pins 18, 22 and 23 versus pins 43 and 52
−
8
mA
pins 14 to 17 and 54 versus pins 43 and 52
−
12
mA
pins 3, 5 and 7 versus pin 4
−
20
mA
IOsink
output sink current (pins 3, 5 and 7 versus pin 4)
−
−0.8
mA
Ptot
total power dissipation
−
550
mW
Tstg
storage temperature
−25
+125
°C
Tamb
operating ambient temperature
0
70
°C
Ves
electrostatic handling; note 1
−300
+300
V
Note
1. Charge device model class B: equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
1996 Oct 25
PARAMETER
thermal resistance from junction to ambient in free air
22
VALUE
UNIT
65
K/W
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
CHARACTERISTICS
Tamb = 0 to 70 °C; VDD = 4.5 to 5.5 V; VCC = 4.75 to 5.25 V; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
digital supply voltage
4.5
−
5.5
V
VCC
analog supply voltage
4.75
−
5.25
V
IDD
digital supply current
−
−
75
mA
ICC
analog supply current
−
−
40
mA
note 1
Digital inputs
VIL
LOW level input voltage
−0.5
−
+0.8
V
VIH
HIGH level input voltage
2.0
−
VDD + 0.5
V
ILI
input leakage current
−
−
10
µA
CIC
input capacitance (clocks)
−
−
10
pF
CID
input capacitance (data)
−
−
10
pF
CIZ
input capacitance (I/O in high Z)
−
−
10
pF
−
−
0.45
mA
Reference and current inputs
II
input current
Digital outputs
VOL
LOW level output voltage
note 2
0
−
0.6
V
VOH
HIGH level output voltage
note 2
2.4
−
VDD
V
Timing
Tcy
CLK cycle time
27
−
−
ns
kCLK
CLK duty cycle TcyHIGH/Tcy
40
−
60
%
tr
CLK rise time
−
−
5
ns
tf
CLK fall time
−
−
6
ns
tsu
input data setup time
−
−
5
ns
th
input data hold time
−
−
6
ns
tDOH
output data hold time
note 2
3
−
−
ns
tDOD
output data delay time
note 2
−
−
25
ns
10
−
35
pF
Data output loads (3-state outputs)
CL
output load capacitance
Characteristics of the D/A converters
RSLY
resolution of the Y DAC
−
9
−
bit
RSLC
resolution of the U and V DAC
−
8
−
bit
B
analog signal bandwidth (−3 dB)
20
−
−
MHz
αct
crosstalk between channels
−
−
−42
dB
DLE
differential linearity error
referred to 8 MSB’s
−
−
±0.5
LSB
ILE
integral linearity error
referred to 8 MSB’s
−
−
±1
LSB
VO
output voltage (without load)
note 3
−
2 V (p-p) −
1996 Oct 25
23
V
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
Notes to the characteristics
1. fCLK = 32 MHz, fdata = 16 MHz (rectangular full scale); without output load.
2. Timings and levels have to be measured with load circuits 1.2 kΩ connected to 3.0 V (TTL load) and CL = 25 pF.
3. A series resistor of 25 Ω is integrated at the outputs of the buffers. With 50 Ω in series, close to the output pins, the
nominal output voltage for 75 Ω line termination is 1 V (p-p).
Input/output timing
tr
handbook, full pagewidth
tf
2.4 V
CLOCK
CK1, CK2
1.5 V
0.6 V
tC27H
tC27
th
tsu
2.0 V
INPUT
DATA
0.8 V
tDOD
tDOH
2.4 V
OUTPUT
DATA
0.6 V
MGE102
Fig.12 Timing diagram.
1996 Oct 25
24
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
If the field memory data can be selectively updated, then
multi picture is possible, with or without a PIP signal
blanked in the YUV input data. In the latter case the
ECOBENDIC will present a lower clock frequency to the
ADC and memory write clock. With a PIP signal blanked in
YUV, the ECOBENDIC will just manoeuvre the PIP
position into the right memory location.
APPLICATION INFORMATION
The ECOBENDIC fits in a concept together with a triple
AD, a field memory and a microcontroller, to form a double
scan converter for YUV data.
The scan mode is AABB only. Proscan and noise
reduction are not intended with the ECOBENDIC
stand-alone. With extra processing of e.g. a Progressive
scan-Zoom and Noise reduction IC (PROZONIC
SAA4990) or Movement Estimation Line-flicker Zoom
Noise reduction IC (MELZONIC SAA4991), other scan
modes and noise reduction become possible.
The microcontroller gets the (12 MHz) clock and the
watchdog reset signals from the ECOBENDIC.
All clock signals in this concept are produced by the
ECOBENDIC. The video processing is done with a
one-clock system. The read clock is frequency divided
by 2 to obtain the write clock. With the aid of a window in
which the PLL frequency is held, a phase disturbance of a
VCR will not affect the display clock stability within the
display of the active part of the video. For compression
purposes, like 4 : 3 video on a 16 : 9 display, an external
second PLL should be used. On both the acquisition and
display side, external PLLs can be applied, with 3-state
switching of the CLK signals from the ECOBENDIC.
1996 Oct 25
25
1996 Oct 25
DYIN0
to DYIN7
DUVIN0
to DUVIN3
26
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
45
46
47
48
49
58
17
49
48
47
44
43
42
39
75
76
77
29
8
TMS4C2970 28
10
MEMORY 27
9
30
31
32
35
30
29
7
TMS4C2970 28
10
MEMORY 27
+5 V
10
29
31
6
41
24
23
21
23
22
20
15
14
16
17
+5 V
D2
D1
D0
D3
D4
D5
D6
6
42
SAA4970T
2
35
+5 V
44
1
12
23
87C654
MICROCONTROLLER
34
8
9
5
4
MGE103
Economical video processing IC
(ECOBENDIC)
11
13
2
3
24
16
33 14 15 18 19 36 37 38 39 40 41 42 43 21 25 10
SCL
13
21 20
SDA
HA
22
19
14
15
23
150 pF
53
55
56
220 Ω
VO
560
Ω
UO
5
52
YO
150 pF
22 nF
3
12 MHz
22 nF
6.8 kΩ
7
9
8
+5 V
16
4 43
VD
HD
VA
24 25 26 27 28 29 30 31 32 33 34 35 36
22 nF
+5 V
18
51
12
D8
D7
11
D9
D10
Fig.13 Application diagram.
6
40
38
24
13
19
7
37
25
12
18
8
36
26
15
16
17
11
9
4 11 21 34 46 52 59 73
13
28
32
5
8
14
27
33
4
18
26
34
3
64
n.c. 65
n.c. 66
19
25
60
61
62
35
+5 V
36
20
17
1
22
16
2
23
14
63
3
21
15
19
80
24
13
18
1
79
25
12
20
2
78
26
11
D11
44
50
72
30
7
SAA4990H
40
41
54
53
70
71
32
31
5
6
+5 V
39
55
89
33
4
9
38
56
88
34
37 10 54 1
22 nF
3
36
87 5 12 22 33 45 51 56 74 57
1
22 nF
ndbook, full pagewidth
35
2
+5 V
Philips Semiconductors
Preliminary specification
SAA4970T
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
PACKAGE OUTLINE
VSO56: plastic very small outline package; 56 leads
SOT190-1
D
E
A
X
c
y
HE
v M A
Z
56
29
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
detail X
28
w M
bp
e
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
3.3
0.3
0.1
3.0
2.8
0.25
0.42
0.30
0.22
0.14
21.65
21.35
11.1
11.0
0.75
15.8
15.2
2.25
1.6
1.4
1.45
1.30
0.2
0.1
0.1
0.90
0.55
0.13
0.012
0.004
0.12
0.11
0.01
0.017 0.0087 0.85
0.012 0.0055 0.84
0.44
0.43
0.03
0.62
0.60
0.089
0.063
0.055
inches
0.057
0.035
0.008 0.004 0.004
0.051
0.022
θ
Note
1. Plastic or metal protrusions of 0.3 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
96-04-02
SOT190-1
1996 Oct 25
EUROPEAN
PROJECTION
27
o
7
0o
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
SOLDERING
Wave soldering
Introduction
Wave soldering techniques can be used for all VSO
packages if the following conditions are observed:
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all VSO
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
1996 Oct 25
28
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Oct 25
29
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
NOTES
1996 Oct 25
30
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
NOTES
1996 Oct 25
31
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1996
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/10/01/pp32
Date of release: 1996 Oct 25
Document order number:
9397 750 01436