74HC3G14; 74HCT3G14 Triple inverting Schmitt trigger Rev. 03 — 8 May 2009 Product data sheet 1. General description The 74HC3G14; 74HCT3G14 is a high-speed Si-gate CMOS device. The 74HC3G14; 74HCT3G14 provides three inverting buffers with Schmitt trigger inputs which accept standard input signals. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. 2. Features n n n n n n n Wide supply voltage range from 2.0 V to 6.0 V High noise immunity Low power dissipation Balanced propagation delays Unlimited input rise and fall times Multiple package options ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Applications n Wave and pulse shaper for highly noisy environments n Astable multivibrators n Monostable multivibrators 4. Ordering information Table 1. Ordering information Type number 74HC3G14DP Package Temperature range Name Description Version −40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm −40 °C to +125 °C XSON8U plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; UTLP based; body 3 × 2 × 0.5 mm 74HCT3G14DP 74HC3G14DC 74HCT3G14DC 74HC3G14GD 74HCT3G14GD 74HC3G14; 74HCT3G14 NXP Semiconductors Triple inverting Schmitt trigger 5. Marking Table 2. Marking Type number Marking code 74HC3G14DP H14 74HCT3G14DP T14 74HC3G14DC H14 74HCT3G14DC T14 74HC3G14GD H14 74HCT3G14GD T14 6. Functional diagram 1A 1Y 3Y 3A 2A 2Y A 001aah728 Fig 1. Y mna025 001aah729 Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one Schmitt trigger) 7. Pinning information 7.1 Pinning 74HC3G14 74HCT3G14 74HC3G14 74HCT3G14 1A 1 8 VCC 3Y 2 7 1Y 2A 3 6 3A GND 4 5 2Y 8 VCC 3Y 2 7 1Y 2A 3 6 3A GND 4 5 2Y 001aak036 Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 5. 74HC_HCT3G14_3 Product data sheet 1 Transparent top view 001aak035 Fig 4. 1A Pin configuration SOT996-2 (XSON8U) © NXP B.V. 2009. All rights reserved. Rev. 03 — 8 May 2009 2 of 18 74HC3G14; 74HCT3G14 NXP Semiconductors Triple inverting Schmitt trigger 7.2 Pin description Table 3. Pin description Symbol Pin Description 1A, 2A, 3A 1, 3, 6 data input GND 4 ground (0 V) 1Y, 2Y, 3Y 7, 5, 2 data output VCC 8 supply voltage 8. Functional description Table 4. Function table[1] Input Output nA nY L H H L [1] H = HIGH voltage level; L = LOW voltage level. 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit −0.5 +7.0 V input clamping current VI < −0.5 V or VI > VCC + 0.5 V [1] - ±20 mA IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] - ±20 mA IO output current VO = −0.5 V to VCC + 0.5 V [1] - ±25 mA supply current [1] - +50 mA IGND ground current [1] −50 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation - 300 mW IIK ICC [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K. For XSON8U package: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 74HC_HCT3G14_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 8 May 2009 3 of 18 74HC3G14; 74HCT3G14 NXP Semiconductors Triple inverting Schmitt trigger 10. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HC3G14 Min Typ 74HCT3G14 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature −40 +25 +125 −40 +25 +125 °C 11. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 °C. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max HIGH-level VI = VT+ or VT− output voltage IO = −20 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = −20 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = −20 µA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = −4.0 mA; VCC = 4.5 V 4.18 4.32 - 4.13 - 3.7 - V IO = −5.2 mA; VCC = 6.0 V 74HC3G14 VOH VOL 5.68 5.81 - 5.63 - 5.2 - V LOW-level VI = VT+ or VT− output voltage IO = 20 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 µA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1.0 - ±1.0 µA II input leakage current ICC supply current per input pin; VCC = 6.0 V; VI = VCC or GND; IO = 0 A; - - 1.0 - 10 - 20 µA CI input capacitance - 2.0 - - - - - pF 4.4 4.5 - 4.4 - 4.4 - V 4.18 4.32 - 4.13 - 3.7 - V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V VI = VCC or GND; VCC = 5.5 V - - ±0.1 - ±1.0 - ±1.0 µA 74HCT3G14 VOH HIGH-level VI = VT+ or VT− output voltage IO = −20 µA; VCC = 4.5 V IO = −4.0 mA; VCC = 4.5 V VOL II LOW-level VI = VIH or VIL output voltage IO = 20 µA; VCC = 4.5 V input leakage current 74HC_HCT3G14_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 8 May 2009 4 of 18 74HC3G14; 74HCT3G14 NXP Semiconductors Triple inverting Schmitt trigger Table 7. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 °C. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max ICC supply current per input pin; VCC = 5.5 V; VI = VCC or GND; IO = 0 A; - - 1.0 - 10 - 20 µA ∆ICC additional per input; supply current VCC = 4.5 V to 5.5 V; VI = VCC − 2.1 V; IO = 0 A - - 300 - 375 - 410 µA CI input capacitance - 2.0 - - - - - pF Table 8. Transfer characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol Parameter 25 °C Conditions −40 °C to +125 °C Unit Min Typ Max Min Max (85 °C) Max (125 °C) VCC = 2.0 V 1.00 1.18 1.50 1.00 1.50 1.50 V VCC = 4.5 V 2.30 2.60 3.15 2.30 3.15 3.15 V VCC = 6.0 V 3.00 3.46 4.20 3.00 4.20 4.20 V VCC = 2.0 V 0.30 0.60 0.90 0.30 0.90 0.90 V VCC = 4.5 V 1.13 1.47 2.00 1.13 2.00 2.00 V VCC = 6.0 V 1.50 2.06 2.60 1.50 2.60 2.60 V VCC = 2.0 V 0.30 0.60 1.00 0.30 1.00 1.00 V VCC = 4.5 V 0.60 1.13 1.40 0.60 1.40 1.40 V VCC = 6.0 V 0.80 1.40 1.70 0.80 1.70 1.70 V VCC = 4.5 V 1.20 1.58 1.90 1.20 1.90 1.90 V VCC = 5.5 V 1.40 1.78 2.10 1.40 2.10 2.10 V VCC = 4.5 V 0.50 0.87 1.20 0.50 1.20 1.20 V VCC = 5.5 V 0.60 1.11 1.40 0.60 1.40 1.40 V VCC = 4.5 V 0.40 0.71 - 0.40 - - V VCC = 5.5 V 0.40 0.67 - 0.40 - - V 74HC3G14 VT+ VT− VH positive-going threshold voltage negative-going threshold voltage hysteresis voltage see Figure 6, Figure 7 see Figure 6, Figure 7 (VT+ − VT−); see Figure 6, Figure 7 and Figure 9 74HCT3G14 VT+ VT− VH positive-going threshold voltage see Figure 6, Figure 7 negative-going threshold voltage see Figure 6, Figure 7 hysteresis voltage (VT+ − VT−); see Figure 6, Figure 7 and Figure 8 74HC_HCT3G14_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 8 May 2009 5 of 18 74HC3G14; 74HCT3G14 NXP Semiconductors Triple inverting Schmitt trigger 11.1 Waveforms transfer characteristics VO VT+ VI VH VT− VI VH VT− Fig 6. VT+ VO mna207 mna208 Transfer characteristic Fig 7. mna031 2.0 Definition of VT+, VT− and VH mna032 3.0 ICC (mA) ICC (mA) 2.0 1.0 1.0 0 0 0 2.5 VI (V) a. VCC = 4.5 V. Fig 8. 0 5.0 3.0 VI (V) 6.0 b. VCC = 5.5 V. Typical 74HCT3G14 transfer characteristics 74HC_HCT3G14_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 8 May 2009 6 of 18 74HC3G14; 74HCT3G14 NXP Semiconductors Triple inverting Schmitt trigger mna028 100 mna029 1.0 ICC (mA) ICC (µA) 0.8 0.6 50 0.4 0.2 0 0 0 1.0 VI (V) 0 2.0 a. VCC = 2.0 V 2.5 VI (V) 5.0 b. VCC = 4.5 V mna030 1.6 ICC (mA) 0.8 0 0 c. Fig 9. 3.0 VI (V) 6.0 VCC = 6.0 V Typical 74HC3G14 transfer characteristics 74HC_HCT3G14_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 8 May 2009 7 of 18 74HC3G14; 74HCT3G14 NXP Semiconductors Triple inverting Schmitt trigger 12. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol Parameter 25 °C Conditions −40 °C to +125 °C Unit Min Typ Max Min Max (85 °C) Max (125 °C) VCC = 2.0 V - 53 125 - 155 190 ns VCC = 4.5 V - 16 25 - 31 38 ns VCC = 6.0 V - 13 21 - 26 32 ns VCC = 2.0 V - 20 75 - 95 110 ns VCC = 4.5 V - 7 15 - 19 22 ns VCC = 6.0 V - 5 13 - 16 19 ns - 10 - - - - pF - 21 32 - 40 48 ns - 6 15 - 19 22 ns - 10 - - - - pF 74HC3G14 propagation delay tpd transition time tt power dissipation capacitance CPD nA to nY; see Figure 10 nY; see Figure 10 [1] [2] VI = GND to VCC [3] nA to nY; see Figure 10 [1] 74HCT3G14 propagation delay tpd VCC = 4.5 V tt transition time CPD power dissipation capacitance nY; see Figure 10 [2] VCC = 4.5 V VI = GND to VCC − 1.5 V [1] tpd is the same as tPLH and tPHL [2] tt is the same as tTLH and tTHL [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. [3] 74HC_HCT3G14_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 8 May 2009 8 of 18 74HC3G14; 74HCT3G14 NXP Semiconductors Triple inverting Schmitt trigger 13. Waveforms VI nA input VM VM GND t PHL t PLH VOH nY output 90 % VM VM 10 % VOL t THL t TLH mna722 Measurement points are given in Table 10. VOL and VOH are typical voltage output levels that occur with the output load. Fig 10. The data input (nA) to output (nY) propagation delays and output transition times Table 10. Measurement points Type Input Output VM VM 74HC3G14 0.5VCC 0.5VCC 74HCT3G14 1.3 V 1.3 V 74HC_HCT3G14_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 8 May 2009 9 of 18 74HC3G14; 74HCT3G14 NXP Semiconductors Triple inverting Schmitt trigger VI tW 90 % negative pulse VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT RT CL 001aad983 Test data is given in Table 11. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 11. Test circuit for measuring switching times Table 11. Test data Type Input Load VI tr, tf CL RL tPHL, tPLH 74HC3G14 GND to VCC ≤ 6 ns 50 pF 1 kΩ open 74HCT3G14 GND to 3.0 V ≤ 6 ns 50 pF 1 kΩ open 74HC_HCT3G14_3 Product data sheet S1 position © NXP B.V. 2009. All rights reserved. Rev. 03 — 8 May 2009 10 of 18 74HC3G14; 74HCT3G14 NXP Semiconductors Triple inverting Schmitt trigger 14. Application information The slow input rise and fall times cause additional power dissipation, which can be calculated using the following formula: Padd = fi × (tr × ∆ICC(AV) + tf × ∆ICC(AV)) × VCC where: Padd = additional power dissipation (µW); fi = input frequency (MHz); tr = input rise time (ns); 10 % to 90 %; tf = input fall time (ns); 90 % to 10 %; ∆ICC(AV) = average additional supply current (µA). ∆ICC(AV) differs with positive or negative input transitions, as shown in Figure 12 and Figure 13. An example of a relaxation circuit using the 74HC3G14/74HCT3G14 is shown in Figure 14. mna036 200 ∆ICC(AV) (µA) 150 positive-going edge 100 50 negative-going edge 0 0 2.0 4.0 VCC (V) 6.0 linear change of VI between 0.1VCC to 0.9VCC. Fig 12. ∆ICC(AV) as a function of VCC for 74HC3G14 74HC_HCT3G14_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 8 May 2009 11 of 18 74HC3G14; 74HCT3G14 NXP Semiconductors Triple inverting Schmitt trigger mna058 200 ∆ICC(AV) (µA) 150 positive-going edge 100 negative-going edge 50 0 0 2 4 VCC (V) 6 linear change of VI between 0.1VCC to 0.9VCC. Fig 13. ∆ICC(AV) as a function of VCC for 74HCT3G14 R C mna035 1 T 1 0.8 × RC For 74HC3G14: f = --- ≈ ---------------------- 1 T 1 0.67 × RC For 74HCT3G14: f = --- ≈ ------------------------- Fig 14. Relaxation oscillator 74HC_HCT3G14_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 8 May 2009 12 of 18 74HC3G14; 74HCT3G14 NXP Semiconductors Triple inverting Schmitt trigger 15. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- Fig 15. Package outline SOT505-2 (TSSOP8) 74HC_HCT3G14_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 8 May 2009 13 of 18 74HC3G14; 74HCT3G14 NXP Semiconductors Triple inverting Schmitt trigger VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 MO-187 Fig 16. Package outline SOT765-1 (VSSOP8) 74HC_HCT3G14_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 8 May 2009 14 of 18 74HC3G14; 74HCT3G14 NXP Semiconductors Triple inverting Schmitt trigger XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm B D SOT996-2 A A E A1 detail X terminal 1 index area e1 v w b e L1 1 4 8 5 C C A B C M M y y1 C L2 L X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 b D E e e1 L L1 L2 v w y y1 mm 0.5 0.05 0.00 0.35 0.15 2.1 1.9 3.1 2.9 0.5 1.5 0.5 0.3 0.15 0.05 0.6 0.4 0.1 0.05 0.05 0.1 REFERENCES OUTLINE VERSION IEC SOT996-2 --- JEDEC JEITA --- EUROPEAN PROJECTION ISSUE DATE 07-12-18 07-12-21 Fig 17. Package outline SOT996-2 (XSON8U) 74HC_HCT3G14_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 8 May 2009 15 of 18 74HC3G14; 74HCT3G14 NXP Semiconductors Triple inverting Schmitt trigger 16. Abbreviations Table 12. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 17. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT3G14_3 20090508 Product data sheet - 74HC_HCT3G14_2 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Added type number 74HC3G14GD and 74HCT3G14GD (XSON8U package) 74HC_HCT3G14_2 20031104 Product specification - 74HC_HCT3G14_1 74HC_HCT3G14_1 20020723 Product specification - - 74HC_HCT3G14_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 8 May 2009 16 of 18 74HC3G14; 74HCT3G14 NXP Semiconductors Triple inverting Schmitt trigger 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 18.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74HC_HCT3G14_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 8 May 2009 17 of 18 NXP Semiconductors 74HC3G14; 74HCT3G14 Triple inverting Schmitt trigger 20. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 11.1 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Waveforms transfer characteristics. . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Application information. . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 8 May 2009 Document identifier: 74HC_HCT3G14_3