PHILIPS N74F8963Y

Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
• Multiple GND pins minimize ground bounce
• Glitch–free power up/power down
FEATURES
• Octal latched transceiver
• Drives heavily loaded backplanes with
operation
equivalent load impedances down to 10Ω
• High drive (100mA) open collector drivers
DESCRIPTION
The 74F8962 and 74F8963 are octal
bidirectional latched transceivers and are
intended to provide the electrical interface to
a high performance wired-OR bus. The B port
inverting drivers are low-capacitance open
collector with controlled ramp and are
designed to sink 100mA from 2 volts. The B
port inverting receivers have a 150mV
threshold region.
on B port
• Reduced voltage swing (1 volt) produces
less noise and reduces power consumption
• High speed operation enhances
performance of backplane buses and
facilitates incident wave switching
• Compatible with IEEE 896 futurebus
74F8962/8963
power consumption and a series diode on
the drivers to reduce capacitive loading.
Incident wave switching to 9Ω is guaranteed.
The voltage swing is much less for BTL, so is
its receiver threshold region, therefore noise
margins are excellent.
BTL offers low power consumption, low
ground bounce, EMI and crosstalk, low
capacitive loading, superior noise margin and
low propagation delays. This results in a high
bandwidth, reliable backplane.
The 74F8962 and 74F8963 A ports have TTL
3-state drivers and TTL receivers with a latch
function.
standards
The B port interfaces to ‘Backplane
Transceiver Logic’ (BTL). BTL features a
reduced (1V to 2V) voltage swing for lower
• Built–in precision band–gap reference
provides accurate receiver thresholds and
improved noise immunity
TYPE
The 74F8963 is the non-inverting version of
74F8962.
TYPICAL PROPAGATION DELAY
TYPICAL SUPPLY CURRENT( TOTAL)
74F8962
6.5ns
90mA
74F8963
5.5ns
90mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
DESCRIPTION
44–pin Quad Flat Pack1
N74F8962Y, N74F8963Y
44–pin Plastic Leaded Chip Carrier
N74F8962A, N74F8963A
Note to ordering information
1. Flatpack package is not available at this time.
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
74F (U.L.)
HIGH/LOW
DESCRIPTION
LOAD VALUE
HIGH/LOW
AI0 – AI8
PNP latched inputs
1.0/0.167
20µA/100µA
B0 – B8
Data inputs with threshold circuitry
5.0/0.167
100µA/100µA
OEAB, OEBA
Output enable inputs (active low)
1.0/0.033
20µA/20µA
LEAB, LEBA
Latch enable inputs (active low)
1.0/0.033
20µA/20µA
AO0 – AO8
3–state outputs
150/40
3mA/24mA
OC/166.7
OC/100mA
B0 – B8
Open collector outputs
Notes to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
2. OC = Open collector.
March 11, 1993
1
853–1425 09230
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
PIN CONFIGURATION FLATPACK AND PLCC
74F8962/8963
IEC/IEEE SYMBOL
74F8962
74F8962
GND
6
AO1
5
AI1 AO0
4
3
AI0
2
VCC OEBA LEBA BO
1
44
43
42
GND
41
B1
40
AI2
7
39
GND
AO2
8
38
B2
A13
9
AO3
24
EN1
25
EN2
43
EN3
44
EN4
2
3
37
GND
10
36
B3
AI4
11
35
GND
GND
12
34
B4
AO4
13
33
GND
42
1
2
4
3D
4
5
40
7
8
38
9
10
11
13
AI5
14
32
B5
AO5
15
31
GND
AI6
16
30
B6
AO6
17
29
GND
36
34
14
15
32
16
17
30
19
18
19
GND AI7
20
AO7
21
22
AI8 AO8
23
24
25
26
27
VCC LEAB OEAB B8
GND
20
21
28
22
B7
PIN DESCRIPTION
SYMBOL
PINS
TYPE
AI0 – AI8
2, 4, 7, 9, 11, 14, 16, 19, 21
Input
B0 – B8
42, 40, 38, 36, 34, 32, 30, 28, 26
I/O
Data input / open collector output, high current drives.
OEAB
25
Input
Output enable input. Enables the B outputs when low.
OEBA
44
Input
Output enable input. Enables the A outputs when high.
LEAB
24
Input
Latch enable input. Enables the AB latches low.
LEBA
43
Input
Latch enable input. Enables the BA latches low.
AO0 – AO8
3, 5, 8, 10, 13, 15, 17, 20, 22
Output
TTL 3–state outputs.
GND
6, 12, 18, 27, 29, 31, 33, 35, 37, 39, 41
Ground
Grounds
VCC
1, 23
Power
Positive supply voltages
March 11, 1993
28
NAME AND FUNCTION
PNP latched inputs.
2
26
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
74F8962/8963
LOGIC SYMBOL FOR 74F8962
74F8962
2
3
4
5
7
8
9
10
11
13 14
15 16 17 19
20 21
22
AI0 AO0 AI1 AO1 AI2 AO2 AI3 AO3 AI4 AO4 AI5 AO5 AI6 AO6 AI7 AO7 AI8 AO8
25
OEAB
24
LEAB
43
LEBA
44
OEBA
VCC = Pin 1, 23
GND = Pin 6, 12, 18, 27, 29, 31, 33, 35, 37, 39, 41
B0 B1 B2
B3 B4 B5 B6 B7 B8
42 40 38
36
34 32
30 28 26
LOGIC SYMBOL FOR 74F8963
74F8963
2
3
4
5
7
8
9
10
11
13 14
15 16 17 19
20 21
22
AI0 AO0 AI1 AO1 AI2 AO2 AI3 AO3 AI4 AO4 AI5 AO5 AI6 AO6 AI7 AO7 AI8 AO8
25
OEAB
24
LEAB
43
LEBA
44
OEBA
B0 B1 B2 B3 B4 B5 B6 B7 B8
VCC = Pin 1, 23
GND = Pin 6, 12, 18, 27, 29, 31, 33, 35, 37, 39, 41
March 11, 1993
42 40 38
36
34 32
3
30 28 26
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
74F8962/8963
LOGIC DIAGRAM
74F8963
74F8962
OEAB
25
LEBA
43
LEAB
24
OEBA
44
2
AI0
3
AO0
4
AI1
5
AO1
7
AI2
8
AO2
9
AI3
10
AO3
11
AI4
13
AO4
OEAB
LEBA
43
LEAB
24
OEBA 44
Data
E
Q
Data
E
Q
Data
E
Q
Data
E
Q
Data
E
Q
Q
42
2
AI0
B0
3
Data
E
Q
AO0
40
4
AI1
B1
5
Data
E
Q
AO1
38
7
AI2
B2
8
Data
E
Q
AO2
36
9
AI3
B3
10
Data
E
Q
AO3
11
34
AI4
B4
13
Data
E
AO4
14
Data
E
AI5
15
AO5
Q
Q
Data
E
17
32
AO6
Q
15
AO5
Data
E
30
AI6
B6
AO6
Q
28
AI7
B7
Data
E
Data
E
Q
Q
Q
Data
E
Q
Q
40
B1
Data
E
Q
38
B2
Data
E
Q
36
B3
Data
E
Q
34
B4
Data
E
Q
Q
32
B5
Data
E
Q
Q
30
B6
Data
E
Q
28
Q
B7
Data
E
21
26
AI8
B8
Data
E
Q
22
Data
E
AO8
VCC = Pin 1, 23
GND = Pin 6, 12, 18, 27, 29, 31, 33, 37, 39, 41
March 11, 1993
Data
E
Data
E
AO7
22
AO8
Q
B0
Data
E
20
21
AI8
Data
E
42
19
20
AO7
Q
Data
E
17
Data
E
Q
Data
E
Q
16
19
AI7
Q
Data
E
AI5
B5
Data
E
Q
Data
E
14
16
AI6
25
4
Q
Data
E
26
B8
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
74F8962/8963
FUNCTION TABLE FOR 74F8962
INPUTS
LATCH STATES
OUTPUTS
AIn
Bn*
LEAB
LEBA
OEAB
OEBA
AB
BA
AOn
Bn
H
H
L
L
H
H
H
H
Z
X
L
L
L
L
H
H
L
L
Z
X
X
X
H
H
H
H
Qn
Qn
Z
X
H
–
L
X
L
H
H
Qn
Z
L
L
–
L
X
L
H
L
Qn
Z
H**
X
H
X
L
H
L
Qn
H
L
X
OPERATING MODE
B and AO disabled
AO 3–state, transparent data from AI to B
B disabled, transparent data from B to AO
X
L
X
L
H
L
Qn
L
H
X
X
X
H
X
L
H
Qn
Qn
Z
Qn
X
X
X
H
H
L
Qn
Qn
Qn
X
B disabled, latched to AO
Latched state to AO and B
X
X
H
H
L
L
Qn
Qn
Qn
Qn
H
–
L
L
L
L
H
L
H
L
L
–
L
L
L
L
L
H
L
H**
AO 3–state, latched data to B
Read back from AI to B to AO
(both latches transparent)
Notes to function table for 74F8962
1. H = High voltage level
2. L = Low voltage level
3. X = Don’t care
4. – = Input not externally driven
5. Z = High impedance ”off’ state
6. Qn = High or low voltage level one setup time prior to the low–to–high LEXX transition.
7. H**= Goes to level of pullup voltage.
8. B* = Precaution should be taken to insure B inputs do not float. If they do they are equal to low state.
FUNCTION TABLE FOR 74F8963
INPUTS
LATCH STATES
OUTPUTS
AIn
Bn*
LEAB
LEBA
OEAB
OEBA
AB
BA
AOn
Bn
H
H
L
L
H
H
L
L
Z
X
L
L
L
L
H
H
H
H
Z
X
X
X
H
H
H
H
Qn
Qn
Z
X
H
–
L
X
L
H
L
Qn
Z
H
L
–
L
X
L
H
H
Qn
Z
L
X
H
X
L
H
L
Qn
L
H
X
OPERATING MODE
B and AO disabled
AO 3–state, transparent data from AI to B
B disabled, transparent data from B to AO
X
L
X
L
H
L
Qn
H
L
X
X
X
H
X
L
H
Qn
Qn
Z
Qn
X
X
X
H
H
L
Qn
Qn
Qn
X
B disabled, latched to AO
AO 3–state, latched data to B
X
X
H
H
L
L
Qn
Qn
Qn
Qn
Latched state to AO and B
H
–
L
L
L
L
L
L
H
H**
Read back from AI to B to AO
L
–
L
L
L
L
H
L
L
L
(both latches transparent)
Notes to function table for 74F8963
1. H = High voltage level
2. L = Low voltage level
3. X = Don’t care
4. – = Input not externally driven
5. Z = High impedance ”off” state
6. Qn = High or low voltage level one setup time prior to the low–to–high LEXX transition.
7. H**= Goes to level of pullup voltage.
8. B* = Precaution should be taken to insure B inputs do not float. If they do they are equal to low state.
March 11, 1993
5
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
74F8962/8963
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
PARAMETER
SYMBOL
VCC
Supply voltage
VIN
Input voltage
IIN
Input current
VOUT
Voltage applied to output in high output state
IOUT
Current applied to output in low output state
Tamb
Operating free air temperature range
Tstg
Storage temperature range
RATING
UNIT
–0.5 to +7.0
V
OEBA, OEAB, LEBA, LEAB
–0.5 to +7.0
V
AI0 – AI8, B0 – B8
–0.5 to +5.5
V
–40 to +5
mA
–0.5 to VCC
V
AO0 – AO8
48
mA
B0 – B8
200
mA
0 to +70
°C
–65 to +150
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
VCC
Supply voltage
VIH
High–level input voltage
VIL
Low–level input voltage
MIN
NOM
MAX
UNIT
4.5
5.0
5.5
V
Except B0 – B8
2.0
V
B0 – B8
1.62
V
Except B0 – B8
0.8
V
B0 – B8
1.47
V
–18
mA
IIk
Input clamp current
IOH
High–level output current
AO0 – AO8
–3
mA
IOL
Low–level output current
AO0 – AO8
24
mA
B0 – B8
100
mA
+70
°C
Tamb
Operating free air temperature
range
March 11, 1993
0
6
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
74F8962/8963
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
PARAMETER
SYMBOL
TEST
LIMITS
CONDITIONS1
IOH
High-level output current
B0 – B8
VCC = MAX, VIL = MAX, VIH = MIN, VOH = 2.1V
IOFF
VOH
Power-off output current
B0 – B8
VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 2.1V
High-level output voltage
AO0 – AO84
VCC = MAX, VIL = MAX, VIH = MIN, IOH = –3mA
AO0 –
VOL
VIK
II
IIH
IIL
Low-level output voltage
B0 – B8
Input clamp voltage
TYP2
2.5
VCC = MIN,
IOL = 24mA
VIL = MAX
IOL = 100mA
0.75
VIH = MIN
IOL = 4mA
0.40
1.0
UNIT
MAX
100
µA
100
µA
VCC
V
0.50
V
1.10
V
V
VCC = MIN, II = IIK
-1.2
V
VCC = MAX, VI = 7.0V
100
µA
Input current at
maximum input voltage
OEAB, OEBA,
LEAB, LEBA,
AI0 – AI8
VCC = MAX, VI = 5.5V
1
mA
VCC = MAX, VI = 2.7V
20
µA
High-level input current
B0 – B8
OEAB, OEBA,
LEAB, LEBA,
AI0 – AI8
B0 – B8
VCC = MAX, VI = 2.1V
100
µA
VCC = MAX, VI = 0.5V
–100
µA
Low-level input current
OEAB, OEBA,
LEAB, LEBA,
AI0 – AI8
B0 – B8
VCC = MAX, VI = 0.3V
–100
µA
AO0 – AO8
VCC = MAX, VO = 2.7V
50
µA
VCC = MAX, VI = 0.5V
–50
µA
-150
mA
IOZH
Off state output current,
high-level voltage applied
IOZL
Off state output current,
low-level voltage applied
IOS
Short circuit output
current3
ICC
AO84
MIN
Supply current (total)
VCC = MAX, Bn = 1.3V, OEBA = 0.8V,
AO0 –
74F8962
’F8960 OEAB = 2.7V
AO8
only
74F8963
-60
VCC = MAX, Bn = 1.8V, OEBA = 0.8V,
OEAB = 2.7V
ICCH
VCC = MAX
80
110
mA
ICCL
VCC = MAX, VIL = 0.5V
105
145
mA
80
110
mA
ICCZ
NOTES TO DC ELECTRICAL CHARACTERISTICS
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
4. Due to test equipment limitations, actual test conditions are for VIH = 1.8V and VIL = 1.3V.
March 11, 1993
7
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
74F8962/8963
AC ELECTRICAL CHARACTERISTICS FOR 74F8962
A PORT LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST
CONDITION
VCC = +5.0V
CL = 50pF,
RL = 500Ω
Tamb = 0°C to
+70°C
VCC = +5.0V ± 10%
CL = 50pF,
RL = 500Ω
Tamb = 0°C to
+70°C
VCC = +5.0V ± 5%
CL = 50pF,
RL = 500Ω
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Waveform 1, 2
5.0
3.5
7.0
5.5
10.0
8.5
4.5
3.5
11.0
8.5
4.5
3.5
10.5
8.5
ns
Propagation delay
LEBA to AOn
Waveform 1, 2
5.5
4.5
7.0
6.5
10.0
9.5
5.0
4.5
10.0
9.5
5.0
4.5
10.0
9.5
ns
tPZH
tPZL
Output enable time to high or
low, OEBA to AOn
Waveform 5, 6
7.5
8.5
9.5
10.5
12.5
13.0
6.5
7.5
13.5
14.5
6.5
7.5
13.0
13.5
ns
tPHZ
tPLZ
Output disable from high or low,
OEBA to AOn
Waveform 5, 6
3.5
4.5
5.5
6.5
8.5
9.5
2.5
4.0
10.0
10.0
2.5
4.0
9.0
9.5
ns
tsk(o)
Skew between receivers in
same package
1.5
2.0
4.0
ns
tPLH
tPHL
Propagation delay
Bn to AOn
tPLH
tPHL
Waveform 4
4.0
B PORT LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST
CONDITION
VCC = +5.0V
CD = 30pF,
RU = 9Ω
Tamb = 0°C to
+70°C
VCC = +5.0V ± 10%
CD = 30pF,
RU = 9Ω
Tamb = 0°C to
+70°C
VCC = +5.0V ± 5%
CD = 30pF,
RU = 9Ω
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tPLH
tPHL
Propagation delay
AIn to Bn
Waveform 1, 2
3.5
4.0
5.5
6.0
8.5
9.5
3.0
3.5
9.0
10.5
3.0
3.5
9.0
10.0
ns
tPLH
tPHL
Propagation delay
LEAB to Bn
Waveform 1, 2
4.0
5.0
6.0
7.0
8.5
10.5
3.5
5.0
9.5
10.5
3.5
5.0
9.5
10.5
ns
tPLH
tPHL
Output enable/disable time
OEBA to Bn
Waveform 1
3.5
3.0
5.0
4.0
8.0
8.0
3.0
2.5
8.5
8.5
3.0
2.5
8.0
8.5
ns
tTLH
tTHL
Transition time, Bn port
10% to 90%, 90% to 10%
Test circuit and
waveforms
1.0
1.0
1.2
2.0
1.6
2.5
1.0
1.0
2.5
3.5
1.0
1.0
2.5
3.5
ns
tsk(o)
Skew between drivers in same
package
0.5
2.5
3.0
ns
Waveform 4
3.0
AC SETUP REQUIREMENTS FOR 74F8962
LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST
CONDITION
VCC = +5.0V
CL = 50pF,
RL = 500Ω
MIN
TYP
MAX
Tamb = 0°C to
+70°C
VCC = +5.0V ± 10%
CL = 50pF,
RL = 500Ω
MIN
MAX
Tamb = 0°C to
+70°C
VCC = +5.0V ± 5%
CL = 50pF,
RL = 500Ω
MIN
UNIT
MAX
tsu(H)
tsu(L)
Setup time, high or low
AIn to LEAB
Waveform 3
3.0
1.0
3.5
2.0
3.0
1.5
ns
th(H)
th(L)
Hold time, high or low
AIn to LEAB
Waveform 3
3.0
0.0
3.5
0.0
3.0
0.0
ns
tsu(H)
tsu(L)
Setup time, high or low
Bn to LEBA
Waveform 3
2.0
1.0
2.5
1.0
2.0
1.0
ns
th(H)
th(L)
Hold time, high or low
Bn to LEBA
Waveform 3
3.0
1.5
3.5
2.0
3.0
2.0
ns
tw(L)
LEAB or LEBA pulse width, low
Waveform 3
4.5
4.5
4.5
ns
March 11, 1993
8
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
74F8962/8963
AC ELECTRICAL CHARACTERISTICS FOR 74F8963
A PORT LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST
CONDITION
VCC = +5.0V
CL = 50pF,
RL = 500Ω
Tamb = 0°C to
+70°C
VCC = +5.0V ± 10%
CL = 50pF,
RL = 500Ω
Tamb = 0°C to
+70°C
VCC = +5.0V ± 5%
CL = 50pF,
RL = 500Ω
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Waveform 1, 2
3.5
2.5
5.5
4.0
8.0
7.0
3.0
2.0
9.0
7.5
3.0
2.0
8.0
7.5
ns
Propagation delay
LEBA to AOn
Waveform 1, 2
6.0
4.0
7.5
5.5
10.0
8.5
5.0
3.5
11.5
9.0
5.0
3.5
10.0
8.5
ns
tPZH
tPZL
Output enable time to high or
low, OEBA to AOn
Waveform 5, 6
9.0
10.0
11.0
12.0
15.0
16.0
8.5
9.0
16.5
18.0
8.5
9.0
15.5
16.5
ns
tPHZ
tPLZ
Output disable time from high or
low, OEBA to AOn
Waveform 5, 6
4.0
5.5
6.0
7.0
9.0
11.0
3.0
5.0
10.5
12.0
3.0
5.0
9.5
11.0
ns
tsk(o)
Skew between receivers in
same package
1.5
2.0
4.0
ns
tPLH
tPHL
Propagation delay
Bn to AOn
tPLH
tPHL
Waveform 4
4.0
B PORT LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST
CONDITION
VCC = +5.0V
CD = 30pF,
RU = 9Ω
Tamb = 0°C to
+70°C
VCC = +5.0V ± 10%
CD = 30pF,
RU = 9Ω
Tamb = 0°C to
+70°C
VCC = +5.0V ± 5%
CD = 30pF,
RU = 9Ω
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tPLH
tPHL
Propagation delay
AIn to Bn
Waveform 1, 2
2.0
2.0
4.0
3.5
6.5
6.5
1.5
1.5
7.0
6.5
2.0
2.0
7.0
6.5
ns
tPLH
tPHL
Propagation delay
LEAB to Bn
Waveform 1, 2
3.5
2.5
5.0
4.0
8.0
7.0
3.0
2.0
8.5
8.0
3.5
2.5
8.5
8.0
ns
tPLH
tPHL
Output enable/disable time
OEBA to Bn
Waveform 1
3.5
3.0
5.5
5.0
9.0
7.5
2.5
2.5
9.5
8.5
2.5
2.5
9.0
8.0
ns
tTLH
tTHL
Transition time, Bn port
10% to 90%, 90% to 10%
Test circuit and
waveforms
1.0
1.0
1.2
2.0
1.6
2.5
1.0
1.0
2.5
3.5
1.0
1.0
2.5
3.5
ns
tsk(o)
Skew between drivers in same
package
0.5
2.0
3.0
ns
Waveform 4
3.0
AC SETUP REQUIREMENTS FOR 74F8963
LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST
CONDITION
VCC = +5.0V
CL = 50pF,
RL = 500Ω
MIN
TYP
MAX
Tamb = 0°C to
+70°C
VCC = +5.0V ± 10%
CL = 50pF,
RL = 500Ω
MIN
MAX
Tamb = 0°C to
+70°C
VCC = +5.0V ± 5%
CL = 50pF,
RL = 500Ω
MIN
UNIT
MAX
tsu(H)
tsu(L)
Setup time, high or low
AIn to LEAB
Waveform 3
4.0
1.0
4.5
1.5
4.0
1.0
ns
th(H)
th(L)
Hold time, high or low
AIn to LEAB
Waveform 3
2.5
0.0
3.0
0.0
2.5
0.0
ns
tsu(H)
tsu(L)
Setup time, high or low
Bn to LEBA
Waveform 3
2.0
1.0
2.5
1.0
2.0
1.0
ns
th(H)
th(L)
Hold time, high or low
Bn to LEBA
Waveform 3
2.5
1.0
3.0
1.5
3.0
1.0
ns
tw(L)
LEAB or LEBA pulse width, low
Waveform 3
4.5
5.5
5.5
ns
March 11, 1993
9
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers
(open-collector)
74F8962/8963
AC WAVEFORMS
AIn, Bn,
LEAB, LEBA
OEAB
VM
tPLH
AOn, Bn
AIn, Bn,
LEAB, LEBA
VM
VM
tPHL
tPHL
VM
VM
VM
VM
An, Bn
AOn, Bn
VM
VM
VM
th(L)
tsk(o)
th(H)
tw(L)
tsu(L)
VM
LEAB, LEBA
VM
VM
VM
tPZH
Waveform 4. Output skew
VM
OEAB
VOH -0.3V
tPHZ
An
VM
AOn, Bn
VM
Waveform 3. Data setup and hold times and LEAB/LEBA pulse widths
OEAB
VM
VM
tsu(H)
VM
Waveform 2. Propagation delay for data or latch enable to
output
Waveform 1. Propagation delay for data or output enable or
latch enable to output
AIn, Bn
tPLH
VM
tPZL
VM
tPLZ
VM
An
0V
VOL +0.3V
Waveform 5. 3–state output enable time to high level
and output disable time from high level
Waveform 6. 3-state output enable time to low level
and output disable time from low level
NOTES TO AC WAVEFORMS
1. For all waveforms, VM = 1.5V.
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST
SWITCH
tPLZ, tPZL
closed
All other
open
tw
90%
NEGATIVE
PULSE
VCC
10%
VIN
RL
VOUT
AMP (V)
VM
VM
7.0V
PULSE
GENERATOR
90%
10%
tTHL (tf )
tTLH (tr )
tTLH (tr )
tTHL (tf )
Low V
D.U.T.
RT
CL
AMP (V)
RL
90%
POSITIVE
PULSE
VM
VM
10%
Test circuit for 3–state outputs on A port
VCC
90%
10%
tw
Low V
7.0V
Input pulse definition
VIN
RU
VOUT
PULSE
GENERATOR
D.U.T.
RT
CD
INPUT PULSE REQUIREMENTS
family
tTLH
tw
74F amplitude Low V VM rep. rate
A port
3.0V
0.0V
1.5V
1MHz
500ns
2.5ns
2.5ns
B port
3.0V
1.0V
1.5V
1MHz
500ns
4.0ns
4.0ns
Test circuit for outputs on B port
DEFINITIONS:
RL = Load resistor; see AC electrical characteristics for value.
CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
RU = Pull up resistor; see AC electrical characteristics for value.
CD = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
RT = Termination resistance should be equal to ZOUT of pulse generators.
March 11, 1993
tTHL
10