INTEGRATED CIRCUITS 74F841/842 Bus interface latches Product data Replaces datasheet 74F841/842/843/845/846 of 1999 Jun 23 2004 Jan 23 Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) FEATURES 74F841/74F842 DESCRIPTION • High speed parallel latches • Extra data width for wide address/data paths or buses carrying The 74F841 and 74F842 bus interface latches are designed to provide extra data width for wider address/data paths of buses carrying parity. parity The 74F841 consists of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the set-up and hold time is latched. • High impedance NPN base input structure minimizes bus loading • IIL is 20 µA for minimum bus loading • Buffered control inputs to reduce AC effects • Ideal where high speed, light loading, or increased fan-in are Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the output is in the high-impedance state. required as with MOS microprocessors • Positive and negative over-shoots are clamped to ground • 3-State outputs glitch free during power-up and power-down • 48 mA sink current • Slim dual in-line 300 mil package • Broadside pinout The 74F842 is the inverted output version of the 74F841. TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74F841, 74F842 5.5 ns 60 mA ORDERING INFORMATION COMMERCIAL RANGE: VCC = 5 V ± 10%; Tamb = 0 °C to +70 °C Type number Package Name Description Version N74F841N, N74F842N DIP24 plastic dual in-line package; 24 leads (300 mil) SOT222-1 N74F841D, N74F842D SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Dn Data inputs 1.0/0.033 20 µA / 20 µA LE Latch Enable input 1.0/0.033 20 µA / 20 µA OE Output Enable input (active-LOW) 1.0/0.033 20 µA / 20 µA Qn Data outputs 1200/80 24 mA / 48 mA Qn Data outputs 1200/80 24 mA / 48 mA NOTE: One (1.0) FAST Unit Load is defined as: 20 µA in the HIGH state and 0.6 mA in the LOW state. 2004 Jan 23 2 Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) PIN CONFIGURATION for 74F841 OE 1 74F841/74F842 PIN CONFIGURATION for 74F842 24 VCC OE 1 24 VCC D0 2 23 Q0 D0 2 23 Q0 D1 3 22 Q1 D1 3 22 Q1 D2 4 21 Q2 D2 4 21 Q2 D3 5 20 Q3 D3 5 20 Q3 D4 6 19 Q4 D4 6 19 Q4 D5 7 18 Q5 D5 7 18 Q5 D6 8 17 Q6 D6 8 17 Q6 D7 9 16 Q7 D7 9 16 Q7 D8 10 15 Q8 D8 10 15 Q8 D9 11 14 Q9 D9 11 14 Q9 GND 12 13 LE GND 12 13 LE SF01279 SF01282 LOGIC SYMBOL for 74F841 LOGIC SYMBOL for 74F842 2 3 4 5 6 7 8 9 10 11 2 3 4 5 6 7 8 9 10 11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 23 22 21 20 19 18 17 16 15 14 13 LE 13 LE 1 OE 1 OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 23 22 21 20 19 18 17 16 15 14 VCC = Pin 24 GND = Pin 12 VCC = Pin 24 GND = Pin 12 SF01280 LOGIC SYMBOL (IEEE/IEC) for 74F841 1 13 LOGIC SYMBOL (IEEE/IEC) for 74F842 1 EN 13 C1 EN C1 23 2 3 22 3 22 4 21 4 21 5 20 5 20 6 19 6 19 7 18 7 18 8 17 8 17 9 16 9 16 10 15 10 15 11 14 11 14 2 1D SF01281 2004 Jan 23 SF01283 1D 23 SF01284 3 Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) 74F841/74F842 LOGIC DIAGRAM for 74F841 74F841 D0 D1 2 D2 3 D L LE OE D3 4 D Q L D4 5 D Q L D5 6 D Q D6 7 D L Q D7 8 D L Q L D Q D8 10 9 L D C Q L D9 11 D Q L D Q L Q 13 1 23 Q0 VCC = Pin 24 GND = Pin 12 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 Q9 SF01297 LOGIC DIAGRAM for 74F842 74F842 D0 D1 2 D2 3 D L LE OE D3 4 D Q L D4 5 D Q L D5 6 D Q D6 7 D L Q D7 8 D L Q L D Q D8 10 9 L D C Q L D9 11 D Q L D Q Q 13 1 23 Q0 VCC = Pin 24 GND = Pin 12 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 OUTPUTS INPUTS 74F841 74F842 OE LE Dn Qn Qn L H L L H L H H H L L ↓ l L H L ↓ h H L H X X Z Z L L X NC NC OPERATING MODE Transparent Latched HIGH voltage level LOW voltage level HIGH state one set-up time before the HIGH-to-LOW LE transition LOW state one set-up time before the HIGH-to-LOW LE transition HIGH-to-LOW transition Don’t care No change High impedance “off” state 2004 Jan 23 15 Q8 14 Q9 SF01298 FUNCTION TABLE for 74F841 and 74F842 H = L = h = l = ↓ = X = NC= Z = L 4 High Impedance Hold Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) 74F841/74F842 ABSOLUTE MAXIMUM RATINGS Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range. SYMBOL PARAMETER RATING UNIT VCC supply voltage –0.5 to +7.0 V VIN input voltage –0.5 to +7.0 V IIN input current –30 to +5 mA VOUT voltage applied to output in HIGH output state –0.5 to VCC V IOUT current applied to output in LOW output state Tamb operating free-air temperature range Tstg storage temperature range 84 mA 0 to +70 °C –65 to +150 °C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER UNIT MIN NOM MAX VCC supply voltage 4.5 5.0 5.5 V VIH HIGH-level input voltage 2.0 – – V VIL LOW-level input voltage – – 0.8 V IIK input clamp current – – –18 mA IOH HIGH-level output current – – –24 mA IOL LOW-level output current – – 48 mA Tamb operating free-air temperature range 0 – +70 °C 2004 Jan 23 5 Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) 74F841/74F842 DC ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range unless otherwise noted. SYMBOL LIMITS TEST CONDITIONS1 PARAMETER MIN VOH O HIGH level output voltage HIGH-level LOW level output voltage LOW-level VIK Input clamp voltage II Input current at maximum input voltage IIH 2.2 – – V ± 5%VCC 2.2 3.3 – V ± 10%VCC 2.0 – – V ± 5%VCC 2.0 – – V IOL = 32 mA ± 10%VCC – 0.38 0.55 V IOL = 48 mA ± 5%VCC – 0.38 0.55 V IOH 24 mA O = –24 VCC = MIN; VIL = MAX; VIH = MIN VOL O MAX ± 10%VCC IOH 15 mA O = –15 VCC = MIN; VIL = MAX; VIH = MIN UNIT TYP2 VCC = MIN; II = IIK – –0.73 –1.2 V VCC = 0 V; VI = 7.0 V – – 100 µA HIGH-level input current VCC = MAX; VI = 2.7 V – – 20 µA IIL LOW-level input current VCC = MAX; VI = 0.5 V – – –20 µA IOZH Off-state output current, HIGH-level voltage applied VCC = MAX; VO = 2.7 V – – 50 µA IOZL Off-state output current, LOW-level voltage applied VCC = MAX; VO = 0.5 V – – –50 µA IOS Short-circuit output current3 VCC = MAX –100 – –225 mA – 50 65 mA – 60 80 mA ICCZ – 70 92 mA ICCH – 40 60 mA – 65 90 mA – 60 90 mA ICCH 74F841 ICC Supply y current (total) 74F842 ICCL VCC = MAX ICCL VCC = MAX ICCZ NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5 V, Tamb = 25 °C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a HIGH output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter test, IOS tests should be performed last. 2004 Jan 23 6 Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) 74F841/74F842 AC ELECTRICAL CHARACTERISTICS for 74F841/74F842 LIMITS SYMBOL PARAMETER Tamb = +25 °C VCC = +5.0 V CL = 50 pF; RL = 500 Ω TEST CONDITION Tamb = 0 °C to +70 °C VCC = +5.0 V ± 10% CL = 50 pF; RL = 500 Ω UNIT MIN TYP MAX MIN MAX Waveform 1, 2 2.0 2.5 4.0 4.5 7.5 7.5 2.0 2.5 8.0 8.0 ns tPLH tPHL Propagation delay Dn to Qn tPLH tPHL Propagation delay LE to Qn Waveform 1, 2 4.5 4.0 6.5 6.0 9.5 9.0 4.0 3.5 10.0 9.5 ns tPLH tPHL Propagation delay Dn to Qn Waveform 1, 2 3.5 3.0 5.5 5.0 8.5 8.0 4.5 4.0 9.0 8.5 ns tPLH tPHL Propagation delay LE to Qn Waveform 1, 2 5.0 4.5 7.0 6.5 10.0 9.0 3.0 3.0 10.5 9.5 ns tPZH tPZL Output enable time HIGH or LOW-level OE to Qn or Qn Waveform 4 Waveform 5 2.5 4.0 4.5 6.0 8.0 9.5 2.0 3.0 8.5 10.5 ns tPHZ tPLZ Output disable time HIGH or LOW-level OE to Qn or Qn Waveform 4 Waveform 5 1.0 1.0 4.5 5.0 8.0 8.0 1.0 1.0 8.5 8.5 ns 74F841 74F842 AC SET-UP REQUIREMENTS for 74F841/74F842 LIMITS SYMBOL PARAMETER ts(H) ts(L) Set-up time, HIGH or LOW Dn to LE th(H) th(L) Hold time, HIGH or LOW Dn to LE tw(H) LE pulse width, HIGH th(H) th(L) Hold time, HIGH or LOW Dn to LE tw(H) LE pulse width, HIGH 2004 Jan 23 Tamb = +25 °C VCC = +5.0 V CL = 50 pF; RL = 500 Ω TEST CONDITION Tamb = 0 °C to +70 °C VCC = +5.0 V ± 10% CL = 50 pF; RL = 500 Ω UNIT MIN TYP MIN MAX Waveform 3 0.0 0.0 – – 1.0 1.0 – – ns Waveform 3 2.5 3.0 – – 3.0 4.0 – – ns Waveform 3 3.5 – 4.0 – ns Waveform 3 3.0 3.5 – – 3.5 4.5 – – ns Waveform 3 3.0 – 3.0 – ns 74F841 74F842 7 Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) 74F841/74F842 AC WAVEFORMS For all waveforms, VM = 1.5 V. The shaded areas indicate when the input is permitted to change for predictable output performance. Dn, LE VM VM tPLH tPHL Qn Dn, LE VM VM VM VM tPHL tPLH VM Qn VM SF01303 Waveform 1. Dn LE VM VM VM VM ts(H) th(H) ts(L) th(L) VM VM Waveform 3. Propagation delay, inverting path SF01306 Data set-up and hold times VM OEn VM tPZH Qn, Qn Waveform 2. VM tw(H) OEn SF01304 Propagation delay, non-inverting path tPHZ VOH – 0.3 V VM VM tPZL VM Qn, Qn 0V tPLZ 3.5V VM VOL + 0.3 V SF00509 SF00510 Waveform 5. 3-State Output Enable time to LOW level and Output Disable time from LOW level Waveform 4. 3-State Output Enable time to HIGH level and Output Disable time from HIGH level 2004 Jan 23 8 Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) 74F841/74F842 TEST CIRCUIT AND WAVEFORMS VCC 7.0 V VIN RL VOUT PULSE GENERATOR tw 90% NEGATIVE PULSE VM CL AMP (V) VM 10% D.U.T. RT 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V RL AMP (V) 90% 90% Test Circuit for 3-State Outputs POSITIVE PULSE VM VM 10% TEST tPLZ tPZL All other SWITCH closed closed open DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 10% tw SWITCH POSITION 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0 V 1.5 V rep. rate 1 MHz tw tTLH 500 ns 2.5 ns tTHL 2.5 ns SF00777 2004 Jan 23 9 Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) DIP24: plastic dual in-line package; 24 leads (300 mil) 2004 Jan 23 10 74F841/74F842 SOT222-1 Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) SO24: plastic small outline package; 24 leads; body width 7.5 mm 2004 Jan 23 11 74F841/74F842 SOT137-1 Philips Semiconductors Product data 10-bit bus interface latches, non-inverting/inverting (3-State) 74F841/74F842 REVISION HISTORY Rev Date Description _4 20040123 Product data (9397 750 12746). ECN 853-1208 A15379 of 22 January 2004. Replaces Product specification 74F841/842/843/845/846_3 dated 1999 Jun 23 (9397 750 06143). Modifications: • Delete all references to 74F843, 74F845, 74F846 (products discontinued). _3 19990623 Product specification (9397 750 06143). ECN 853-1208 21851 of 23 June 1999. Replaces datasheet 74F841/842/843/844/845/846 of 1999 Jan 08. Data sheet status Level Data sheet status [1] Product status [2] [3] Definitions I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 01-04 For sales offices addresses send e-mail to: [email protected]. Document order number: 2004 Jan 23 12 9397 750 12746