74HC573-Q100; 74HCT573-Q100 Octal D-type transparent latch; 3-state Rev. 2 — 16 August 2012 Product data sheet 1. General description The 74HC573-Q100; 74HCT573-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC573-Q100; 74HCT573-Q100 has octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches. When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the latches are transparent, i.e. a latch output changes state each time its corresponding D input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Input levels: For 74HC573: CMOS level For 74HCT573: TTL level Inputs and outputs on opposite sides of package allowing easy interface with microprocessors Useful as input or output port for microprocessors and microcomputers 3-state non-inverting outputs for bus-oriented applications Common 3-state output enable input Multiple package options ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 74HC573-Q100; 74HCT573-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state 3. Ordering information Table 1. Ordering information Type number 74HC573D-Q100 Package Temperature range Name Description Version 40 C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1 thin quad flat package; no leads; 20 terminals; body 2.5 4.5 0.85 mm 74HCT573D-Q100 74HC573PW-Q100 74HCT573PW-Q100 74HC573BQ-Q100 74HCT573BQ-Q100 4. Functional diagram 2 D0 Q0 19 3 D1 Q1 18 4 D2 Q2 17 5 D3 6 D4 7 D5 Q5 14 8 D6 Q6 13 9 D7 Q7 12 LATCH 1 to 8 3-STATE OUTPUTS Q3 16 Q4 15 11 LE 1 OE mna809 Fig 1. Functional diagram 74HC_HCT573_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 August 2012 © NXP B.V. 2012. All rights reserved. 2 of 19 74HC573-Q100; 74HCT573-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state D0 D1 D Q D2 D Q D3 D Q D4 D Q D5 D Q D6 D Q D7 D Q D Q LATCH 1 LATCH 2 LATCH 3 LATCH 4 LATCH 5 LATCH 6 LATCH 7 LATCH 8 LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aae075 Fig 2. Logic diagram 11 1 1 2 3 4 5 6 7 8 9 2 OE D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 19 Fig 3. Logic symbol 74HC_HCT573_Q100 Product data sheet 19 1D 3 18 4 17 16 5 16 15 6 15 14 7 14 8 13 9 12 18 17 13 12 LE 11 C1 EN1 mna807 mna808 Fig 4. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 August 2012 © NXP B.V. 2012. All rights reserved. 3 of 19 74HC573-Q100; 74HCT573-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state 5. Pinning information 5.1 Pinning 1 OE terminal 1 index area 74HC573-Q100 74HCT573-Q100 20 VCC 74HC573-Q100 74HCT573-Q100 D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 OE 1 20 VCC D0 2 19 Q0 D1 3 18 Q1 D3 5 16 Q3 6 15 Q4 7 4 17 Q2 D3 5 16 Q3 D5 D4 6 15 Q4 D5 7 14 Q5 D6 8 13 Q6 D7 9 12 Q7 GND 10 11 LE 8 D7 9 13 Q6 12 Q7 GND 10 D6 14 Q5 GND(1) LE 11 D2 D4 aaa-003604 Transparent top view aaa-003603 (1) The die substrate is attached to this pad using conductive die attach material. It cannot be used as supply pin or input Fig 5. Pin configuration SO20 and TSSOP20 Fig 6. Pin configuration DHVQFN20 5.2 Pin description Table 2. Pin description Symbol Pin Description OE 1 3-state output enable input (active LOW) D[0:7] 2, 3, 4, 5, 6, 7, 8, 9 data input GND 10 ground (0 V) LE 11 latch enable input (active HIGH) Q[0:7] 19, 18, 17, 16, 15, 14, 13, 12 3-state latch output VCC 20 74HC_HCT573_Q100 Product data sheet supply voltage All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 August 2012 © NXP B.V. 2012. All rights reserved. 4 of 19 74HC573-Q100; 74HCT573-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state 6. Functional description Table 3. Function table[1] Operating mode OE LE Dn Internal latches Enable and read register (transparent mode) L H L L H H H Latch and read register L L l L L h H H l L Z h H Z Latch register and disable outputs [1] Control H Input L Output L Qn H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA IO output current VO = 0.5 V to (VCC + 0.5 V) - 35 mA ICC supply current - +70 mA IGND ground current - 70 mA Tstg storage temperature Ptot total power dissipation [1] [2] Conditions VI < 0.5 V or VI > VCC + 0.5 V Min Max Unit 0.5 +7 V - 20 mA 65 +150 C DIP20 package [1] - 750 mW SO20, SSOP20, TSSOP20 and DHVQFN20 packages [2] - 500 mW For DIP20 package: Ptot derates linearly with 12 mW/K above 70 C. For SO20: Ptot derates linearly with 8 mW/K above 70 C. For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN20 package: Ptot derates linearly with 4.5 mW/K above 60 C. 74HC_HCT573_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 August 2012 © NXP B.V. 2012. All rights reserved. 5 of 19 74HC573-Q100; 74HCT573-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC573-Q100 Min Typ 74HCT573-Q100 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min Typ VCC = 2.0 V 1.5 VCC = 4.5 V 3.15 VCC = 6.0 V 4.2 VCC = 2.0 V - VCC = 4.5 V - VCC = 6.0 V 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max 1.2 - 1.5 - 1.5 - V 2.4 - 3.15 - 3.15 - V 3.2 - 4.2 - 4.2 - V 0.8 0.5 - 0.5 - 0.5 V 2.1 1.35 - 1.35 - 1.35 V - 2.8 1.8 - 1.8 - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 6.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 7.8 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 6.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 7.8 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V 74HC573-Q100 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1.0 - 1.0 A IOZ OFF-state output current VI = VIH or VIL; VO = VCC or GND; VCC = 6.0 V - - 0.5 - 5.0 - 10.0 A 74HC_HCT573_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 August 2012 © NXP B.V. 2012. All rights reserved. 6 of 19 74HC573-Q100; 74HCT573-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min ICC supply current CI input capacitance VI = VCC or GND; IO = 0 A; VCC = 6.0 V 40 C to +85 C 40 C to +125 C Unit Typ Max Min Max Min Max - - 8.0 - 80 - 160 - 3.5 - A pF 74HCT573-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 6 mA 3.98 4.32 - 3.84 - 3.7 - V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A - 0 0.1 - 0.1 - 0.1 V IO = 6.0 mA - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1.0 - 1.0 A IOZ OFF-state output current VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A - - 0.5 - 5.0 - 10 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 - 80 - 160 A ICC additional supply current VI = VCC 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A per input pin; Dn inputs - 35 126 - 158 - 172 A per input pin; LE input - 65 234 - 293 - 319 A per input pin; OE input - 125 450 - 563 - 613 - 3.5 - CI input capacitance 74HC_HCT573_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 August 2012 A pF © NXP B.V. 2012. All rights reserved. 7 of 19 74HC573-Q100; 74HCT573-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V - 47 150 - 190 - 225 ns VCC = 4.5 V - 17 30 - 38 - 45 ns VCC = 5 V; CL = 15 pF - 14 - - - - - ns VCC = 6.0 V - 14 26 - 33 - 38 ns - 50 150 - 190 - 225 ns For type 74HC573-Q100 tpd tpd propagation delay propagation delay Dn to Qn; see Figure 7 LE to Qn; see Figure 8 [1] [1] VCC = 2.0 V VCC = 4.5 V - 18 30 - 38 - 45 ns VCC = 5 V; CL = 15 pF - 15 - - - - - ns - 14 26 - 33 - 38 ns VCC = 2.0 V - 44 140 - 175 - 210 ns VCC = 4.5 V - 16 28 - 35 - 42 ns - 13 24 - 30 - 36 ns VCC = 2.0 V - 55 150 - 190 - 225 ns VCC = 4.5 V - 20 30 - 38 - 45 ns - 16 26 - 33 - 38 ns VCC = 6.0 V ten enable time OE to Qn; see Figure 9 [2] VCC = 6.0 V tdis disable time OE to Qn; see Figure 9 [3] VCC = 6.0 V tt tW tsu th transition time pulse width set-up time hold time [4] Qn; see Figure 7 VCC = 2.0 V - 14 60 - 75 - 90 ns VCC = 4.5 V - 5 12 - 15 - 18 ns VCC = 6.0 V - 4 10 - 13 - 15 ns LE HIGH; see Figure 8 VCC = 2.0 V 80 14 - 100 - 120 - ns VCC = 4.5 V 16 5 - 20 - 24 - ns VCC = 6.0 V 14 4 - 17 - 20 - ns Dn to LE; see Figure 10 VCC = 2.0 V 50 11 - 65 - 75 - ns VCC = 4.5 V 10 4 - 13 - 15 - ns VCC = 6.0 V 9 3 - 11 - 13 - ns VCC = 2.0 V 5 3 - 5 - 5 - ns VCC = 4.5 V 5 1 - 5 - 5 - ns 5 1 - 5 - 5 - ns - 26 - - - - - pF Dn to LE; see Figure 10 VCC = 6.0 V CPD power dissipation capacitance 74HC_HCT573_Q100 Product data sheet CL = 50 pF; f = 1 MHz; VI = GND to VCC [5] All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 August 2012 © NXP B.V. 2012. All rights reserved. 8 of 19 74HC573-Q100; 74HCT573-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - 20 35 - 44 - 53 ns - 17 - - - - - ns For type 74HCT573-Q100 tpd propagation delay Dn to Qn; see Figure 7 [1] VCC = 4.5 V VCC = 5 V; CL = 15 pF tpd ten propagation delay enable time LE to Qn; see Figure 8 [1] VCC = 4.5 V - 18 35 - 44 - 53 ns VCC = 5 V; CL = 15 pF - 15 - - - - - ns - 17 30 - 38 - 45 ns - 18 30 - 38 - 45 ns - 5 12 - 15 - 18 ns 16 5 - 20 - 24 - ns 13 7 - 16 - 20 - ns 9 4 - 11 - 15 - ns - 26 - - - - - pF OE to Qn; see Figure 9 [2] VCC = 4.5 V tdis disable time OE to Qn; see Figure 9 [3] VCC = 4.5 V tt tW [4] transition time Qn; see Figure 7 pulse width LE HIGH; see Figure 8 VCC = 4.5 V VCC = 4.5 V tsu set-up time Dn to LE; see Figure 10 VCC = 4.5 V th hold time Dn to LE; see Figure 10 VCC = 4.5 V CPD [1] power dissipation capacitance CL = 50 pF; f = 1 MHz; VI = GND to VCC [5] tpd is the same as tPLH and tPHL. [2] ten is the same as tPZH and tPZL. [3] tdis is the same as tPLZ and tPHZ. [4] tt is the same as tTHL and tTLH. [5] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 74HC_HCT573_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 August 2012 © NXP B.V. 2012. All rights reserved. 9 of 19 74HC573-Q100; 74HCT573-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state 11. Waveforms VM Dn input t PLH t PHL 90 % VM Qn output 10 % t TLH t THL 001aae082 Measurement points are given in Table 8. Fig 7. Propagation delay data input (Dn) to output (Qn) and output transition time VM LE input tW t PHL t PLH 90 % VM Qn output 10 % t THL t TLH 001aae083 Measurement points are given in Table 8. Fig 8. Pulse width latch enable input (LE), propagation delay latch enable input (LE) to output (Qn) and output transition time 74HC_HCT573_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 August 2012 © NXP B.V. 2012. All rights reserved. 10 of 19 74HC573-Q100; 74HCT573-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state VI OE input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM 10% VOL tPHZ tPZH VOH 90% output HIGH-to-OFF OFF-to-HIGH GND VM outputs enabled outputs disabled outputs enabled 001aae307 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Enable and disable times VM LE input t su t su th th VM Dn input 001aae084 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 10. Set-up and hold times for data input (Dn) to latch input (LE) Table 8. Measurement points Type Input Output VM VM 74HC573-Q100 0.5VCC 0.5VCC 74HCT573-Q100 1.3 V 1.3 V 74HC_HCT573_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 August 2012 © NXP B.V. 2012. All rights reserved. 11 of 19 74HC573-Q100; 74HCT573-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT CL RT 001aad983 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 11. Test circuit for measuring switching times Table 9. Test data Type Input VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74HC573-Q100 VCC 6 ns 15 pF, 50 pF 1 k open GND VCC 74HCT573-Q100 3V 6 ns 15 pF, 50 pF 1 k open GND VCC 74HC_HCT573_Q100 Product data sheet Load S1 position All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 August 2012 © NXP B.V. 2012. All rights reserved. 12 of 19 74HC573-Q100; 74HCT573-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT163-1 (SO20) 74HC_HCT573_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 August 2012 © NXP B.V. 2012. All rights reserved. 13 of 19 74HC573-Q100; 74HCT573-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 13. Package outline SOT360-1 (TSSOP20) 74HC_HCT573_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 August 2012 © NXP B.V. 2012. All rights reserved. 14 of 19 74HC573-Q100; 74HCT573-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b 1 0.05 0.00 0.30 0.18 mm c D (1) Dh E (1) Eh 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT764-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 14. Package outline SOT764-1 (DHVQFN20) 74HC_HCT573_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 August 2012 © NXP B.V. 2012. All rights reserved. 15 of 19 74HC573-Q100; 74HCT573-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic MIL Military 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT573_Q100 v.2 20120816 Product data sheet - 74HC_HCT573_Q100 v.1 Modifications: 74HC_HCT573_Q100 v.1 74HC_HCT573_Q100 Product data sheet • Alternative descriptive title corrected (errata). 20120802 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 August 2012 - © NXP B.V. 2012. All rights reserved. 16 of 19 74HC573-Q100; 74HCT573-Q100 NXP Semiconductors Octal D-type transparent latch; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74HC_HCT573_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 August 2012 © NXP B.V. 2012. All rights reserved. 17 of 19 NXP Semiconductors 74HC573-Q100; 74HCT573-Q100 Octal D-type transparent latch; 3-state No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74HC_HCT573_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 16 August 2012 © NXP B.V. 2012. All rights reserved. 18 of 19 NXP Semiconductors 74HC573-Q100; 74HCT573-Q100 Octal D-type transparent latch; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 16 August 2012 Document identifier: 74HC_HCT573_Q100