AN95599 Hardware Design Guidelines for EZ-PD CCG2.pdf

AN95599
Hardware Design Guidelines for EZ-PD™ CCG2
Author: Rahul Raj Sharma
Associated Project: No
Associated Part Family: CYPD210x
Software Version: NA
Related Application Notes: AN95615
To get the latest version of this application note, or the associated project file, please visit
http://www.cypress.com/go/AN95599.
AN95599 provides hardware design and PCB layout guidelines for EZ-PD™ CCG2. These guidelines will help to ensure
the best performance with respect to signal integrity and full electrical compliance with the USB Power Delivery and
Type-C specification.
Contents
Introduction
Introduction .......................................................................1
Introduction to USB Type-C ..............................................2
Signals in USB Type-C .................................................2
Basic Terminology .............................................................3
USB Type-C Connection Orientation Detection............3
Schematic Design Requirements ......................................4
Power System ...................................................................6
VCONN Selection .........................................................7
Connecting an Authentication Chip ...................................8
Routing of USB Data Lines...........................................8
Signal Via Routing ...................................................... 10
Summary ......................................................................... 11
Appendix A: BOM and Schematics ................................. 12
Reference BOM for CCG2-based EMCA Paddle Card
................................................................................... 12
Paddle Card Reference Schematics for Single/Dual
Chip CCG2 (CSP) EMCA – CYPD2103-20FNXIT ...... 13
Paddle Card Reference Schematics for Single/Dual
Chip CCG2 (DFN) EMCA – CYPD2103-14LHXIT ...... 15
Document History ............................................................ 17
Worldwide Sales and Design Support ............................. 18
EZ-PD CCG2 is Cypress’s second generation of USB
Type-C electronically marked cable assembly (EMCA)
controllers compliant with the USB Power Delivery (PD)
specification 2.0. CCG2 provides a complete USB Type-C
and USB PD solution for passive cables, active cables,
and powered accessories. It combines an industry®
®
standard, high-performance 32-bit ARM Cortex -M0
CPU, serial communication blocks (SCBs) to support
2
standard serial communication protocols such as I C, SPI,
UART, and an integrated USB Type-C transceiver
1
including the termination resistors RD, RP, and RA.
In Type-C EMCA designs, active components including
CCG2 are placed on a paddle card (Figure 2)  a card at
each end of the cable, which holds the USB Type-C plugs
and connects to the cable harness. The hardware
guidelines in this application note apply to the design of
the paddle card. Table 1 lists the CCG2 product options
available for different applications. For more details on
these applications, see AN95615. For more details on
USB Type-C and USB PD, see www.usb.org.
Table 1. EZ-PD CCG2 Product Options
Features
CYPD2103
CYPD2104
CYPD2105
Application
Passive Cable
Accessory2
Active Cable3
Package
20-ball
WLCSP,
20-ball WLCSP 20-ball WLCSP
14-pin DFN
1. See the Type-C specification for more details on termination resistors.
2. An upstream facing port (UFP) with the form factor of a cable or dongle.
3. Electronically marked cable assembly with a re-driver to condition USB data signals.
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Hardware Design Guidelines for EZ-PD™ CCG2
Introduction to USB Type-C
Major advantages of the USB Type-C specification are as
follows:
The USB Type-C Cable and Connector specification
define a new 2.4-mm thin receptacle and plug. These
plugs are designed with user convenience in mind and
they can be plugged in either orientation. The USB Type-C
cable provides up to 100 W of power. The USB Type-C
specification also allows the cables to carry high-definition
video in parallel with USB 3.0 communication.



The USB Type-C receptacle, plug, and cable provide a
smaller, thinner, and more robust alternative to the
existing USB 3.1 interconnects (standard and micro USB
cables and connectors). The target applications range
from ultra-thin notebook PCs to smart phones, where
existing standard-A and micro-AB receptacles are deemed
too large, too difficult to use, or inadequately robust.
Slim industrial design with a 2.4-mm plug height
Reversible plug orientation and cable direction
Transport of both USB signals and
DisplayPort signals on the same connector
PCIe
or

Easy implementation of low-cost power delivery up to
100 W
USB Type-C provides an all-in-one solution for today’s
applications supporting high bandwidth and power
requirements as illustrated in Figure 1.
Figure 1. USB Type-C Combines It All
Signals in USB Type-C
A full-featured USB Type-C cable contains the following
signals:

VCONN: Provides 5 V to power the active electronics
inside the Type-C cable assembly. VCONN is sourced
by the downstream facing port (DFP) or host initially
and can be sourced by the upstream facing port
(UFP) or device after a power-role swap.

VBUS: Power that can go as high as 20 V carrying 5 A
depending on the power negotiation between the host
and device as defined in the USB PD specification.

CC: Configuration channel dedicated to USB-PD
communications and shared between the USB host,
cable, and device.
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
Dn/Dp: Standard USB 2.0 lines used for USB 2.0
communication between a host and a device.

RX/TX lines: Two pairs of RX and TX differential pairs
in a full-featured USB Type-C cable assembly. At any
time, only one set of RX and TX pairs is used for USB
3.0 communication, depending on the orientation in
which the cable assembly is plugged in. See the
section, USB Type-C Connection Orientation
Detection.

SBU1/SBU2: Sideband use signal lines used in
alternate modes to transmit auxiliary signals such as
audio. For more details on these signals, see the USB
Type-C specification.
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Hardware Design Guidelines for EZ-PD™ CCG2
Cable
Housing
Cable
Housing
Type-C
Plug
Type-C
Plug
Figure 2. USB Type-C Connector Housing
Figure 3. USB Type-C Connection/Orientation Detection
Basic Terminology
1
SOP*: SOP stands for Start of Packet; A PD starts with an
SOP* sequence. See the USB PD specification.
DFP: Downstream facing port (DFP) is a USB Type-C port
on a host or a hub to which devices are connected.
UFP: Upstream facing port (UFP) is a USB Type-C port on
a device or a hub that connects to a host or a hub DFP.
USB Type-C Connection Orientation Detection
A DFP exposes Rp terminations on its CC pins (CC1 and
CC2), and a UFP exposes Rd terminations on its CC pins,
as Figure 3 shows. The cables will expose Ra terminations
on the VCONN pin. The purpose of Rp and Rd terminations
on the CC pins is to identify the DFP to the UFP
connection and the CC pin that will be used for
communication. When the cable is connected, the DFP
monitors both CC pins for a voltage lower than its unterminated voltage.
By detecting the CC pin (CC1 or CC2) at the Type-C
receptacle that is terminated by the Rd at the UFP, the
DFP determines the SuperSpeed (SS) USB signals (from
the two pairs) that are to be used for the connection and
accordingly controls the functional switch to route the
appropriate SuperSpeed USB signal pairs.
Similarly, the UFP detects the CC pin terminated by the
DFP and accordingly controls the functional switch to
route the appropriate SuperSpeed USB signal pairs. After
a connection is established, the DFP will reassign CC1 or
CC2 to provide cable power over the VCONN pin of the
plug. See the Type-C specification for more details on the
Type-C connection and orientation-detection mechanism.
1
www.cypress.com
Illustration source: USB Type-C specification
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Hardware Design Guidelines for EZ-PD™ CCG2
After the cable is enumerated, the host may shut down the
VCONN supply. One of the key and unique requirements
for this application is to power the chip from two separate
VCONN pins, as shown in Figure 4. This solution needs a
dedicated wire running between the plugs. The GPIO pin
(ball D3 of the wafer level chip scale package (WLCSP)
or pin 13 of the DFN package) of the CCG2 device must
be left floating for this application.
Schematic Design Requirements
This section explains the schematic design requirements
for CCG2-based EMCAs. Three application scenarios
serve as a reference.
EMCA Solution With One CCG2 Chip per
Cable
This EMCA solution contains a CCG2 chip in only one of
its plugs. It requires running the VCONN wire through the
cable (not through the chip), so that the chip (residing at
one end of the cable) can be powered by either VCONN1
or VCONN2, regardless of which plug is connected to the
host (DFP).
Figure 4. Power System Recommendation for a Single CCG2-based EMCA Cable Solution
Type-C
Plug
Type-C
Plug
VBUS
VCONN 2
VCONN 1
1uF
E4
E3
E1
VDDD
VDDIO
VCONN1
VCONN2
0.1uF
GPIO
C3
A1
VDDIO
4.7 k
GPIO
GPIO
GPIO
VCCD
1uF
CYPD2103-20FNXIT
B1
GPIO
CC2
XRES
0.1uF
C2
D2
B2
A4
CC1 B4
D4 VSS
C1 VSS
RD1
I2C_0 I2C_0
_SCL _SDA
A2
A3
C4
D3
B3
SWD_ SWD_
IO
CLK
D1
E2
CC
SuperSpeed and HighSpeed Lines
GND
Note Figure 4 is for representative purpose and is based on the WLCSP package. For the DFN reference schematic, see the
Appendix.
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Hardware Design Guidelines for EZ-PD™ CCG2
E M C A S o l u t i o n W i t h T w o C C G 2 C h i p s p e r C a b l e ( o n e C C G 2 a c t i ve a t a T i m e )
This EMCA solution contains two CCG2 devices, one in each plug, with only one powered at a time. In this solution, the
VCONN signal does not run across the cable, but it breaks at the CCG2 device in each plug. Also, only the CCG2 device that
is nearer to the DFP supplying VCONN is powered. After the cable is enumerated, the host may shut down the VCONN
supply. This cable does not need the VCONN wire to run across from one end to the other as Figure 5 shows, saving the cost
of copper wire.
Figure 5. Power System Recommendation for Dual CCG2-based EMCA Cable Solution
Type-C
Plug
Type-C
Plug
VBUS
VCONN2
VCONN1
1uF
1uF
E4
E3
E1
VDDD
VDDIO
VCONN1
VCONN2
0.1uF
GPIO
C3
A1
VDDIO
4.7 k
GPIO
GPIO
VCCD
GPIO
1uF
CYPD2103-20FNXIT
B1
GPIO
CC2
XRES
D4 VSS
C1 VSS
I2C_0 I2C_0
_SCL _SDA
A2
A3
E4
C4
E1
VDDIO
VCONN1
GPIO
D3
C3
C2
A1
D2
VDDIO
B2
GPIO
VCCD
1uF
4.7 k
A4
GPIO
GPIO
CYPD2103-20FNXIT
B1
XRES
D4 VSS
B3
C1 VSS
I2C_0 I2C_0
_SCL _SDA
A2
A3
SWD_ SWD_
IO
CLK
D1
E2
GPIO
CC2
CC1 B4
RD1
E3
VDDD
VCONN2
C4
D3
0.1uF
C2
D2
B2
A4
CC1 B4
RD1
B3
SWD_ SWD_
IO
CLK
D1
E2
CC
SuperSpeed and HighSpeed Lines
GND
Note Figure 5 is for representative purpose and is based on the WLCSP package. For the DFN reference schematic, see the
Appendix.
A c t i ve E M C A S o l u t i o n W i t h T w o C C G 2 C h i p s p e r C a b l e ( B o t h C C G 2 s Ac t i ve )
This EMCA solution contains two CCG2 devices, one in each plug, with both CCG2s powered at a time. The typical use case
of this solution is in active cables. The main function of an active EMCA is to provide signal conditioning by adding a re-driver
on the data path. Active cables that require configuration or signal conditioning are referred to as “managed active cables.”
When a managed active cable requires independent management or signal conditioning at each end of the cable, separate
USB PD controllers responding to USB PD structured vendor-defined messages (VDMs) must be located in each plug. For
more details on VDMs, see the USB PD specification.
This active cable solution contains two CCG2 chips, one on each plug. VCONN is wired across the cable but is not shorted
between the two connectors. In this solution, the wiring is done such that the cable is reversible as shown in Figure 6. The
GPIO pins (ball D3 of the WLCSP package or pin 13 of the DFN package) of both CCG2 devices must be pulled down to
ground in this application.
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Document No. 001-95599 Rev. **
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Hardware Design Guidelines for EZ-PD™ CCG2
Figure 6. Power System Recommendation (Both Chips Powered)
Type-C
Plug
Type-C
Plug
VBUS
VCONN2
VCONN1
0.1uF
1uF
E4
E3
E1
VDDD
VDDIO
VCONN1
VCONN2
0.1uF
GPIO
C3
A1
VDDIO
GPIO
GPIO
VCCD
1uF
GPIO
CYPD2105-20FNXIT
4.7 k
B1
C1
`
1uF
GPIO
CC2
XRES
C1 VSS
RD1
E1
VDDD
VDDIO
VCONN2
VCONN1
GPIO
D3
C3
C2
A1
VDDIO
D2
GPIO
GPIO
VCCD
GPIO
1uF
B2
GPIO
CYPD2105-20FNXIT
4.7 k
A4
B1
CC2
XRES
C1 VSS
B3
I2C_0 I2C_0
_SCL _SDA
A2
A3
SWD_ SWD_
IO
CLK
D1
E2
E4
D3
C2
D2
B2
A4
CC1 B4
D4 VSUB
CC1 B4
D4 VSUB
I2C_0 I2C_0
_SCL _SDA
A2
A3
C4
C4
E3
RD1
B3
SWD_ SWD_
IO
CLK
D1
E2
From CCG2 GPIO
From CCG2 GPIO
CC
SuperSpeed and Hi-Speed Lines
USB-Redriver
USB-Redriver
GND
Note Figure 6 is for representative purpose and is based on the WLCSP package.
Power System
CCG2 can operate from one of the two power rails named
VCONN1 and VCONN2. Figure 4 and Figure 5 show the
recommended power supply-decoupling scheme for
single- and dual-CCG2-based EMCA cables.

Each CCG2 chip needs a minimum of five passive
components:


Reset pull-up: This pull-up is required to ensure that
the XRES line of the CCG2 chip is always pulled to
the VDDIO rail so that the chip is not held in reset.

Decoupling capacitor for VCONN rails: This 0.1-uF
capacitor should be placed on the VCONN line to
meet the ESD performance of the CCG2 chip (± 8-kV
contact discharge and ±15-kV air gap discharge
based on IEC61000-4-2 Level 4C).

Decoupling capacitor for VDDD rail: CCG2 regulators
and all peripherals are powered from the VDDD rails
internally. To ensure reliable performance of the chip,
a clean DC voltage is required at this pin. A 1 uF
decoupling capacitor is required to reduce ripples in
this rail.
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Decoupling capacitor for VCCD rail: VCCD is the
1.8-V internal regulator output. A 1-uF decoupling
capacitor must be added to stabilize the supply and
remove ripples from the rail.
Decoupling capacitor for VDDIO rail: The internal
GPIO buffers of CCG2 are powered from this rail. If
the rail is powered from a dedicated supply, then it
needs a 1-uF decoupling capacitor to reduce ripples.
This rail can shorted to VDDD in cable applications as
shown in Figure 4, Figure 5, and Figure 6.
Note In addition, four capacitors are needed on the VBUS
pins of the Type-C connector according to the Type-C
specification. A 10-nF bypass capacitor (minimum voltage
rating of 30 V) is required for the VBUS pin in the fullfeatured cable at each end of the cable. The bypass
capacitors should be placed as close as possible to the
VBUS pins of the Type-C connector. See the Type-C
Specification for more details.
Table 2 lists the recommended values of these passive
components.
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Hardware Design Guidelines for EZ-PD™ CCG2
Table 2. Recommended Values of Passive Components
Recommended
Value
Passive Component
XRES pull-up
4.7 kΩ
VCONN decoupling capacitor
0.1 µF per used rail
VDDD decoupling capacitor
1 µF
VCCD decoupling capacitor
1 µF
VDDIO decoupling capacitor (if powered from separate rail)
1 µF
VBUS bypass capacitor
10 nF per VBUS pin
For various CCG2 applications, the minimum number of components required is listed in Table 3.
Table 3. BOM for CCG2 in Various Applications
Application
Figure
Reference
Minimum
Components
Description
EMCA Solution with One CCG2 per Cable
Figure 4
5
Four decoupling capacitors, one XRES pullup resistor
EMCA Solution with Two CCG2 per Cable (Only One
CCG2 Powered)
Figure 5
8
Three decoupling capacitors per chip, one
XRES pull-up resistor per chip
Active EMCA Solution with Two CCG2 per Cable (Both
Powered)
Figure 6
8
Three decoupling capacitors per chip, one
XRES pull-up resistor per chip
VCONN Selection
CCG2 has two VCONNs (VCONN_1 and VCONN_2) with internal diode to power the VDDD pad of the chip, which in turn
powers the rest of the chip (Figure 7).
Figure 7. CCG2 Power and Bypass Scheme
4.0V to 5.5V VCONN1
0.1uF
VCONN2
RA
RA
VDDD
1uF
Core Regulator
VCCD
VDDIO
1uF
GPIO
Core
CC
Tx/Rx
VSS
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Hardware Design Guidelines for EZ-PD™ CCG2
Figure 9. Placement of Capacitors
Connecting an Authentication Chip
For applications that require tamper-proof authentication,
CCG2 can be connected to an external authentication
chip. This additional chip will ensure that only the specific
vendor-provided cable works with the vendor’s host and
the host can terminate negotiations immediately if
authentication fails. The authentication chip can be
connected as shown in Figure 8, where U2 represents the
2
authentication device with an I C slave interface.
Figure 8. Authentication Chip Connection
Placement of Power and Ground Planes
Place the power plane close to the ground plane for good
planar capacitance. Planar capacitance between the
planes acts as a distributed decoupling capacitor for highfrequency noise filtering, reducing electromagnetic
radiation.
Routing of USB Data Lines
PCB Layout Guidelines
This section explains PCB design guidelines for routing
power signals and USB signals. It provides
recommendations for placing components on the board.
See the Power System section for recommendations on
component values.
Power Domain
CCG2 devices are powered from the VCONN supply from
the DFP. Consider the following while designing the power
system network:


A USB Type-C cable consists of one or two PCBs, known
as “paddle cards,” depending on the cable design. All fullfeatured Type-C cables must be electronically marked
according to the Type-C specification and thus will be
using these paddle cards.
Although the USB data lines are not directly connected to
CCG2, you must pay careful attention to how they are
treated in a paddle card design. The USB data lines are
most critical to achieve good signal quality and reduce
emission. Follow the guidelines below while designing a
paddle card:

Use a high-performance substrate material for paddle
cards.

Keep USB SuperSpeed traces as short as possible.
Ensure that these traces have a nominal differential
characteristic impedance of 90 Ω.

Match the differential SS pair trace lengths within
0.12 mm (5 mils).

Match the high-speed (Dp and Dn) signal trace
lengths within 1.25 mm (50 mils).

Ensure that the differential pairs have a minimum pairto-pair separation of 0.5 mm.

Adjust the high-speed signal trace lengths near the
USB receptacle, if necessary.

Make adjustments for SS Rx signal trace lengths near
the USB receptacle. Make adjustments for SS Tx
signal trace lengths near the device if necessary.
Placement of bulk and decoupling capacitors
Placement of power and ground planes
Placement of Bulk and Decoupling
Capacitors
Place decoupling capacitors for high-frequency noise
filtering close to the VCONN, VDDD, and VCCD pins as
shown in Figure 9. Place the bulk capacitor, which acts as
a local power supply to the power pin, close to the VDDD
pin of CCG2.
Make the power trace width the same as the power pad
width. To connect the power pins to the power plane, keep
vias very close to the power pads. This helps to minimize
stray inductance and IR drop on the line.
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Document No. 001-95599 Rev. **
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Hardware Design Guidelines for EZ-PD™ CCG2

Figure 11. All VBUS Pins are Grouped Together
Select a grounded coplanar waveguide (CPWG)
system as a transmission line method as shown in
Figure 10.
Figure 10. CPWG Example


Minimize the use of vias.
Group the VBUS pins together (all VBUS pins are
brought out to the same plane using vias) as shown in
Figure 11.

Similarly, group the GND pins together (all GND pins
are brought out to the same plane using vias).

Additional ground pad is needed to solder the shield
for a coax cable.
T yp i c a l 3 2 - m i l , S i x - L a ye r P C B E x a m p l e
Figure 12 shows the recommended stack up for a
standard 32-mil-(0.8 mm) thick PCB. When this stack up is
used with two parallel traces, each with a width (W) of ‘x’
mils and a spacing (S) of ‘y’ mils, the calculated differential
impedance is 90 Ω.
Figure 12. PCB Stack-Up
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Hardware Design Guidelines for EZ-PD™ CCG2
Impedance Matching
Maintain a constant trace width and spacing in differential
pairs to avoid impedance mismatches, as Figure 13
shows.
Figure 15. Solid Ground Plane Under SS Signal
SS trace
Signal layer
Figure 13. Differential Pair Placement
Ground layer
Whenever two pairs of USB traces cross each other in
different layers, a ground layer should run all the way
between the two USB signal layers, as Figure 16 shows.
Figure 16. Ground Insertion

‘g’ is the minimum gap between the trace and other
planes (8 mils)


‘W’ is the width of the signal trace
‘S’ is the gap between the differential pair signals
All SS signal lines should be routed over an adjacent
ground plane layer to provide a good return current path.
Figure 14. Differential Pair Impedance Matching
Techniques
Not recommended
Not recommended
Signal Via Routing
Recommended
Splitting the ground plane underneath the SS signals
introduces an impedance mismatch, thereby increasing
the loop inductance and electrical emissions. Figure 15
shows a recommended solid ground plane under the SS
signal.
This section discusses the general recommendations for
routing the SS signals. In applications such as paddle
cards for Type-C cables, it may not be possible to follow
all these guidelines due to size constraint.
SS signals should be routed in a single layer. Vias
introduce discontinuities in the signal line and affect the
SS signal quality.
If you need to route the SS signal to another layer,
maintain continuous grounding to ensure uniform
impedance throughout. To do so, place ground vias next
to signal vias, as shown in Figure 17. The distance
between the signal and ground vias should be at least
40 mils.
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Document No. 001-95599 Rev. **
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Hardware Design Guidelines for EZ-PD™ CCG2
Figure 17. Ground Vias
Differential impedance
should be maintained
at 90 ohms in these
sections
These four sections should
be routed as a single ended
trace. The impedance of
each individual trace should
be maintained at 45 ohms.
Figure 19. USB Signal Bends
Ground vias
Distance between each
via should be about 40
mils (center to center)
SS signal vias
Not recommended
Voids for vias on the SS signal traces should be common
for the differential pair. A common void, shown in Figure
18, helps to match the impedance better than separate
vias.
Figure 18. Void Vias Placement for SS Traces
Void in plane
for vias
Recommended
Distance between each
via pair should be about
40 mils.
On USB signal lines, use as few bends as possible. Do
not use a 90-degree bend. Use 45-degree or rounded
(curved) bends if necessary, as illustrated in Figure 19.
Recommended
Summary
USB PD operation demands careful hardware design. By
following the guidelines in this application note, your
CCG2-based cable design has a good chance of first-pass
success.
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Document No. 001-95599 Rev. **
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Hardware Design Guidelines for EZ-PD™ CCG2
Appendix A: BOM and Schematics
Reference BOM for CCG2-based EMCA Paddle Card
Table 4. Reference BOM for CCG2-based Paddle Card
Item
Qty per Paddle
Card
1
1
2
Reference Designator
Description
R1
Resistance 4.7 kΩ
1 (2*)
C3*, C4
Capacitor 0.1 µF 16 V
3
2
C1, C2
Capacitor 1 µF 16 V
4
1
U1
CCG2 Controller IC
5
1
J1
USB Type-C Plug-Connector
6
4
C5, C6, C7, C8
Capacitor 10 nF 35V
* Applicable only to a single-chip CCG2 EMCA solution.
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Document No. 001-95599 Rev. **
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Hardware Design Guidelines for EZ-PD™ CCG2
Paddle Card Reference Schematics for Single/Dual Chip CCG2 (CSP) EMCA – CYPD2103-20FNXIT
Figure 20. WLCSP-based Reference Schematics (Type-C connector portion)
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Hardware Design Guidelines for EZ-PD™ CCG2
Figure 21. WLCSP-based Reference Schematics (CCG2 controller portion)
Note Connection to VCONN_FAR and capacitor C3 is required only for a single-chip solution. For a dual-chip solution leave
this pin open.
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Document No. 001-95599 Rev. **
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Hardware Design Guidelines for EZ-PD™ CCG2
Paddle Card Reference Schematics for Single/Dual Chip CCG2 (DFN) EMCA – CYPD2103-14LHXIT
Figure 22. DFN-based Reference Schematics (Type-C connector portion)
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Hardware Design Guidelines for EZ-PD™ CCG2
Figure 23. DFN-based Reference Schematics (CCG2 controller portion)
Note Connection to VCONN_FAR and capacitor C3 is required only for a single-chip solution. For a dual-chip solution leave
this pin open.
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Document No. 001-95599 Rev. **
16
Hardware Design Guidelines for EZ-PD™ CCG2
Document History
Document Title: AN95599 - Hardware Design Guidelines for EZ-PD™ CCG2
Document Number: 001-95599
Revision
**
ECN
4666815
www.cypress.com
Orig. of
Change
RRSH
Submission
Date
04/03/2015
Description of Change
New Application Note
Document No. 001-95599 Rev. **
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Hardware Design Guidelines for EZ-PD™ CCG2
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© Cypress Semiconductor Corporation, 2015. The information contained herein is subject to change without notice. Cypress Semiconductor
Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any
license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or
safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The
inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies
Cypress against all charges.
This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide
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Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the
right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or
use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a
malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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Document No. 001-95599 Rev. **
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