SCAN921821 Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1 (JTAG), and At-Speed BIST General Description Features The SCAN921821 is a dual channel 18-bit serializer featuring signal conditioning, boundary SCAN, and at-speed BIST. Each serializer block transforms an 18-bit parallel LVCMOS/ LVTTL data bus into a single Bus LVDS data stream with embedded clock. This single serial data stream with embedded clock simplifies PCB design and reduces PCB cost by narrowing data paths that in turn reduce PCB size and layers. The single serial data stream also reduces cable size, the number of connectors, and eliminates clock-to-data and data-to-data skew. Each channel also has an 8-level selectable pre-emphasis feature that significantly extends performance over lossy interconnect. Each channel also has its own powerdown pin that saves power by reducing supply current when the channel is not being used. The SCAN921821 also incorporates advanced testability features including IEEE 1149.1 and at-speed BIST PRBS pattern generation to facilitate verification of board and link integrity n 15-66 MHz Dual 18:1 Serializer with 2.376 Gbps total throughput n 8-level selectable pre-emphasis on each channel drives lossy cables and backplanes n > 15kV HBM ESD protection on Bus LVDS I/O pins n Robust BLVDS serial data transmission with embedded clock for exceptional noise immunity and low EMI n Power saving control pin for each channel n IEEE 1149.1 "JTAG" Compliant n At-Speed BIST - PRBS generation n No external coding required n Internal PLL, no external PLL components required n Single +3.3V power supply n Low power: 260 mW (typ) per channel at 66 MHz with PRBS-15 pattern n Single 3.3 V supply n Fabricated with advanced CMOS process technology n Industrial −40 to +85˚C temperature range n Compact 100-ball FBGA package Block Diagram 20084401 © 2004 National Semiconductor Corporation DS200844 www.national.com SCAN921821 - Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1 (JTAG), and At-Speed BIST November 2004 SCAN921821 Absolute Maximum Ratings (Note 1) Derating Above 25˚C If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. θJC Supply Voltage (VDD) −0.3V to +4V Supply Voltage (VDD) Ramp Rate < 30 V/ms 28.57 mW/˚C Thermal resistance θJA 35˚C/W 11.1˚C/W ESD Rating HBM, 1.5 KΩ, 100 pF > 8 kV > 15 kV > 1200 V > 2 kV All pins LVCMOS/LVTTL Input Voltage −0.3V to (VDD +0.3V) LVCMOS/LVTTL Output Voltage −0.3V to (VDD +0.3V) Bus LVDS Driver Output Voltage −0.3V to +3.9V Bus LVDS Output Short Circuit Duration 10ms Bus LVDS pins MM, 0Ω, 200 pF Junction Temperature +150˚C Storage Temperature −65˚C to +150˚C CDM Recommended Operating Conditions Lead Temperature (Soldering, 4 seconds) +220˚C Min Nom Max Units Supply Voltage (VDD) 3.15 3.3 3.45 V Operating Free Air Temperature (TA) −40 +25 +85 ˚C Clock Rate 15 Supply Noise 66 MHz 100 mV p-p Maximum Package Power Dissipation at 25˚C FBGA-100 3.57 W DC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units LVCMOS/LVTTL Input DC Specifications VIH High Level Input Voltage 2.0 VDD V VIL Low Level Input Voltage GND 0.8 V VCL Input Clamp Voltage ICL = −18 mA −1.5 -0.7 IINH High Level Input Current VIN = VDD = VDDMAX −20 ±2 +20 µA IINL Low Level Output Current VIN = VSS, VDD = VDDMAX −10 ±2 +10 µA V 1149.1 (JTAG) DC Specifications VIH High Level Input Voltage 2.0 VDD V VIL Low Level Input Voltage GND 0.8 V VCL Input Clamp Voltage ICL = −18 mA −1.5 IINH High Level Input Current VIN = VDD = VDDMAX -20 +20 µA IINL Low Level Output Current VIN = VSS, VDD = VDDMAX -200 +200 µA VOH High Level Output Voltage IOH = −9 mA 2.3 VDD mV VOL Low Level Output Voltage IOL = 9 mA GND 0.5 mV IOS Output Short Circuit Current VOUT = 0 V -100 -50 mA IOZ Output Tri-state Current PWDN or EN = 0.8V, VOUT = 0 V -10 +10 µA PWDN or EN = 0.8V, VOUT = VDD -30 +30 µA www.national.com 2 -0.7 -80 V (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units Figure 10, RL = 100Ω 450 500 550 mV 2 15 mV 1.2 1.25 V 2.7 15 mV Bus LVDS Output DC Specifications VOD Output Differential Voltage (DO+) (DO-) ∆VOD Output Differential Voltage Unbalance VOS Offset Voltage ∆VOS Offset Voltage Unbalance QPOV Pre-Emphasis Output Voltage Ratio | VODPRE / VOD | IOS Output Short Circuit Current IOZ TRI-STATE Output Current 1.05 Pre-Emphasis Level = 1 1.10 1.24 1.35 Pre-Emphasis Level = 2 1.35 1.47 1.55 Pre-Emphasis Level = 3 1.55 1.70 1.80 Pre-Emphasis Level = 4 1.80 1.91 1.95 Pre-Emphasis Level = 5 1.95 2.08 2.20 Pre-Emphasis Level = 6 2.10 2.21 2.35 Pre-Emphasis Level = 7 2.15 2.30 2.50 DO = 0V, Din = H, PWDN and EN = 2.4V -10 -25 -75 mA PWDN or EN = 0.8V, DO = 0V (Note 4) -10 µA -55 ±1 ±6 +10 PWDN or EN = 0.8V, DO = VDD (Note 4) +55 µA f = 66 MHz, PRBS-15 Pattern 160 225 mA f = 66 MHz, Worst Case Pattern (Checker-Board Pattern) 180 mA f = 66 MHz, PRBS-15 Pattern 240 mA f = 66 MHz, Worst Case Pattern (Checker-Board Pattern) 280 325 mA 1.0 3.0 mA Power Supply Current (DVDD, PVDD and AVDD Pins) IDD IDDP IDDX Total Supply Current (includes load current) Total Supply Current with Pre-Emphasis (includes load current) Supply Current Powerdown CL = 15pF, RL = 100 Ω CL = 15pF, RL = 100 Ω PWDN = 0.8V, EN = 0.8V Timing Requirements for TCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Min Typ Max Units tTCP Transmit Clock Period Conditions 15.2 T 66.7 ns tTCIH Transmit Clock High Time 0.4T 0.5T 0.6T ns tTCIL Transmit Clock Low Time 0.4T 0.5T 0.6T ns tCLKT TCLK Input Transition Time 3 6 ns tJIT TCLK Input Jitter 80 ps (RMS) (Note 5) 3 www.national.com SCAN921821 DC Electrical Characteristics SCAN921821 AC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units 0.3 0.4 ns 0.3 0.4 ns Serializer AC Specifications tLLHT Bus LVDS Low-to-High Transition Time tLHLT Bus LVDS High-to-Low Transition Time tDIS DIN (0-17) Setup to TCLK tDIH DIN (0-17) Hold from TCLK tHZD DO ± HIGH to TRI-STATE Delay tLZD DO ± LOW to TRI-STATE Delay tZHD DO ± TRI-STATE to HIGH Delay tZLD DO ± TRI-STATE to LOW Delay tSPW SYNC Pulse Width Figure 7, RL = 100Ω tPLD Serializer PLL Lock Time Figure 6, RL = 100Ω tSD Serializer Delay Figure 8 , RL = 100Ω tSKCC Channel to Channel Skew tRJIT Random Jitter tDJIT Deterministic Jitter Figure 9, (Note 5) Figure 2, (Note 5) RL = 100Ω, CL=10pF to GND Figure 4, (Note 5) RL = 100Ω, CL=10pF to GND 1.9 ns 0.6 ns 3.9 10 ns 3.5 10 ns 3.2 10 ns 2.4 10 ns 5*tTCP 6*tTCP ns 510*tTCP 1024*tTCP ns tTCP + 2.5 tTCP + 4.5 tTCP + 6.5 ns 70 ps 6.1 ps (RMS) Figure 5 RL = 100Ω, CL=10pF to GND Room Temperature, VDD = 3.3V, 66 MHz 15 MHz -390 320 ps 66 MHz -60 30 ps 1149.1 (JTAG) AC Specifications fMAX Maximum TCK Clock Frequency 25 MHz tS TDI or TMS Setup to TCK, H or L 2.4 ns tH TDI or TMS Hold from TCK, H or L 2.8 ns tW1 TCK Pulse Width, H or L 10 ns tW2 TRST Pulse Width, L 10 ns tREC Recovery Time, TRST to TCK 2 ns CL = 15pF, RL = 500 Ω Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Typical values are given for VCC = 3.3V and TA = +25˚C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ∆VOD, VTH and VTL which are differential voltages. Note 4: IOZ is measured at each pin. The DOUT pin not under test is floated to isolate the TRI-STATE current flow. Note 5: Guaranteed by Design (GBD) using statistical analysis. www.national.com 4 SCAN921821 AC Timing Diagrams and Test Circuits 20084403 FIGURE 1. “Worst Case” Serializer IDD Test Pattern 20084405 FIGURE 2. Serializer Bus LVDS Distributed Output Load and Transition Times 20084407 FIGURE 3. Serializer Input Clock Transition Time 20084408 FIGURE 4. Serializer Setup/Hold Times 5 www.national.com SCAN921821 AC Timing Diagrams and Test Circuits (Continued) 20084409 FIGURE 5. Serializer TRI-STATE Test Circuit and Timing 20084410 FIGURE 6. Serializer PLL Lock Time, and PWRDN TRI-STATE Delays www.national.com 6 SCAN921821 AC Timing Diagrams and Test Circuits (Continued) 20084434 FIGURE 7. SYNC Timing Delay 20084411 FIGURE 8. Serializer Delay 7 www.national.com SCAN921821 AC Timing Diagrams and Test Circuits (Continued) 20084429 FIGURE 9. Deterministic Jitter and Ideal Bit Position 20084416 VOD = (DO+)–(DO−). Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode. FIGURE 10. VOD Diagram Pre-emphasis Truth Table www.national.com PEM LEVEL PEM2 PEM1 PEM0 0 L L L 1 L L H 2 L H L 3 L H H 4 H L L 5 H L H 6 H H L 7 H H H 8 SCAN921821 Pin Diagram SCAN921821TVV Top View 20084402 9 www.national.com SCAN921821 Pin Descriptions Pin Name Pin Count I/O, Type Description I, LVCMOS Transmitter inputs. There is a pull-down circuitry on each of these pins which are active if respective PWDNA or PWDNB pin is pulled high. DATA PINS DINA0-17 18 DINB0-17 18 DOUTAP 1 DOUTAN 1 DOUTBP 1 DOUTAN 1 O,BLVDS Inverting and non-inverting differential transmitter outputs. TIMING AND CONTROL PINS TxCLK 1 ENA 1 ENB 1 PWDNA 1 PWDNB 1 SYNCA 1 SYNCB 1 I, LVCMOS Transmitter reference clock. Used to strobe data at the inputs and to drive the transmitter PLL. There is a pull-up circuitry on this pin which is always active. I, LVCMOS Transmitter outputs enable pins. There is a pull-down circuitry on each of these pins that are active if corresponding PWDNA or PWDNB pin is pulled high. When these pins are set to LOW, the transmitter outputs will be disabled. The PLL will remain locked. I, LVCMOS Stand-by mode pins. There is a pull-down circuitry on each of these pins that are always active. When these pins are set to LOW, the transmitter will be put in low power mode and the PLL will lose lock. I, LVCMOS Transmitter synchronization pins. There is a pull-down circuitry on each of these pins that are active if corresponding PWDNA or PWDNB pin is pulled high. When these pins are set to HIGH, the transmitter will ignore incoming data and send SYNC patterns to provide a locking reference to receiver(s). I, LVCMOS 8-level pre-emphasis selection pins. There is a pull-down circuitry on each of these pins which are active if corresponding PWDNA or PWDNB pin is pulled high. PRE-EMPHASIS PINS PEMA0-2 PEMB0-2 3 3 JTAG PINS TDI 1 I, LVCMOS Test Data Input to support IEEE 1149.1. There is a pull-up circuitry on this pin which is always active. TDO 1 O, LVCMOS Test Data Output to support IEEE 1149.1. TMS 1 I, LVCMOS Test Mode Select Input to support IEEE 1149.1. There is a pull-up circuitry on this pin which is always active. TCK 1 I, LVCMOS Test Clock Input to support IEEE 1149.1. There is no failsafe circuitry on this pin. TRST 1 I, LVCMOS Test Reset Input to support IEEE 1149.1. There is a pull-up circuitry on this pin which is always active. BISTA 1 I, LVCMOS BISTB 1 BIST selection pins. These pins select which transmitter will generate a PRBS like data. There is a pull-down circuitry on these pins which are active if corresponding PWDNA or PWDNB pin is pulled high. BIST PINS POWER PINS AVDD 6 I, POWER Power Supply for the LVDS circuitry. DVDD 8 I, POWER Power Supply for the digital circuitry. PVDD 5 I, POWER Power Supply for the PLL and BG circuitry. AVSS 5 I, POWER Ground reference for the LVDS circuitry. DVSS 10 I, POWER Ground reference for the digital circuitry. PVSS 5 I, POWER Ground reference for the PLL and BG circuitry. 1 N/A OTHER PINS NC www.national.com Not connected. 10 inches (millimeters) unless otherwise noted Dimensions shown in millimeters only Order Number SCAN921821TSM NS Package Number SLC100A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: [email protected] Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: [email protected] National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: [email protected] Tel: 81-3-5639-7560 SCAN921821 - Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1 (JTAG), and At-Speed BIST Physical Dimensions