Features • • • • • • • • Supply-voltage Range 3V to 4.6V (Regulated) Auxiliary Voltage Regulator On-chip (3.2V to 4.6V) Low Current Consumption Few Low-cost External Components No Mechanical Tuning Required Supports Multiple Reference Clocks (10.368 MHz/13.824 MHz) Fast Settling Synthesizer (864 kHz Channel Spacing) TX Preamplifier with 3 dBm Output Power at 2.45 GHz (4 Programmable Power Levels) • Ramp-signal Generator for Power Ramping and Power Control of External SiGe Power Amplifier (T7024 and T7026) 2.4 GHz WDECT/ISM Single-chip Transceiver Electrostatic sensitive device. Observe precautions for handling. T2803 1. Description The T2803 is an RF IC for low-power applications in the 2.45 GHz ISM band. The QFN48-packaged IC is a complete transceiver including image rejection mixer, IF amplifier, FM demodulator, baseband filter, RSSI, TX preamplifier, power-ramping generator for power amplifiers, integrated synthesizer, fully integrated VCO and Gaussian data filter for TX. No mechanical tuning is necessary in production. Figure 1-1. Block Diagram DEMOD MIXER OUT IF_IN IF_TANK IF AMP 1 IR MIXER CF TANK IF AMP 2 BB_OUT RF_IN DEMOD BB FILTER RAMP_OUT RAMP_SET RAMP GEN D/A RAMP D/A DEMOD DAC RSSI RSSI GF VCO TX/RX SWITCH TX_DATA PC 3-WIRE BUS PD f TX_OUT CLOCK DATA ENABLE :n TX DRIVER VCO REG AUX REG RC CP VREG_VCO VS_VCO VREG VS_REG OLE GND_VCO PU_REG REG_CTRL VTUNE f :n CP LD CTRL LOGIC RX_ON TX_ON PU_RX/TX PU_PLL REF_CLK I_CPSW Rev. 4572I–DECT–07/05 Table 1-1. Functional Block Description Name Description AUX REG Auxiliary voltage regulator BBF Baseband filter CP Charge pump DAC D/A converter for demodulator tuning DEMOD Demodulator GF Gaussian filter for transmit data IF AMP1 1st intermediate frequency amplifier IF AMP2 2nd intermediate frequency amplifier IR MIXER Image rejection mixer PC Programmable counter PD Phase detector RAMP GEN Ramp-signal generator RC Reference counter RSSI Received signal-strength indicator TX DRIVER Buffer amplifier for TX_OUT TX/RX SWITCH Switches VCO signal to IR MIXER respectively TX DRIVER VCO Voltage-controlled oscillator VCO REG Voltage regulator for VCO 2. Pin Configuration RX_ON RAMP_SET TX_ON VS_MIXER GND_PLL PU_RX/TX OLE TX_DATA PU_PLL Pinning QFN48 I_CPSW Figure 2-1. 48 47 46 45 44 43 42 41 40 39 38 37 CLOCK 1 36 RAMP_OUT DATA 2 35 IF_IN2 ENABLE 3 34 IF_IN1 REF_CLK 4 33 VS_IF LD 5 32 TX_OUT PU_REG 6 31 GND3 VS_PLL 7 30 RF_IN2 VREG 8 29 RF_IN1 REG_CTRL 9 28 GND2 IF_TANK2 T2803 VS_REG 10 27 GND_CP 11 26 IF_TANK1 VS_CP 12 25 RSSI 2 BB_OUT BB_CF DAC_DEC REG_DEC DEMOD_TANK2 GND1 DEMOD_TANK1 VTUNE GND_VCO VS_VCO VREG_VCO CP 13 14 15 16 17 18 19 20 21 22 23 24 T2803 4572I–DECT–07/05 T2803 Table 2-1. Pin Pin Description Symbol Function Configuration VS_PLL 1 CLOCK 3-wire-bus: Clock input 2 DATA 3-wire-bus: Data input 3 ENABLE 3-wire-bus: Enable input 7 CLOCK DATA ENABLE 1,2,3 5k 5k GND_PLL 43 VS_PLL 7 4 REF_CLK Reference-frequency input 10k 10k REF_CLK 4 GND_PLL 43 LD 5 5 LD 100 Lock-detect output GND_PLL 43 PU_REG 6 6 PU_REG Power-up input for auxiliary voltage regulator 25k 25k GND_PLL 43 3 4572I–DECT–07/05 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration VS_PLL 7 GND1 VS_REG 10 18 VS_CP 12 GND2 28 VS_VCO 14 7 VS_PLL GND3 PLL supply voltage 31 VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 VS_REG 10 VS_PLL 7 8 VREG REG_CTRL 9 Auxiliary voltage-regulator output VREG 8 9 REG_CTRL Auxiliary voltage-regulator control output 10 VS_REG Auxiliary voltage-regulator supply voltage GND_PLL 43 VS_CP 12 11 GND_CP 12 VS_CP 13 CP Charge-pump ground Charge-pump supply voltage VS_PLL 7 CP 13 Charge-pump output GND_PLL 43 GND_CP 11 4 T2803 4572I–DECT–07/05 T2803 Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration VS_VCO 14 VS_PLL 7 14 VS_VCO VCO voltage-regulator supply voltage 15 VREG_VCO VCO voltage-regulator control output VREG_VCO 15 16 GND_VCO VCO ground GND_PLL 43 GND_VCO 16 VREG_VCO 15 VS_PLL 7 17 VTUNE VCO tuning voltage input VTUNE 17 GND_PLL 43 GND_VCO 16 VS_PLL 7 GND1 VS_REG 10 VS_CP 12 18 GND2 28 VS_VCO 14 GND3 18 GND1 Ground 31 VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 5 4572I–DECT–07/05 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration VS_MIXER 42 19 DEMOD_TANK1 VS_IF 33 10k Demodulator tank circuit 10k DEMOD TANK1 19 20 DEMOD_TANK2 DEMOD TANK2 20 Demodulator tank circuit GND2 28 GND1 18 VREG_VCO 15 VS_PLL 7 21 DAC_DEC Decoupling pin 10k DAC_DEC 21 GND_PLL 43 400 GND_VCO 16 VREG_VCO 15 VS_IF 33 22 REG_DEC 2k Decoupling pin for VCO_REG REG_DEC 22 42k GND2 28 GND_VCO 16 6 T2803 4572I–DECT–07/05 T2803 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration VS_IF 33 23 BB_CF Baseband filter corner-frequency control input BB_CF 23 GND2 28 GND1 18 VS_IF 33 24 BB_OUT Baseband filter output BB_OUT 24 GND2 28 GND1 18 VS_IF 33 25 RSSI Received signal strength indicator output RSSI 25 13k GND2 28 VS_IF 33 26 IF_TANK1 IF tank circuit IF_TANK1 26 27 IF_TANK2 27 IF tank circuit GND2 28 7 4572I–DECT–07/05 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration VS_PLL 7 GND1 VS_REG 10 VS_CP 12 18 GND2 28 VS_VCO 14 GND3 28 GND2 Ground 31 VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 VS_MIXER 42 29 RF_IN1 RF input of image reject mixer RF_IN1 29 30 RF_IN2 RF_IN2 30 RF input of image reject mixer GND2 28 VS_PLL 7 GND1 VS_REG 10 VS_CP 12 18 GND2 28 VS_VCO 14 GND3 31 GND3 Ground 31 VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 8 GND_PLL 43 T2803 4572I–DECT–07/05 T2803 Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration TX_OUT 32 32 TX_OUT TX driver amplifier output for PA GND3 31 VS_PLL 7 GND1 VS_REG 10 18 VS_CP 12 GND2 28 VS_VCO 14 GND3 33 VS_IF IF amplifier supply voltage 31 VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 VS_IF 33 34 IF_IN1 IF input of IF amplifier IF_IN1 34 35 IF_IN2 90k IF_IN2 35 IF input of IF amplifier GND2 28 VS_MIXER 42 VS_IF 33 36 RAMP_OUT Ramp-generator output for PA power ramping RAMP_OUT 36 GND2 28 9 4572I–DECT–07/05 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration VS_MIXER 42 VS_IF 33 37 RAMP_SET Slew-rate setting of ramping signal 1k 100 RAMP SET 37 GND2 28 VS_IF 33 38 RX_ON RX control input 39 TX_ON TX control input RX_ON TX_ON 38, 39 5k 5k GND2 28 GND1 18 VS_MIXER 42 VS_IF 33 40 MIXER_OUT1 270 Mixer output to SAW filter MIXER_OUT1 40 41 MIXER_OUT2 270 MIXER_OUT2 41 Mixer output to SAW filter GND2 28 10 T2803 4572I–DECT–07/05 T2803 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration VS_PLL 7 GND1 VS_REG 10 18 VS_CP 12 GND2 28 42 VS_MIXER Mixer supply voltage VS_VCO 14 GND3 31 43 GND_PLL PLL ground VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 VS_PLL 7 44 OLE Open loop enable input OLE 44 5k 5k GND_PLL 43 PU_RX/TX 45 45 PU_RX/TX 25k RX/TX power-up input 25k GND18 18 11 4572I–DECT–07/05 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration 20k 10k PU PLL 46 46 PU_PLL 10k 10k 25k 25k 140k PLL power-up input GND PLL 43 5k 5k VS_PLL 7 VS_PLL 7 47 TX_DATA TX data input of Gaussian filter TX_DATA 47 2.5k GND_PLL 43 VS_PLL 7 48 I_CPSW Charge-pump current control input I_CPSW 48 5k GND_PLL 43 12 T2803 4572I–DECT–07/05 T2803 3. Functional Description 3.1 Receiver The RF signal at RF_IN is fed to an image rejection mixer IR_MIXER with its differential outputs MIXER_OUT1 and MIXER_OUT2 driving an IF-SAW filter at 110.592 MHz or 112.32 MHz. The IF_AMP1 and IF_AMP2 IF amplifiers with an external IF_TANK and an integrated RSSI function feed the signal to the demodulator DEMOD working at f = fIF/2 (≈ 55 MHz) and finally to an integrated baseband filter BB. For demodulator tunning in production an integrated 5-bit digital-to-analog (D/A) converter is provided to control the on-chip varicap diode. 3.2 Transmitter The transmit data at TX_DATA is filtered by an integrated Gaussian Filter GF and fed to the fully integrated VCO operating at twice the output frequency. After modulation the signal is frequency-divided by 2 and fed via a TX/RX SWITCH to the TX_DRIVER. This bus-controlled driver amplifier supplies typically +3 dBm output power at TX_OUT. A ramp-signal generator RAMP_GEN, providing a ramp signal at RAMP_OUT for the external power amplifier, is integrated. The slope of the ramp signal is controlled by a capacitor at the RAMP_SET pin. 3.3 Synthesizer The IR_MIXER, the TX_DRIVER and the programmable counter PC are driven by the fully integrated VCO (including on-chip inductors and varactors). The output signal is frequency-divided to supply the desired frequency to the TX_DRIVER, 0/90 degree phase shifter for the IR_MIXER and to be used by the PC for the phase detector PD (fPD = 1.728 MHz). Open loop modulation is supported. 3.4 Power Supply An integrated bandgap-stabilized voltage regulator for use with an external low-cost PNP transistor is implemented. Multiple power-down and current saving modes are provided. 13 4572I–DECT–07/05 Figure 3-1. PLL Principle RF_IN Programable counter PC "- Main counter MC "- Swallow counter SC fVCO = fPD x (SMC x 32 + SSC) fVCO ext. loop filter PA driver Phase frequency detector PD fPD = 1.728 MHz Charge pump Divider by 2 VCO Mixer VCO DAC GF_DATA Gaussian filter GF Reference counter RC REF_CLK 6.912 MHz SRC 10.368 MHz 6 13.824 MHz 8 1.152 Mbit/s PLL reference Frequency REF_CLK TX_DATA Baseband controller 14 T2803 4572I–DECT–07/05 T2803 Table 3-1 shows the LO frequencies for RX and TX for the DECT band plus additional channels for the extended DECT band. Intermediate frequencies of 110.592 MHz and 112.32 MHz are supported. Table 3-1. Mode LO Frequencies fIF/MHz TX RX RX Formula TX: RX: Channel fANT/MHz fVCO/MHz SMC SSC N C0 2401.056 2401.056 86 27 2779 C1 2401.920 2401.920 86 28 2780 ... ... ... ... ... ... C93 2481.408 2481.408 89 24 2872 C94 2482.272 2482.272 89 25 2873 C0 2401.056 2290.464 82 27 2651 C1 2401.920 2291.328 82 28 2652 – 110.592 (for 10.368 MHz REF_CLK recommended) 112.320 (for 13.824 MHz REF_CLK recommended) ... ... ... ... ... ... C93 2481.408 2370.816 85 24 2744 C94 2482.272 2371.680 85 25 2745 C0 2401.056 2288.736 82 25 2649 C1 2401.920 2289.600 82 26 2650 ... ... ... ... ... ... C93 2481.408 2369.088 85 22 2742 C94 2482.272 2369.952 85 23 2743 fANT = fVCO = 864 kHz × (32 × SMC + SSC) fANT = 864 kHz × (32 × SMC + SSC) + fIF 4. Control Signals Table 4-1. Control Signals – Functions Signal Functions I_CPSW Charge pump current control PU_REG Activates AUX voltage regulator supplying the complete transceiver PU_RX/TX Activates RX/TX blocks PU_PLL Activates PLL circuits: PC, PD, CP, RC, VCO RX_ON Activates RX circuits: BBF, DEMOD, IF AMP, IR MIXER TX_ON Activates TX circuits: TX-DRIVER, RAMP GEN, Starts RAMP SIGNAL at RAMP OUT OLE Activates open loop mode of the PLL Data Word 1, bit D0 Activates GF 15 4572I–DECT–07/05 Table 4-2. Control Signals – Modes Modes TX Mode RX Mode RSSI Only PU_REG 1 1 1 PU_VCO 1 1 1 PU_RX/TX 1 1 1 PU_PLL 1 1 1 RX_ON 0 1 1 TX_ON 1 0 1 BB filter OFF ON OFF Demodulator OFF ON OFF IF amplifiers and RSSI OFF ON ON IR mixer OFF ON ON RX switch OFF ON ON TX switch ON OFF OFF TX driver ON OFF OFF Ramp generator ON OFF OFF Programmable counter ON ON ON Voltage-controlled oscillator ON ON ON Gaussian filter ON OFF OFF Phase detector/charge pump ON ON ON Reference counter ON ON ON 56 mA 85 mA 82 mA Typical current consumption at VS = 3.2V 5. Serial Programming Bus The transceiver is programmed by the 3-wire bus (CLOCK, DATA and ENABLE). After setting enable signal to low condition, on the rising edge of the clock signal, the data is transferred bit by bit into the shift register, starting with the MSB-bit. When the enable signal has returned to high condition, the programmed information is loaded into the addressed latches according to the address bit condition (last bit). Additional leading bits are ignored and there is no check made how many pulses arrived during enable low condition. During enable low condition, the bus current is increased to speed up the bus logic. The programming of the transceiver is separated into two data words. Data word 1 controls mainly the channel information together with settings, which are closely related with the channel. Data word 2 holds setup information, which is adjusted during production. 16 T2803 4572I–DECT–07/05 T2803 5.1 Data Word 1 MSB LSB Data bits Address bit D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A0 RC GFCS SC MC VS x 0 0 0 0 0 CPCS GF 1 D11 = x: do not care 5.2 Data Word 2 E12 E11 E10 PA E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 DEMODDAC/RAMPDAC x x x TEST A0 0 E3, E4, E5 = x: do not care 6. Data Word 1 Programs 6.1 PLL Settings Table 6-1. With the Reference Counter bits D22-D22 RC (Reference Counter) Table 6-2. D22 SRC REF_CLK 0 6 10.368 MHz 1 8 13.824 MHz With the Main Counter bits D13-D16 MC (Main Counter) D16 D15 D14 D13 SMC 0 0 0 0 80 0 0 0 1 81 ... ... ... ... ... 1 1 1 0 94 1 1 1 1 95 17 4572I–DECT–07/05 Table 6-3. With the Swallow Counter bits D17-D21 SC (Swallow Counter) 6.2 D21 D20 D19 D18 D17 SSC 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 ... ... ... ... ... ... 1 1 1 0 1 29 1 1 1 1 0 30 1 1 1 1 1 31 VCO Selection Table 6-4. With bit D12 VCO Selection 6.3 VCO Mode 0 VCO 1 1 VCO 2 Gaussian Filter On/off Table 6-5. 6.4 D12 With bit D0, GF is used only in TX mode D0 GF (Gaussian Filter) 0 OFF 1 ON GFCS Adjustment Table 6-6. With bits D7-D9, only in TX mode effective for setting the frequency deviation of the modulation GFCS (Gaussian Filter Settings) 18 D9 D8 D7 GFCS 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130% T2803 4572I–DECT–07/05 T2803 6.5 CPCS Adjustment Table 6-7. With bits D1-D2 CPCS (Charge-Pump Current Settings) Note: D2 D1 CPCS 0 0 –1 0 1 0 1 0 1 1 1 2 Used to adjust the charge pump current. This can be used to compensate the change of the tuning sensitivity over frequency and device tolerances. 7. Data Word 2 Programs 7.1 DEMODDAC Adjustment Table 7-1. With bits E6-E10 Demod DAC Voltage E10 E9 E8 E7 E6 fIFcenter % 0 0 0 0 0 –5 0 0 0 0 1 ... 0 0 0 1 0 ... ... ... ... ... ... ... 1 1 1 0 1 ... 1 1 1 1 0 ... 1 1 1 1 1 5 Note: Only in RX mode effective. Used to tune the demodulator center frequency and allows to compensate tolerances of external components and the T2803. 19 4572I–DECT–07/05 7.2 RAMPDAC Adjustment for TX Mode Table 7-2. With bits E6-E10 RAMPDAC Voltage (at Pin 36 RAMP_OUT) E10 E9 E8 E7 E6 VRAMP_OUT 0 0 0 0 0 1.1V 0 0 0 0 1 ... 0 0 0 1 0 ... ... ... ... ... ... ... 1 0 1 1 1 1.68V 1 1 0 0 0 1.7V ... ... ... ... ... ... 1 1 1 1 0 ... 1 1 1 1 1 1.7V Note: 7.3 Only in TX mode effective. Used to control the power of the external PA by adjusting the ramping voltage TEST Mode Settings Table 7-3. E2 E1 E0 Signal at Lock Detect Output CP Mode 0 0 0 Lock detect Active 0 0 1 PC out/2 Active 0 1 0 RC out/2 Active 0 1 1 do not care Active 1 0 0 Lock detect Active 1 0 1 PC out/2 Active 1 1 0 RC out/2 Active 1 1 1 GFTEST: RC out Active Note: 7.4 With bits E0-E2 In normal operation Lock detect output is used. All other settings are for test only. Output Power Settings Table 7-4. With bits E11-E12 PA (Output Power Settings) Note: 20 E12 E11 PA 0 0 –21 dBm 0 1 –11 dBm 1 0 –4 dBm 1 1 +3 dBm Use of maximum power (+3 dBm) for external PA is recommended. T2803 4572I–DECT–07/05 T2803 Figure 7-1. 3-wire Bus Protocol Timing Diagram DATA CLOCK ENABLE TC TPER TL TS Table 7-5. TT TEC TH 3-wire bus Protocol Table Description Symbol Minimum Value Unit Clock period TPER 125 ns Set time data to clock TS 60 ns Hold time data to clock TH 60 ns Clock pulse width TC 125 ns Set time enable to clock TL 200 ns Hold time enable to data TEC 0 ns TT 250 ns Time between two protocols Figure 7-2. TX DATA Timing RefCLK TX_DATA TS Set-up time TX DATA TS > 8 ns Hold time TX DATA TH > 8 ns TH When using REFCLK = 10.368 MHz, TS and TH must be considered for falling and rising edge of REFCLK 21 4572I–DECT–07/05 8. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages refer to GND Parameters Pin Symbol Min. Max. Unit Supply voltage regulator 10 VS_REG 3.2 4.7 V 7, 12, 14, 33, 42 VS 3.0 4.7 V 1, 2, 3, 38, 39, 44-48 VIN –0.3 VS V 125 °C 150 °C Supply voltage Logic input voltage Junction temperature Tjmax Storage temperature Tstg –40 9. Thermal Resistance Parameters Junction ambient Symbol Value Unit RthJA 25 K/W 10. Handling Do not operate this part near strong electrostatic fields. This IC meets class 1 ESD test requirement (HBM in accordance to EIA/JESD22-A114-A (October 97) and class A ESD test requirement (MM) in accordance to EIA/JESD22-A115A. 11. Operating Range Parameters Pin Symbol Min. Typ. Max. Unit Supply voltage regulator 10 VS_REG 3.2 3.6 4.6 V 7, 14, 33, 42 VS 2.9 3.0 4.6 V 12 VSCP VS 4.6 V Tamb –10 +60 °C Supply voltage Supply voltage charge pump Ambient temperature 22 T2803 4572I–DECT–07/05 T2803 12. Electrical Characteristics Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25°C Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit IR Mixer (Pins 29, 30, 40 and 41) Input impedance Pins 29 or 30 (single ended) Zin 110 + j12 Ω Image rejection ratio Pins 40 and 41 IRR 20 dB DSB noise figure Pins 29 or 30 (single ended) NFDSB = NFSSB 10 dB Conversion gain Rload = 200Ω Gconv 11 dB Input intercept point Pins 29 or 30 (single ended) IIP3 –7 dBm Pin 40 and 41 (differential) ZOUT 175 + j145 Ω Pins 34 and 35 (differential) Zin 1200 – j480 Ω Lower cut-off frequency fl3dB 90 MHz Upper cut-off frequency fu3dB 130 MHz Gp 85 dB BW3dB 10 MHz NF 9 dB Output impedance IF Amplifier (Pins 26, 27, 34 and 35) Input impedance Power gain Bandwidth of external tank circuit Pins 26 and 27 Noise figure RSSI (Pins 25, 34 and 35) RSSI sensitivity At IF_IN1,2; pins 34 and 35 Pmin 20 dBµV RSSI compression At IF_IN1,2; pins 34 and 35 Pmax 100 dBµV DR 80 dB Acc ±2 dB RSSI dynamic range RSSI resolution Slope of the RSSI has to be steady RSSI rise time Pin = 30 to 100 dBµV, pin 25 tr 1 µs RSSI fall time Pin = 100 to 30 dBµV, pin 25 tf 1 µs Quiescent output voltage At Pin < 20 dBµV at IF_IN1, IF_IN2, pin 25 Vout 0.4 V Maximum output voltage At Pin = 100 dBµV at IF_IN1, IF_IN2, pin 25 Vout 1.9 V FM Demodulator, BB-filter (Pins 19, 20, 23 and 24) Co-channel rejection ratio at Pin = –75 dBm at IR-mixer input CCRR 10 dB Sensitivity Quality factor of external tank circuit approximately 20, fres = FIF/2, pin 24 S 0.5 V/MHz Amplitude of recovered signal Nominal deviation of signal ±400 kHz, pin 24 A 450 mVpp Corner frequency Pin 23: C = 68 pF fc 680 kHz Output voltage DC range Pin 24 DEMOD_DAC range (see bus protocol E6 to E10) VoutDC 1 VS – 1 ±5 ∆fIFcenter V % VCOs Frequency range VCO 1, D12 VS = 1 VCO 2, D12 VS = 0 Tuning gain Frequency control voltage range fvco fvco 2289 2289 200 Gtune Pin 17 Vtune 2483 2483 0.4 MHz MHz MHz/V 2.8 V 23 4572I–DECT–07/05 12. Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25°C Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit PLL SPSC 32/33 Scaling factor main counter SMC 82-89 Scaling factor swallow counter SSC Scaling factor prescaler External reference input frequency AC coupled sinewave, pin 4 fREF_CLK External reference input voltage AC coupled sinewave, pin 4 VREF_CLK Scaling factor reference counter 0 31 10.368 13.824 50 MHz MHz 250 SRC 6/8 mVRMS Charge Pump (Pin 13) Output current VCP = VVS_CP/2, I_CPSW = 1, pin 48 ICP_nom ±7.5 mA Output current VCP = VVS_CP/2, I_CPSW = 0, pin 48 ICP_nom ±1.2 mA Current scaling ICP = ICP_nom + CPCS × ICP_step (see bus protocol D1 ... D2) ICP_step 0.2 mA Leakage current OLE = 1 IL ±100 pA 1152 kBit/s fTXFCLK 6.912 MHz GFFM_nom ±400 kHz Gaussian Transmit Filter (Gaussian Shape B × T = 0.5) Tx data rate Tx data filter clock 6 taps in filter Frequency deviation GFFM = GFFM_nom × GFCS (see bus protocol D7 ... D9) GFCS Maximum output power At L = 5.6 nH, pin 32 (see bus protocol E11-E12) PTX 3 dBm Minimum output power At L = 5.6 nH, pin 32 (see bus protocol E11-E12) PTX –21 dBm RF leakage In RX mode Pleak Output impedance At L = 5.6 nH, 2.5 GHz, pin 32 ZOUT 13+j40 Ω Vmin 0.7 V Frequency deviation scaling 60 130 % TX Driver (Pin 32) –47 dBm Ramp Generator (Pins 36 and 37) Minimum output voltage Vmax 1.1 1.8 V Maximum output voltage (see bus protocol E6-E10) Rise time Cramp = 270 pF at pin 37 tr 5 µs Fall time Cramp = 270 pF at pin 37 tf 5 µs Lock Detect and Test Mode Output (Pin 5) Locked = 1, unlocked = 0 Lock detect output, test mode output Test modes (see bus protocol E0 ... E2) Leakage current VOH = 4.6V Saturation voltage IOL = 0.5 mA LD IL 5 µA VSL 0.4 V Auxiliary Regulator (Pins 8, 9 and 10) Output voltage VSREG = 3V, pin 8 VREG 2.9 3.0 3.1 V VSVCO = 3V, pin 15 VREG_VCO 2.6 2.7 2.8 V VCO Regulator (Pins 14, 15 and 12) Output voltage 24 T2803 4572I–DECT–07/05 T2803 12. Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25°C Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit 6.912 MHz 3-wire Bus Clock fClock Logic Input Levels (CLOCK, DATA, ENABLE, RX_ON, TX_ON, OLE, TX_DATA, DATA_HOLD) (Pins 1, 2, 3, 38, 39, 44, 47 and 48) High input level 1.5 V =1 ViH Low input level =0 ViL 0.5 V High input current =1 IiH –5 5 µA Low input current =0 IiL –5 5 µA Standby Control (Pins 6, 45 and 46) Power Up PU_REG = 1 PU_RX/TX = 1 PU_PLL = 1 High input level Standby PU_REG = 0 PU_RX/TX = 0 PU_PLL = 0 Low input level Pin 6 Pin 45 Pin 46 VPU_REG VPU_RX/TX VPU_PLL Pin 6 Pin 45 Pin 46 VPU_REG,OFF VPU_RX/TX,OFF VPU_PLL,OFF 2.0 V 0.7 V Power Up PU_REG = 1 PU_RX/TX = 1 VPU = 3V, pin 6 VPU = 4.6V, pin 45 PU_PLL = 1 High input current VPU = 3V, pin 46 VPU = 4.6V Standby PU_xxxx = 0 Low input current VPU = 0V, pin 6 VPU = 0.5V, pins 45, 46 Settling Time VS = 0 → active operation Switched from VS = 0 to VS = 3V tsoa < 10 µs Settling Time standby → active operation Switched from PU = 0 to PU = 1 tssa < 10 µs Settling Time active operation → standby Switched from PU = 1 to standby tsas <2 µs RX IS 85 mA RSSI only IS 82 mA TX IS 54 mA TX (GF active) IS 56 mA Standby current PU_RX/TX = GND IS Supply current CP VVS_CP = 3V, PLL in lock condition, Pin 13 ICP IPU_REG IPU_RX/TX IPU_PLL 20 60 30 80 40 100 µA µA 100 200 125 300 150 400 µA µA 0.1 1 µA µA IPU,OFF Power Supply (Pins 7, 10, 12, 14, 33 and 42) Total supply current 10 1 µA µA 25 4572I–DECT–07/05 Figure 12-1. Typical Application Circuit RAMP_OUT TX_OUT RF_IN 47 pF 180 nH 100 nH SAW 47 pF Filter TFS 112B 18 pF 27 pF RSSI RSSI 25 IF_TANK1 26 GND2 28 RF_IN1 29 GND3 31 RF_IN2 30 VS_IF 33 IF_TANK2 27 56 pF TX_OUT 32 27 pF IF_IN1 34 RAMP_OUT 36 150 nH IF_IN2 35 68 pF BB_OUT 24 37 RAMP_SET RX_ON 38 RX_ON BB_CF 23 TX_ON 39 TX_ON REG_DEC 22 40 MIXER_OUT1 DAC_DEC 21 41 MIXER_OUT2 DEMOD_TANK2 20 T2803 42 VS_MIXER GND1 18 12 VS_CP 11 GND_CP 10 VS_REG 9 REG_CTRL 8 VREG VS_VCO 14 7 VS_PLL 48 I_CPSW 6 PU_REG 47 TX_DATA I_CPSW TBD 22 nF GND_VCO 16 5 LD TX_DATA TBD VREG_VCO 15 4 REF_CLOCK 46 PU_PLL 3 ENABLE 45 PU_RX/TX PU_PLL 2 DATA PU_RX/TX 100 pF VTUNE 17 1 CLOCK 44 OLE 2.2 nF DEMOD_TANK1 19 43 GND_PLL OLE BB_OUT 68 pF 180 Ω 150 nF CP 13 56 pF 470 nF CLOCK DATA ENABLE 220 pF REF_CLK LD 4.7 nF PU_REG VCC BC808 or similar tantal 26 tantal T2803 4572I–DECT–07/05 T2803 13. Ordering Information Extended Type Number Package Remarks MOQ QFN48 Taped and reeled 4000 pcs. QFN48, Pb-free, halogen-free Taped and reeled 4000 pcs. T2803-PLQ T2803-PLQW 14. Package Information 27 4572I–DECT–07/05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2005. All rights reserved. Atmel ®, logo and combinations thereof, Everywhere You Are ® and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Printed on recycled paper. 4572I–DECT–07/05