U2782B 1100 MHz Twin PLL Description The IC U2782B is a low power twin PLL manufactured with TEMIC’s advanced UHF process. The maximum operating frequency is 1100 MHz for both PLLs. It features a wide supply voltage range from 2.7 to 5.5 V. Prescaler 64/65 and power down function for both PLL’s is integrated. Applications are CT1, IS54, JDC etc. Electrostatic sensitive device. Observe precautions for handling. Features Benefits D Very low current consumption (typical 3 V/11 mA) D Low current consumption leads to extended talk time D Twin PLL saves costs and space D One foot print for all TEMIC twin PLL’s saves design- D Supply voltage range 2.7 to 5.5 V D Maximum input frequency: 1100 for both PLLs in time D 2 pins for separate power down functions D Output for PLL lock status D Prescaler 64/65 for both inputs D SSO20 package D ESD protected according to MIL-STD 833 method 3015 cl.2 Block Diagram 1 VS analog VS digital 6 AGND 15 OSCo Ports 2 DGND OSCi 9 4 Power down Test 7 8 Oscillator 20 Control functions Clock Data Enable 5 64 / 65 Prescaler 1 11 3 bit 10 HPD1/Port1 HPD2/Port4 Port3 Lock Port2 12 bit latch 1 12 bit reference divider 1 17 bit latch 1 RFi1 Lock select 16 bit latch on / off divide by 2 14 5I/Port 0 Phase detector 1 Charge pump 1 3 17 17 bit main divider 1 17 bit Shift register Pump bias 19 CP1 VScp Iset 12 13 Load control 12 bit latch 2 12 bit reference divider 2 17 bit latch 2 RFi2 16 64 / 65 Prescaler 2 17 bit main divider 2 Phase detector 2 Charge pump 2 18 CP2 94 8916 Figure 1. TELEFUNKEN Semiconductors Rev. A4, 17-Oct-97 1 (10) U2782B Ordering Information Extended Type Number U2782B-AFS U2782B-AFSG3 Package SSO20 SSO20 Pin Description Remarks Rail, MOQ 830 PCS Tape and Reel, MOQ 4000 pcs Pin 1 2 3 5I/Port 0 1 20 Port 3 VS digital 2 19 Iset CP 1 3 18 CP 2 VS analog 4 17 VScp 4 5 6 7 8 9 RFi 1 5 16 RFi 2 10 GNDD 6 15 GNDA OSCi 7 14 HPD2/Port 4 11 12 13 14 OSCo 8 13 Enable HPD1/Port 1 9 12 Data Lock/Port 2 10 15 16 17 18 11 Clock 19 95 9622 20 Symbol Function 5I/Port 0 5I – Control input / o.c.output VS digital Power supply digital section CP 1 Charge pump output of synthesizer 1 VS analog Power supply analog section RFi 1 RF divider input synthesizer GNDD Ground for digital section OSCi Reference oscillator input OSCo Reference oscillator output HPD 1/ Hardware power down input of Port 1 synthesizer 1 / o.c.output Lock/ Lock output / o.c.output / Port 2 testmode output Clock 3-wire-bus: serial clock input Data 3-wire-bus: serial data input Enable 3-wire-bus: serial enable input HPD 2/ Hardware power down input of Port 4 synthesizer 2 / o.c.output GNDA Ground for analog section RFi 2 RF divider input synthesizer 2 VScp Charge pump supply voltage CP 2 Charge pump output of synthesizer 2 Iset Reference pin for charge pump currents Port 3 o.c.output Absolute Maximum Ratings Supply voltage Input voltage Parameters Pins 2, 4 and 17 Pins 1, 3, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18 and 20 Junction temperature Storage temperature range Symbol VS, VScp Vi Value 6 0 to VS Unit V V Tj Tstg 125 – 40 to + 125 °C °C Symbol VS, VScp Tamb Value 2.7 to 5.5 – 40 to + 85 Unit V °C Operating Range Parameters Supply voltage Pins 2, 4 and 17 Ambient temperature range 2 (10) TELEFUNKEN Semiconductors Rev. A4, 17-Oct-97 U2782B Thermal Resistance Junction ambient Parameters SSO20 Symbol Rthja Value 140 Unit K/W Electrical Characteristics Tamb = 25_C, VS = 2.7 to 5.5 V, VScp = 5 V, unless otherwise specified ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Parameters DC Supply Supply current Supply current Supply current CP PLL 1 + PLL2 Input voltage Scaling factor prescaler Scaling factor main counter Scaling factor swallow counter Reference counter Reference oscillator Recommended crystal series resistance External reference input frequency Test conditions Symbol Min. Typ. Max. Unit VS = 3V, SPD1 = SPD2 = 0 VS = 3V, SPD1 = SPD2 = 1 VCP = 5 V, PLL in lock condition IS IS ICP 0.5 7 0 0.8 11 1 1.1 13 10 mA mA µA VRFi1 SPSC SM 20 200 mVRMS 5 2047 SS 0 63 SR 5 4096 10 200 1 1 20 40 fRFi1 = 200 – 1100 MHz AC coupled sinewave RF/2 = 0 RF/2 = 1 AC coupled sinewave x 1) RMS voltage at 50 W; x 2) W OSCi 2) External reference input OSCi amplitude Logic input levels (Clock, Data, Enable, HPD1, HPD2, 5I) High input level ViH Low input level ViL High input current IiH Low input current IiL Logic output levels (Port 0, 1, 2, 3, 4, Lock) Leakage current VOH = 5.5 V IL Saturation voltage IOL = 0.5 mA VSL Charge pump output (Rset = tbd.) Source current VCP VScp/2 PLL2 5I = L PLL1 Isource 5I = H PLL1 Sink current VCP VScp/2 PLL2 5I = L PLL1 Isink 5I = H PLL1 Leakage current VCP VScp/2 IL x 64/65 100 1.5 0 –5 –5 mVRMS 0.4 5 5 10 0.4 –1 –0.2 –1 1 0.2 1 5 " MHz V V mA mA mA V mA mA nA OSCo is open if an external reference frequency is applied TELEFUNKEN Semiconductors Rev. A4, 17-Oct-97 3 (10) U2782B Serial Bus Programming Reference and programmable counters can be programmed by the 3-wire-bus (Clock, Data and Enable). After setting enable signal to high condition, the data status is transfered but by but on the rising edge of the clock signal into the shift register, starting with the MSB-bit. After the Enable signal returns to low condition the programmed information is loaded according to the addressbits (last three bits) into the addressed latch. Additional leading bits are ignored and there is no check made how many clock pulses arrived during enable high condition. In powerdown mode the 3-wire-bus remains active and the IC can be programmed. Data is entered with the most significant bit first. The leading bits deliver the divider or control information. The trailing three bits are the address field. There are six different addresses used. The trailing address bits are decoded upon the falling edge of the Enable signal. The internal Loadpulse is beginning with the falling edge of the Enable signal and ending with falling edge of the Clock signal. Therefore a minimum holdtime clockenable tHCE is required. Bit Allocation MSB Bit 1 LSB Bit 7 Bit 8 D16 D15 D14 D13 D12 D11 D10 D9 D8 PLL1 M10 PLL2 M10 Bit 2 M9 M9 Bit 3 M8 M8 Bit 4 M7 M7 Bit 5 M6 M6 Bit 6 Bit Bit 9 10 data bits Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Bit 16 Bit 17 Bit Bit Bit 18 19 20 address bits D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 M5 M4 M3 M2 M1 M0 S5 S4 S3 S2 S1 PLL1 S0 0 0 1 PLL1 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 PL1 R0 0 1 0 M5 M4 M3 M2 M1 M0 S5 S4 S3 S2 S1 PLL2 S0 0 1 1 P0 1 1 0 0 0 1 SP D1 1 1 0 PLL2 R11 RF/ 2 Test 5IP TRI 2 R10 R9 R8 R7 TRI PS2 PS1 H2P H1P 1 R6 LP B R5 LPA R4 P4 R3 P3 R2 P2 R1 P1 SP SP D 5I D 2 PLL2 R0 Scaling Factors S0 ... S5: These bits are setting the swallow counter SS. TS = S0*20 + S1*21 + ... + S4*24 + S5*25 allowed scalling factors for SS: 0 ... 63, TS < TM M0 ... M10: These bits are setting the main counter SM. TM = M0*20 + M1*21 + ... + M9*29 + M10*210 allowed scalling factors for SM: 5 ... 2047 SPGD: Total scalling factor of the programmable counter: SPGD = (64*SM) + SS Condition: SS < SM R0 ... R11: These bits are setting the reference counter SR. SR = R0*20 + ... + R10*210 + R11*211 allowed scalling factors for SR: 5 ... 4096 SRFD: Total scalling factor of the reference counter: RF/2 = 1: SRFD = 2 * SR RF/2 = 0: SRFD = SR 4 (10) TELEFUNKEN Semiconductors Rev. A4, 17-Oct-97 U2782B Serial Programming Bus Control Bits: P0 ... P4: o.c. output ports (1 = high impedance) LPA, LPB: selection of P2 output or locksignal LPA LPB function of pin 10 0 0 o.c. output P2 0 1 locksignal of synthesizer 2 1 0 locksignal of synthesizer 1 1 1 wiredor locksignal of both synthesizer H1P, H2P: selection of P1/4 output or hardware power down input of synthesizer 1/2 (0 = Port / 1 = HPD) 5IP: selection of P0 output or high current switching input for the charge pump current of synthesizer 1 (0 = Port / 1 = charge pump 1 current switch input) PS1, PS2: phase selection of synthesizer 1 and synthesizer 2 (1 = normal / 0 = invers) PS-PLL1/2 = 1 CP1/2 Isink Isource 0 fR > fP fR < fP fR = fP PS-PLL1/2 = 0 CP1/2 Isource Isink 0 RF/2: divide by 2 prescaler for reference divider (0 = off / 1 = on) SPD1, SPD2: software power down bit of synthesizer 1/2 (0 = powerdown / 1 = powerup) 5I: software switch for the charge pump current of synthesizer 1 (0 = low current / 1 = high current) TRI1, TRI2: enables tristate for the charge pump of synthesizer 1/2 (0 = normal / 1 = tristate) TEST: enables counter testmode (0 = disabled / 1 = enabled) TEST LPA LPB PS1 PS2 1 1 1 1 1 1 0 0 0 0 1 1 1 0 x x x x 1 0 Testsignal at pin 10 RFD1 PGD1 RFD2 PGD2 To operate the software power down mode the following condition must be set: HXP = 0; power up and power down will be set by SPDX = 1 (on) and SPDX = 0 (off). To operate the hardware power down mode the following condition must be set: HXP = 1; SPDX = 1; power up and power down will be set by high and low state at the hardware power down pins 9/14. High current of charge pump synthesizer 1 is active when 5I = 1 and if 5IP = 1 the charge pump current control input pin 1 is in high state. TELEFUNKEN Semiconductors Rev. A4, 17-Oct-97 5 (10) 6 (10) 47u 12 51 CRYSTAL OSC. INPUT RF1 VS VS VCO 10n VCO1 10n 10n 10n C1 18 12 18 18 51 C2 R1 47u 10n 10n 10n R 51 18 18 18 C2 10n 10n R1 LOCK / PORT2 / TEST CLOCK DATA ENABLE HPD1 / PORT1 HPD2 / PORT4 P3 5I / P0 C1 94 9621 VCO2 47u 10n 12 10n RF2 47u VScp 12 U2782B Application Circuit Figure 2. TELEFUNKEN Semiconductors Rev. A4, 17-Oct-97 U2782B Timing Diagram Serial Bus Data Clock Enable tEL tSEC tCH tCL tSDC tHDC tHCE tHEC Internal Loadpulse 96 11828 Clock High Time Clock Low Time Clock Period Set up Time Clock Data to Clock Hold Time Data to Clock Hold Time Clock to Enable Hold Time Enable to Clock Enable Low Time Set up Time Enable to Clock tCH tCL tPER tSDC tHDC tHCE tHEC tEL tSEC >750 >350 >1100 >100 >400 >400 >400 >200 >4000 4.0 ns ns ns ns ns ns ns ns ns 1000 3.5 1m Veff on 50W Icp / mA 3.0 2.5 5I=1 2.0 1.5 100 Guaranteed Area 10 1.0 0.5 0 3000 96 11679 1 30000 R19/ W 300000 Figure 3. Charge pump characteristics TELEFUNKEN Semiconductors Rev. A4, 17-Oct-97 0 96 11680 200 400 600 800 1000 1200 Frequency/ MHz Figure 4. Input sensitivity of PLL1 and PLL2 7 (10) U2782B Input Impedence of PLL1 and PLL2 j 0.5j 2j 5j 0.2j ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ 0 0.2 0.5 1 Á Á 2 Á Á 1 5 100 MHz –0.2j –5j 500 MHz 1 GHz –0.5j –2j 1.5 GHz Z0 = 50 W 96 11686 –j 8 (10) TELEFUNKEN Semiconductors Rev. A4, 17-Oct-97 U2782B Package Information Package SSO20 5.7 5.3 Dimensions in mm 6.75 6.50 4.5 4.3 1.30 0.15 0.15 0.05 0.25 6.6 6.3 0.65 5.85 20 11 technical drawings according to DIN specifications 13007 1 TELEFUNKEN Semiconductors Rev. A4, 17-Oct-97 10 9 (10) U2782B Ozone Depleting Substances Policy Statement It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2831, Fax number: 49 ( 0 ) 7131 67 2423 10 (10) TELEFUNKEN Semiconductors Rev. A4, 17-Oct-97