Features • • • • • • • • • • • • • • • • • Operating Range from 5V to 27V Baud Rate up to 20Kbaud Improved Slew Rate Control According to LIN Specification 2.0, 2.1 and SAEJ2602-2 Fully Compatible with 3.3V and 5V Devices Atmel ATA6663: TXD Time-out Timer, Atmel ATA6664: No TXD Time-out Timer Normal and Sleep Mode Wake-up Capability via LIN Bus (90µs Dominant) External Wake-up via WAKE Pin (35µs Low Level) INH Output to Control an External Voltage Regulator or to Switch the Master Pull-up Very Low Standby Current During Sleep Mode (10µA) Wake-up Source Recognition Bus Pin Short-circuit Protected versus GND and Battery LIN Input Current < 2µA if VBAT Is Disconnected Overtemperature Protection High EMC Level Interference and Damage Protection According to ISO/CD 7637 Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications Rev.1.1” LIN Transceiver Atmel ATA6663 Atmel ATA6664 1. Description The Atmel ATA6663 is a fully integrated LIN transceiver complying with the LIN specification 2.0, 2.1 and SAEJ2602-2. The Atmel ATA6664 is an identical version, the only difference is that the TXD-dominant Time-out function is disabled so the device is able to send a static low signal to the LIN bus. It interfaces the LIN protocol handler and the physical layer. The device is designed to handle the low-speed data communication in vehicles, for example, in convenience electronics. Improved slope control at the LIN bus ensures secure data communication at up to 20Kbaud with an RC oscillator for protocol handling. Sleep Mode guarantees minimal current consumption even in the case of a floating bus line or a short circuit on the LIN bus to GND. The ATA6663/ATA6664 feature advanced EMI and ESD performance. 9146D–AUTO–09/10 Figure 1-1. Block Diagram 7 VS 6 LIN Receiver RXD 1 Filter Short-circuit and overtemperature protection Wake-up bus timer TXD TXD time-out timer 4 Slew rate control (only ATA6663) VS VS Control unit WAKE Wake-up timer 3 5 Sleep mode 2 GND 8 EN INH 2. Pin Configuration Figure 2-1. Pinning SO8 RXD EN WAKE TXD Table 2-1. 8 7 6 5 INH VS LIN GND Pin Description Pin Symbol 1 RXD 2 EN Enables normal mode; when the input is open or low, the device is in sleep mode 3 WAKE High voltage input for local wake-up request. If not needed, connect directly to VS 4 TXD Transmit data input; active low output (strong pull-down) after a local wake-up request 5 GND Ground, heat sink 6 LIN 7 VS Battery supply INH Battery-related inhibit output for controlling an external voltage regulator or to switch-off the LIN master pull-up resistor; active high after a wake-up request 8 2 1 2 3 4 Function Receive data output (open drain) LIN bus line input/output Atmel ATA6663/ATA6664 9146D–AUTO–09/10 Atmel ATA6663/ATA6664 3. Functional Description 3.1 Physical Layer Compatibility Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical layer according to LIN2.x can be used along with LIN physical layer nodes, which are according to older versions (i.e., LIN1.0, LIN1.1, LIN1.2, LIN1.3), without any restrictions. 3.2 Supply Pin (VS) Undervoltage detection is implemented to disable transmission if VS falls to a value below 5V in order to avoid false bus messages. After switching on VS, the IC switches to fail-safe mode and INHIBIT is switched on. The supply current in sleep mode is typically 10µA. 3.3 Ground Pin (GND) The Atmel ATA6663/ATA6664 does not affect the LIN Bus in the case of a GND disconnection. It is able to handle a ground shift up to 11.5% of VS. 3.4 Bus Pin (LIN) A low-side driver with internal current limitation and thermal shutdown, and an internal pull-up resistor are implemented as specified by LIN2.x. The voltage range is from –27V to +40V. This pin exhibits no reverse current from the LIN bus to VS, even in the case of a GND shift or VBatt disconnection. The LIN receiver thresholds are compatible to the LIN protocol specification.The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope controlled. The output has a self-adapting short-circuit limitation: During current limitation, as the chip temperature increases, the current is reduced. Note: 3.5 The internal pull-up resistor is only active in normal and fail-safe mode. Input/Output Pin (TXD) In Normal Mode the TXD pin is the microcontroller interface to control the state of the LIN output. TXD must be at Low- level in order to have a low LIN Bus. If TXD is high, the LIN output transistor is turned off and the Bus is in recessive state. The TXD pin is compatible to both a 3.3V or 5V supply. During fail-safe Mode, this pin is used as output and is signalling the wakeup source (see Section 3.14 “Wake-up Source Recognition” on page 8). It is current limited to < 8mA. 3.6 TXD Dominant Time-out Function (only Atmel ATA6663) The TXD input has an internal pull-down resistor. An internal timer prevents the bus line from being driven permanently in dominant state. If TXD is forced to low longer than tDOM > 40ms, the pin LIN will be switched off (recessive mode). To reset this mode, TXD needs to be switched to high (> 10µs) before switching LIN to dominant again. Note: The ATA6664 does not provide this functionality. 3 9146D–AUTO–09/10 3.7 Output Pin (RXD) This pin forwards information on the state of the LIN bus to the microcontroller. LIN high (recessive) is indicated by a high level at RXD, LIN low (dominant) is reported by a low voltage at RXD. The output is an open drain, therefore, it is compatible to a 3.3V or 5V power supply. The AC characteristics are defined by a pull-up resistor of 5kΩ to 5V and a load capacitor of 20pF. The output is short-current protected. In unpowered mode (VS = 0V), RXD is switched off. For ESD protection a Zener diode with VZ = 6.1V is integrated. 3.8 Enable Input Pin (EN) This pin controls the operation mode of the device. If EN = 1, the device is in normal mode, with the transmission path from TXD to LIN and from LIN to RXD both active. At a falling edge on EN, while TXD is already set to high, the device switches to sleep mode and transmission is not possible. In sleep mode, the LIN bus pin is connected to VS with a weak pull-up current source. The device can transmit only after being woken up (see Section 3.9, “Inhibit Output Pin (INH)” ). During sleep mode the device is still supplied from the battery voltage. The supply current is typically 10µA. The pin EN provides a pull-down resistor in order to force the transceiver into sleep mode in case the pin is disconnected. 3.9 Inhibit Output Pin (INH) This pin is used to control an external voltage regulator or to switch on/off the LIN Master pull-up resistor in case the device is used in a Master node. The inhibit pin provides an internal switch towards pin VS which is protected by temperature monitoring. If the device is in normal or fail-safe mode, the inhibit high-side switch is turned on. When the device is in sleep mode, the inhibit switch is turned off, thus disabling the voltage regulator or other connected external devices. A wake-up event on the LIN bus or at pin WAKE will switch the INH pin to the VS level. After a system power-up (VS rises from zero), the pin INH switches automatically to the VS level. 3.10 Wake-up Input Pin (WAKE) This pin is a high-voltage input used to wake-up the device from sleep mode. It is usually connected to an external switch in the application to generate a local wake-up. A pull-up current source with typically –10µA is implemented. The voltage threshold for a wake-up signal is 3V below the VS voltage with an output current of typically –3µA. If a local wake-up is not needed in the application, pin WAKE can directly be connected to pin VS. 4 Atmel ATA6663/ATA6664 9146D–AUTO–09/10 Atmel ATA6663/ATA6664 3.11 Operation Modes 1. Normal Mode This is the normal transmitting and receiving mode. All features are available. 2. Sleep Mode In this mode the transmission path is disabled and the device is in low-power mode. Supply current from VBatt is typically 10µA. A wake-up signal from the LIN bus or via pin WAKE will be detected and will switch the device to fail-safe mode. If EN then switches to high, normal mode is activated. Input debounce timers at pin WAKE (tWAKE), LIN (tBUS) and EN (tsleep,tnom) prevent unwanted wake-up events due to automotive transients or EMI. In sleep mode the INH pin remains floating. The internal termination between pin LIN and pin VS is disabled. Only a weak pull-up current (typical 10 µA) between pin LIN and pin VS is present. Sleep mode can be activated independently from the actual level on pin LIN or WAKE. 3. Fail-safe Mode At system power-up or after a wake-up event, the device automatically switches to fail-safe mode. It switches the INH pin to a high state, to the VS level when VS exceeds 5V. LIN communication is switched off. The microcontroller of the application will then confirm normal mode by setting the EN pin to high. Figure 3-1. Mode of Operation Power-up a a: Power-up (VS > 3V) b: VS < 5V c: Bus wake-up event d: Wake-up from wake switch Fail-safe Mode Communication: OFF RXD: see table of Modes INH: high (INH HS switch ON) if VS > 5V b EN = 1 & NOT b b c or d Go to sleep command EN = 0 Normal Mode INH: high (INH HS switch ON) Communication: ON Table 3-1. Local wake-up event EN = 1 Sleep Mode INH: high impedance (INH HS switch OFF) Communication: OFF Table of Operation Modes Mode of Operation Transceiver Fail-safe Off Normal Sleep On Off INH On, except VS < 5V On Off RXD High, except after wake-up LIN depending High ohmic LIN Recessive TXD depending Recessive Wake-up events from sleep mode: • LIN bus • EN pin • WAKE pin • VS undervoltage Figure 3-1 on page 5, Figure 3-2 on page 6 and Figure 3-5 on page 8 show the details of wake-up operations. 5 9146D–AUTO–09/10 3.12 Remote Wake-up via Dominant Bus State A voltage lower than the LIN pre-wake detection VLINL at pin LIN activates the internal LIN receiver and starts the wake-up detection timer. A falling edge at pin LIN, followed by a dominant bus level VBUSdom maintained for a certain time period (tBUS) and a rising edge at pin LIN results in a remote wake-up request. The device switches to fail-safe mode. Pin INH is activated (switches to VS) and the internal termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller (see Figure 3-2). Figure 3-2. LIN Wake-up Waveform Diagram Bus wake-up filtering time (tBUS) LIN bus High INH Low or floating RXD High or floating Low External voltage regulator Off state Regulator wake-up time delay Normal Mode EN High EN Node in sleep state Microcontroller start-up delay time In sleep mode the device has a very low current consumption, even during short-circuits or floating conditions on the bus. A floating bus can arise if the Master pull-up resistor is missing, e.g., in case it is switched off when the LIN Master is in sleep mode or if the power supply of the Master node is switched off. To minimize the current consumption IVS during voltage levels at the LIN-pin below the LIN pre-wake threshold, the receiver is activated only for a specific time tmon. If tmon elapses while the voltage at the bus is lower than pre-wake detection low (VLINL) and higher than the LIN dominant level, the receiver is switched off again and the circuit reverts to sleep mode. The current consumption is then the result of IVSsleep plus ILINwake. If a dominant state is reached on the bus no wake-up will occur. Even if the voltage exceeds the pre-wake detection high (VLINH), the IC will remain in sleep mode (see Figure 3-3 on page 7). This means the LIN bus must be above the Pre-wake detection threshold VLINH for a few microseconds before a new LIN wake-up is possible. 6 Atmel ATA6663/ATA6664 9146D–AUTO–09/10 Atmel ATA6663/ATA6664 Figure 3-3. Floating LIN Bus During Sleep Mode LIN Pre-wake VLINL LIN BUS LIN dominant state VBUSdom tmon IVSsleep + ILINwake IVSfail IVS IVSsleep Mode of operation Sleep Mode Int. Pull-up Resistor RLIN IVSsleep Wake-up Detection Phase Sleep Mode off (disabled) If the Atmel® ATA6663/ATA6664 is in sleep mode and the voltage level at the LIN is in dominant state (VLIN < VBUSdom) for a time period exceeding tmon (during a short circuit at LIN, for example), the IC switches back to sleep mode. The VS current consumption then consists of IVSsleep plus ILINWAKE. After a positive edge at pin LIN the IC switches directly to fail-safe mode (see Figure 3-4). Figure 3-4. Short Circuit to GND on the LIN Bus During Sleep Mode LIN Pre-wake LIN BUS VLINL LIN dominant state VBUSdom tmon tmon IVSfail IVS Mode of operation Int. Pull-up Resistor RLIN IVSsleep Sleep Mode Wake-up Detection Phase off (disabled) IVSsleep + ILINwake Sleep Mode Fail-Safe Mode on (enabled) 7 9146D–AUTO–09/10 3.13 Local Wake-up via Pin WAKE A falling edge at pin WAKE, followed by a low level maintained for a certain time period (tWAKE), results in a local wake-up request. According to ISO7637, the wake-up time ensures that no transient creates a wake-up. The device then switches to fail-safe mode. Pin INH is activated (switches to V S ) and the internal termination resistor is switched on. The local wake-up request is indicated both by a low level at pin RXD to interrupt the microcontroller and by a strong pull-down at pin TXD (see Figure 3-5). The voltage threshold for a wake-up signal is 3V below the VS voltage with an output current of typically –3µA. Even in case of a continuous low at pin WAKE it is possible to switch the IC into sleep mode via a low level at pin EN. The IC will remain in sleep mode for an unlimited time. To generate a new wake-up at pin WAKE, a high signal > 6 µs is required. A negative edge then starts the wake-up filtering time again. Figure 3-5. Wake-up from Wake-up Switch State change Wake pin INH Low or floating RXD High or floating TXD TXD weak pull-down resistor High Low High TXD strong pull-down Weak pull-down Wake filtering time tWAKE Voltage regulator On state Off state Regulator wake-up time delay EN Node in operation EN High Node in sleep state Microcontroller start-up delay time 3.14 Wake-up Source Recognition The device can distinguish between a local wake-up request (pin WAKE) and a remote wake-up request (LIN bus). The wake-up source can be read at pin TXD in fail-safe mode. If an external pull-up resistor (typically 5kΩ) has been added on pin TXD to the power supply of the microcontroller, a high level indicates a remote wake-up request (weak pull-down at pin TXD), a low level indicates a local wake-up request (strong pull-down at pin TXD). The wake-up request flag (indicated at pin RXD) as well as the wake-up source flag (indicated at pin TXD) are reset immediately if the microcontroller sets pin EN to high (see Figure 3-2 on page 6 and Figure 3-5 on page 8). 8 Atmel ATA6663/ATA6664 9146D–AUTO–09/10 Atmel ATA6663/ATA6664 3.15 Fail-safe Features • During a short-circuit at LIN to VBAT, the output limits the output current to IBUS_LIM. Due to the power dissipation, the chip temperature exceeds Toff, and the LIN output is switched off. The chip cools down, and after a hysteresis of Thys, it switches the output on again. • During a short-circuit from LIN to GND the IC can be switched to sleep mode, and even in this case the current consumption is lower than 45µA. When the short-circuit has elapsed, the IC starts with a remote wake-up. • If the Atmel® ATA6663/ATA6664 is in sleep mode and a floating condition occurs on the bus, the IC switches back to sleep mode automatically. The current consumption is lower than 45µA in this case. • The reverse current is < 2µA at pin LIN during loss of VBAT. This is the best behavior for bus systems where some slave nodes are supplied from battery or ignition. • Pin EN provides a pull-down resistor to force the transceiver into sleep mode if EN is disconnected • Pin RXD is set floating if VBAT is disconnected • Pin TXD provides a pull-down resistor to provide a static low if TXD is disconnected • The INH output transistor is protected by temperature monitoring 9 9146D–AUTO–09/10 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Max. Unit –0.3 +40 V Wake DC and transient voltage (with 2.7kΩ serial resistor) - Transient voltage according to ISO7637 (coupling 1nF) –3 –150 +40 +100 V V Logic pins (RXD, TXD, EN) –0.3 +5.5 V LIN - DC voltage - Transient voltage according to ISO7637 (coupling 1nF) –27 –150 +40 +100 V V INH - DC voltage –0.3 VS + 0.3 V VS - Continuous supply voltage Symbol ESD according to IBEE LIN EMC Test specification 1.0 according to IEC 61000-4-2 - Pin VS, LIN to GND - Pin WAKE (2.7kΩ serial resistor) Min. Typ. ±8 ±6 KV KV ±6 KV ±3 KV CDM ESD STM 5.3.1 ±750 V Machine Model ESD AEC-Q100-Rev.F (003) ±200 V ESD HBM according to STM5.1 with 1.5kΩ / 100pF - Pin VS, LIN, WAKE, INH to GND HBM ESD ANSI/ESD-STM5.1 JESD22-A114 AEC-Q100 (002) Junction temperature Tj –40 +150 °C Storage temperature Tstg –55 +150 °C Symbol Min. Max. Unit 145 K/W 5. Thermal Characteristics Parameters Thermal resistance junction ambient RthJA Special heat sink at GND (pin 5) on PCB (fused lead frame to pin 5) RthJA Typ. 80 K/W Thermal shutdown Toff 150 165 180 °C Thermal shutdown hysteresis Thys 5 10 20 °C 10 Atmel ATA6663/ATA6664 9146D–AUTO–09/10 Atmel ATA6663/ATA6664 6. Electrical Characteristics 5V < VS < 27V, Tj = –40°C to +150°C No. 1 1.1 1.2 Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 5 13.5 27 V A VS Pin DC voltage range nominal Supply current in sleep mode 1.3 Supply current in normal mode 1.4 7 VS Sleep mode VLIN > VS – 0.5V VS < 14V 7 IVSsleep 10 20 µA A Sleep mode, bus shorted to GND VLIN = 0V VS < 14V 7 IVSsleep_sc 23 45 µA A Bus recessive VS < 14V 7 IVSrec 0.9 1.3 mA A Bus dominant VS < 14V Total bus load > 500Ω 7 IVSdom 1.2 2 mA A Bus recessive VS < 14V 7 IVSfail 0.5 1.1 mA A 1.5 Supply current in fail-safe mode 1.6 VS undervoltage threshold on 7 VSth 4 4.95 V A 1.7 VS undervoltage threshold off 7 VSth 4.05 5 V A 1.8 VS undervoltage threshold hysteresis 7 VSth_hys 50 500 mV A 1.3 8 mA A 0.4 V A 2 RXD Output Pin (Open Drain) 2.1 Low-level output sink current Normal mode VLIN = 0V, VRXD = 0.4V 1 IRXDL 2.2 RXD saturation voltage 5-kΩ pull-up resistor to 5V 1 VsatRXD 2.3 High-level leakage current Normal mode VLIN = VBAT, VRXD = 5V 1 IRXDH –3 +3 µA A 2.4 ESD Zener diode IRXD = 100µA 1 VZRXD 5.8 8.6 V A 3 2.5 TXD Input Pin 3.1 Low-level voltage input 4 VTXDL –0.3 +0.8 V A 3.2 High-level voltage input 4 VTXDH 2 7 V A 600 kΩ A +3 µA A 8 mA A +0.8 V A 3.3 Pull-down resistor VTXD = 5V 4 RTXD 125 3.4 Low-level leakage current VTXD = 0V 4 ITXD_leak –3 3.5 Low-level output sink current Fail-safe mode, local wake-up VTXD = 0.4V VLIN = VBAT 4 ITXD 1.3 2 VENL –0.3 4 250 2.5 EN Input Pin 4.1 Low-level voltage input 4.2 High-level voltage input 2 VENH 2 4.3 Pull-down resistor VEN = 5V 2 REN 125 4.4 Low-level input current VEN = 0V 2 IEN –3 250 7 V A 600 kΩ A +3 µA A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 11 9146D–AUTO–09/10 6. Electrical Characteristics (Continued) 5V < VS < 27V, Tj = –40°C to +150°C No. 5 Parameters Test Conditions Pin Symbol Min. VS – 0.75 Typ. Max. Unit Type* VS V A 50 Ω A INH Output Pin 5.1 High-level voltage Normal or fail-safe mode IINH = –15mA 8 VINHH 5.2 Switch-on resistance between VS and INH Normal or fail-safe mode 8 RINH 5.3 Leakage current Sleep mode VINH = 0V/27V, VS = 27V 8 IINHL –3 +3 µA A 3 VWAKEH VS – 1V VS + 0.3V V A VS – 3.3V V A µA A 6 30 WAKE Pin 6.1 High-level input voltage 6.2 Low-level input voltage IWAKE = typically –3µA 3 VWAKEL –1V 6.3 Wake pull-up current VS < 27V 3 IWAKE –30 6.4 High-level leakage current VS = 27V, VWAKE = 27V 3 IWAKE –5 +5 µA A 0.9 × VS VS V A 7 –10 LIN Bus Driver 7.1 Driver recessive output voltage RLOAD = 500Ω / 1kΩ 6 VBUSrec 7.2 Driver dominant voltage VBUSdom_DRV_LoSUP VVS = 7V, Rload = 500Ω 6 V_LoSUP 1.2 V A 7.3 Driver dominant voltage VBUSdom_DRV_HiSUP VVS = 18V, Rload = 500Ω 6 V_HiSUP 2 V A 7.4 Driver dominant voltage VBUSdom_DRV_LoSUP VVS = 7V, Rload = 1000Ω 6 V_LoSUP_1k 0.6 V A 7.5 Driver dominant voltage VBUSdom_DRV_HiSUP VVS = 18V, Rload = 1000Ω 6 V_HiSUP_1k_ 0.8 V A 7.6 Pull-up resistor to VS The serial diode is mandatory 6 RLIN 20 47 kΩ A 7.7 In pull-up path with Rslave Voltage drop at the serial diodes ISerDiode = 10mA 6 VSerDiode 0.4 1.0 V D 7.8 LIN current limitation VBUS = VBAT_max 6 IBUS_LIM 40 200 mA A 7.9 Input leakage current at the receiver, including pull-up resistor as specified Input leakage current Driver off VBUS = 0V, VS = 12V 6 IBUS_PAS_dom –1 mA A 7.10 Leakage current LIN recessive Driver off 8V < VBAT < 18V 8V < VBUS < 18V VBUS ≥ VBAT 6 IBUS_PAS_rec 7.11 Leakage current at ground loss; control unit disconnected from GNDDevice = VS ground; loss of local ground must VBAT =12V not affect communication in the 0V < VBUS < 18V residual network 6 IBUS_NO_Gnd –10 30 120 10 20 µA A +0.5 +10 µA A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 12 Atmel ATA6663/ATA6664 9146D–AUTO–09/10 Atmel ATA6663/ATA6664 6. Electrical Characteristics (Continued) 5V < VS < 27V, Tj = –40°C to +150°C No. Parameters Pin Symbol 7.12 Leakage current at loss of battery; node has to substain the VBAT disconnected current that can flow under this VSUP_Device = GND condition; bus must remain 0V < VBUS < 18V operational under this condition 6 IBUS_NO_Bat 7.13 Capacitance on pin LIN to GND 6 CLIN 8 Test Conditions Min. Typ. Max. Unit Type* 0.1 2 µA A 20 pF D 0.525 × VS V A LIN Bus Receiver 8.1 Center of receiver threshold VBUS_CNT = (Vth_dom + Vth_rec) / 2 6 VBUS_CNT 0.475 × VS 8.2 Receiver dominant state VEN = 5V 6 VBUSdom –27 0.4 × VS V A 8.3 Receiver recessive state VEN = 5V 6 VBUSrec 0.6 × VS 40 V A 8.4 Receiver input hysteresis VHYS = Vth_rec – Vth_dom 6 VBUShys 0.028 × VS 0.175 × VS V A 8.5 Pre-wake detection LIN High-level input voltage 6 VLINH VS – 2V VS + 0.3V V A 8.6 Pre-wake detection LIN Low-level input voltage Switches the LIN receiver on 6 VLINL –27V VS – 3.3V V A 8.7 LIN Pre-wake pull-up current VS < 27V VLIN = 0V 6 ILINWAKE –30 –10 µA A 9 0.5 × VS 0.1 × VS Internal Timers 9.1 Dominant time for wake-up via LIN bus VLIN = 0V 6 tBUS 30 90 150 µs A 9.2 Time of low pulse for wake-up via pin WAKE VWAKE = 0V 3 tWAKE 7 35 50 µs A 9.3 Time delay for mode change from fail-safe mode to normal mode via pin EN VEN = 5V 2 tnorm 2 7 15 µs A 9.4 Time delay for mode change from normal mode into sleep mode via pin EN VEN = 0V 2 tsleep 7 15 24 µs A 9.5 Atmel ATA6663: TXD dominant time out time VTXD = 0V 4 tdom 40 60 85 ms A 9.6 Power-up delay between VS = 5V VVS = 5V until INH switches to high 7, 8 tVS 200 µs A 9.7 Monitoring time for wake-up via LIN bus 6 tmon 15 ms A 6 10 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 13 9146D–AUTO–09/10 6. Electrical Characteristics (Continued) 5V < VS < 27V, Tj = –40°C to +150°C No. Parameters 10 LIN Bus Driver AC Parameter with Different Bus Loads Load 1 (small): 1nF, 1kΩ ; Load 2 (large): 10nF, 500Ω ; RRXD = 5kΩ ; CRXD = 20pF; Load 3 (medium): 6.8nF, 660Ω characterized on samples; 10.1 and 10.2 specifies the timing parameters for proper operation at 20Kbit/s, 10.3 and 10.4 at 10.4Kbit/s. 10.1 10.2 10.3 10.4 11 Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Duty cycle 1 THRec(max) = 0.744 × VS THDom(max) = 0.581 × VS VS = 7.0V to 18V tBit = 50µs D1 = tbus_rec(min) / (2 × tBit) 6 D1 Duty cycle 2 THRec(min) = 0.422 × VS THDom(min) = 0.284 × VS VS = 7.0V to 18V tBit = 50µs D2 = tbus_rec(max) / (2 × tBit) 6 D2 Duty cycle 3 THRec(max) = 0.778 × VS THDom(max) = 0.616 × VS VS = 7.0V to 18V tBit = 96µs D3 = tbus_rec(min) / (2 × tBit) 6 D3 Duty cycle 4 THRec(min) = 0.389 × VS THDom(min) = 0.251 × VS VS = 7.0V to 18V tBit = 96µs D4 = tbus_rec(max) / (2 × tBit) 6 D4 0.590 6 µs A +2 µs A 0.396 A 0.581 A 0.417 A A Receiver Electrical AC Parameters of the LIN Physical Layer LIN receiver, RXD load conditions: CRXD = 20pF, Rpull-up = 5kΩ 11.1 Propagation delay of receiver (see Figure 6-1 on page 15) trec_pd = max(trx_pdr , trx_pdf) VS = 7.0V to 18V 1 trx_pd 11.2 Symmetry of receiver propagation delay rising edge minus falling edge trx_sym = trx_pdr – trx_pdf VS = 7.0V to 18V 1 trx_sym –2 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 14 Atmel ATA6663/ATA6664 9146D–AUTO–09/10 Atmel ATA6663/ATA6664 Figure 6-1. Definition of Bus Timing Parameter tBit tBit tBit TXD (Input to transmitting node) tBus_dom(max) tBus_rec(min) Thresholds of THRec(max) receiving node 1 VS (Transceiver supply of transmitting node) THDom(max) LIN Bus Signal Thresholds of THRec(min) receiving node 2 THDom(min) tBus_dom(min) tBus_rec(max) RXD (Output of receiving node 1) trx_pdr(1) trx_pdf(1) RXD (Output of receiving node 2) trx_pdr(2) trx_pdf(2) 15 9146D–AUTO–09/10 Figure 6-2. Application Circuit Master node pull-up VBAT 22 µF 100 nF 12V 1k 7 Atmel ATA6663/ATA6664 5 kΩ VDD VS Receiver 1 LIN sub bus 5V RXD Filter Microcontroller LIN Wake-up bus timer 4 TXD Time-out timer TXD 220 pF VS VS Control unit 10 kΩ 2.7 kΩ 16 Slew rate control Short-circuit and overtemperature protection (only ATA6663) GND IO External switch 6 3 WAKE Wake-up timer 5 Sleep mode GND 2 8 EN INH Atmel ATA6663/ATA6664 9146D–AUTO–09/10 Atmel ATA6663/ATA6664 7. Ordering Information Extended Type Number Package Remarks ATA6663-FAQW DFN8 LIN transceiver, Pb-free, 8k, taped and reeled ATA6663-TAQY SO8 LIN transceiver, Pb-free, 4k, taped and reeled ATA6664-TAQY SO8 LIN transceiver, Pb-free, 4k, taped and reeled 8. Package Information Figure 8-1. SO8 Package: SO 8 Dimensions in mm 5±0.2 4.9±0.1 0.1+0.15 1.4 0.2 3.7±0.1 0.4 1.27 3.8±0.1 6±0.2 3.81 8 5 technical drawings according to DIN specifications 1 4 Drawing-No.: 6.541-5031.01-4 Issue: 1; 15.08.06 17 9146D–AUTO–09/10 Figure 8-2. DFN8 Top View D 8 E PIN 1 ID technical drawings according to DIN specifications 1 A A3 A1 Dimensions in mm Side View Partially Plated Surface Bottom View 4 COMMON DIMENSIONS E2 1 Z (Unit of Measure = mm) Symbol MIN NOM MAX A 0.8 0.9 1 e A1 A3 0.0 0.15 0.02 0.2 0.05 0.25 D2 D 2.9 3 3.1 D2 2.35 2.4 2.45 E 2.9 3 3.1 E2 1.55 1.6 1.65 L 0.35 0.4 0.45 b e 0.25 0.28 0.65 BSC 0.35 8 5 L Z 10:1 NOTE b Package Drawing Contact: [email protected] 18 TITLE Package: VQFN_3x3_8L Exposed pad 2.4x1.6 03/03/10 DRAWING NO. REV. 6.543-5165.02-4 1 Atmel ATA6663/ATA6664 9146D–AUTO–09/10 Atmel ATA6663/ATA6664 9. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 9146D-AUTO-09/10 • Section 7 “Ordering Information” on page 17 changed • Section 8 “Package Information” on pages 17 to 18 changed 9146C-AUTO-07/10 • Section 6 “Electrical Characteristics” numbers 9.4 and 9.5 on page 13 changed 9146B-AUTO-05/10 • Features changed • Headings 3.6 and 3.10: text changed • Abs.Max.Ratings table: row “ESD HBM acc. to STM5.1” changed 19 9146D–AUTO–09/10 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 Atmel Asia Limited Unit 01-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 JAPAN Tel: (+81) (3) 3523-3551 Fax: (+81) (3) 3523-7581 © 2010 Atmel Corporation. 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