CY7C1012DV33 12-Mbit (512 K × 24) Static RAM Datasheet.pdf

CY7C1012DV33
12-Mbit (512 K × 24) Static RAM
12-Mbit (512 K × 24) Static RAM
Features
Functional Description
■
High speed
❐ tAA = 10 ns
The CY7C1012DV33 is a high performance CMOS static RAM
organized as 512K words by 24 bits. Each data byte is separately
controlled by the individual chip selects (CE1, CE2, and CE3).
CE1 controls the data on the I/O0–I/O7, while CE2 controls the
data on I/O8–I/O15, and CE3 controls the data on the data pins
I/O16–I/O23. This device has an automatic power down feature
that significantly reduces power consumption when deselected.
■
Low active power
❐ ICC = 175 mA at 10 ns
■
Low CMOS standby power
❐ ISB2 = 25 mA
■
Operating voltages of 3.3 ± 0.3 V
■
2.0 V data retention
■
Automatic power down when deselected
■
TTL compatible inputs and outputs
■
Available in Pb-free standard 119-ball PBGA
Writing the data bytes into the SRAM is accomplished when the
chip select controlling that byte is LOW and the write enable input
(WE) input is LOW. Data on the respective input and output (I/O)
pins is then written into the location specified on the address pins
(A0–A18). Asserting all of the chip selects LOW and write enable
LOW writes all 24 bits of data into the SRAM. Output enable (OE)
is ignored while in WRITE mode.
Data bytes are also individually read from the device. Reading a
byte is accomplished when the chip select controlling that byte
is LOW and write enable (WE) HIGH, while output enable (OE)
remains LOW. Under these conditions, the contents of the
memory location specified on the address pins appear on the
specified data input and output (I/O) pins. Asserting all the chip
selects LOW reads all 24 bits of data from the SRAM.
The 24 I/O pins (I/O0–I/O23) are placed in a high impedance state
when all the chip selects are HIGH or when the output enable
(OE) is HIGH during a READ mode. For more information, see
the Truth Table on page 10.
For a complete list of related documentation, click here.
Logic Block Diagram
512 K x 24
ARRAY
COLUMN
DECODER
I/O0 – I/O7
SENSE AMPS
A(9:0)
ROW DECODER
INPUT BUFFER
I/O8 – I/O15
I/O16 – I/O23
CONTROL LOGIC
CE1, CE2, CE3
WE
OE
A(18:10)
Cypress Semiconductor Corporation
Document Number: 38-05610 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 20, 2014
CY7C1012DV33
Contents
Selection Guide ................................................................ 3
Pin Configuration ............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics .......................................... 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
AC Switching Characteristics ......................................... 6
Data Retention Characteristics ....................................... 7
Data Retention Waveform ................................................ 7
Switching Waveforms ...................................................... 7
Truth Table ...................................................................... 10
Document Number: 38-05610 Rev. *G
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagram ............................................................ 12
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC Solutions ......................................................... 15
Page 2 of 15
CY7C1012DV33
Selection Guide
Description
-10
Unit
Maximum Access Time
10
ns
Maximum Operating Current
175
mA
Maximum CMOS Standby Current
25
mA
Pin Configuration
Figure 1. 119-ball PBGA (Top View) [1]
1
2
3
4
5
6
7
A
NC
A
A
A
A
A
NC
B
NC
A
A
CE1
A
A
NC
C
I/O12
NC
CE2
NC
CE3
NC
I/O0
D
I/O13
VDD
VSS
VSS
VSS
VDD
I/O1
E
I/O14
VSS
VDD
VSS
VDD
VSS
I/O2
F
I/O15
VDD
VSS
VSS
VSS
VDD
I/O3
G
I/O16
VSS
VDD
VSS
VDD
VSS
I/O4
H
I/O17
VDD
VSS
VSS
VSS
VDD
I/O5
J
NC
VSS
VDD
VSS
VDD
VSS
NC
K
I/O18
VDD
VSS
VSS
VSS
VDD
I/O6
L
I/O19
VSS
VDD
VSS
VDD
VSS
I/O7
M
I/O20
VDD
VSS
VSS
VSS
VDD
I/O8
N
I/O21
VSS
VDD
VSS
VDD
VSS
I/O9
P
I/O22
VDD
VSS
VSS
VSS
VDD
I/O10
R
I/O23
A
NC
NC
NC
A
I/O11
T
NC
A
A
WE
A
A
NC
U
NC
A
A
OE
A
A
NC
Note
1. NC pins are not connected on the die.
Document Number: 38-05610 Rev. *G
Page 3 of 15
CY7C1012DV33
Maximum Ratings
DC Input Voltage [2] ............................ –0.5 V to VCC + 0.5 V
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Current into Outputs (LOW) ........................................ 20 mA
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Supply Voltage on
VCC Relative to GND [2] ...............................–0.5 V to +4.6 V
Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Latch Up Current ................................................... > 200 mA
Operating Range
DC Voltage Applied to Outputs
in High Z State [2] ................................ –0.5 V to VCC + 0.5 V
Range
Ambient Temperature
VCC
Industrial
–40 C to +85 C
3.3 V  0.3 V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions [3]
VOH
Output HIGH voltage
Min VCC, IOH = –4.0 mA
VOL
Output LOW voltage
Min VCC, IOL = 8.0 mA
VIH
VIL[2]
-10
Min
Max
Unit
2.4
–
V
–
0.4
V
Input HIGH voltage
2.0
VCC + 0.3
V
Input LOW voltage
–0.3
0.8
V
IIX
Input leakage current
GND < VIN < VCC
–1
+1
A
IOZ
Output leakage current
GND < VOUT < VCC, output disabled
–1
+1
A
ICC
VCC operating supply current
VCC = Max, f = fMAX = 1/tRC, IOUT = 0 mA,
CMOS levels
–
175
mA
ISB1
Automatic CE power-down
current – TTL inputs
Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX
–
30
mA
ISB2
Automatic CE power-down
current – CMOS inputs
Max VCC, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V, f = 0
–
25
mA
Notes
2. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
3. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 or CE2 , or CE3 is LOW. When HIGH, CE indicates the CE1 , CE2 , and
CE3 are HIGH.
Document Number: 38-05610 Rev. *G
Page 4 of 15
CY7C1012DV33
Capacitance
Parameter [4]
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 3.3 V
Max
Unit
8
pF
10
pF
Thermal Resistance
Parameter [4]
Description
JA
Thermal Resistance
(junction to ambient)
JC
Thermal Resistance
(junction to case)
Test Conditions
119-ball PBGA Unit
Still air, soldered on a 3 × 4.5 inch, four layer printed circuit
board
20.31
C/W
8.35
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [5]
50
OUTPUT
Z0 = 50
R1 317 
3.3V
VTH = 1.5V
OUTPUT
30 pF*
R2
351
5 pF*
*Including jig
and scope
(a)
(b)
*Capacitive Load consists of all
components of the test environment
3.0V
GND
All input pulses
90%
10%
90%
10%
Fall Time:> 1 V/ns
Rise Time > 1 V/ns
(c)
Notes
4. Tested initially and after any design or process changes that may affect these parameters.
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0 V). 100 s (tpower) after reaching the minimum operating
VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0 V) voltage.
Document Number: 38-05610 Rev. *G
Page 5 of 15
CY7C1012DV33
AC Switching Characteristics
Over the Operating Range
Parameter [6]
Description
-10
Min
Max
–
Unit
Read Cycle
tpower [7]
VCC(typical) to the first access
100
s
tRC
Read cycle time
10
–
ns
tAA
Address to data valid
–
10
ns
tOHA
Data hold from address change
3
–
ns
–
10
ns
[8]
tACE
CE active LOW to data valid
tDOE
OE LOW to data valid
–
5
ns
tLZOE
OE LOW to low Z [9]
1
–
ns
tHZOE
OE HIGH to high Z [9]
–
5
ns
3
–
ns
–
5
ns
0
–
ns
–
10
ns
tLZCE
CE active LOW to low Z
[8, 9]
[8, 9]
tHZCE
CE deselect HIGH to high Z
tPU
CE active LOW to power up [8, 10]
tPD
Write Cycle
CE deselect HIGH to power down
[8, 10]
[11, 12]
tWC
Write cycle time
10
–
ns
tSCE
CE active LOW to write end [8]
7
–
ns
tAW
Address setup to write end
7
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
7
–
ns
tSD
Data Setup to write end
5.5
–
ns
tHD
Data Hold from write end
0
–
ns
tLZWE
WE HIGH to low Z
[9]
3
–
ns
tHZWE
WE LOW to high Z [9]
–
5
ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use
output loading as shown in part (a) of Figure 2 on page 5, unless specified otherwise.
7. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
8. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 or CE2 , or CE3 is LOW. When HIGH, CE indicates the CE1 , CE2 , and
CE3 are HIGH.
9. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in part (b) of Figure 2 on page 5. Transition is measured 200 mV from
steady state voltage.
10. These parameters are guaranteed by design and are not tested.
11. The internal write time of the memory is defined by the overlap of CE1 or CE2 or CE3 LOW and WE LOW. Chip enables must be active and WE must be LOW to initiate
a write. The transition of any of these signals terminate the write. The input data setup and hold timing are referenced to the leading edge of the signal that terminates
the write.
12. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 38-05610 Rev. *G
Page 6 of 15
CY7C1012DV33
Data Retention Characteristics
Over the Operating Range
Parameter
Conditions [13]
Description
VDR
VCC for data retention
ICCDR
Data retention current
tCDR [14]
Chip deselect to data retention
time
tR [15]
Operation recovery time
VCC = 2 V, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
Min
Typ
Max
Unit
2
–
–
V
–
–
25
mA
0
–
–
ns
tRC
–
–
ns
Data Retention Waveform
Figure 3. Data Retention Waveform
DATA RETENTION MODE
VCC
3.0 V
VDR > 2 V
3.0 V
tR
tCDR
CE
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [16, 17]
tRC
RC
ADDRESS
tOHA
DATA I/O
PREVIOUS DATA VALID
tAA
DATA OUT VALID
Notes
13. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 or CE2 , or CE3 is LOW. When HIGH, CE indicates the CE1 , CE2 , and
CE3 are HIGH.
14. Tested initially and after any design or process changes that may affect these parameters.
15. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.
16. Device is continuously selected. OE, CE = VIL.
17. WE is HIGH for read cycle.
Document Number: 38-05610 Rev. *G
Page 7 of 15
CY7C1012DV33
Switching Waveforms (continued)
Figure 5. Read Cycle No. 2 (OE Controlled) [18, 19, 20]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tHZCE
tLZOE
DATA I/O
HIGH IMPEDANCE
DATA OUT VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
50%
50%
ISB
Figure 6. Write Cycle No. 1 (CE Controlled) [18, 21, 22]
tWC
ADDRESS
tSCE
CE
tSCE
tSA
tHA
tAW
WE
tPWE
tSD
DATA I/O
tHD
DATA IN VALID
Notes
18. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 or CE2 , or CE3 is LOW. When HIGH, CE indicates the CE1 , CE2 , and
CE3 are HIGH.
19. WE is HIGH for read cycle.
20. Address valid before or similar to CE transition LOW.
21. Data I/O is high impedance if OE = VIH.
22. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05610 Rev. *G
Page 8 of 15
CY7C1012DV33
Switching Waveforms (continued)
Figure 7. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [23, 24, 25]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
OE
tSD
tHZOE
DATA I/O
tHD
DATA IN VALID
NOTE 26
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [23, 25]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
DATA I/O
NOTE 26
tHD
DATA IN VALID
tHZWE
tLZWE
Notes
23. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 or CE2 , or CE3 is LOW. When HIGH, CE indicates the CE1 , CE2 , and
CE3 are HIGH.
24. Data I/O is high impedance if OE = VIH.
25. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
26. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05610 Rev. *G
Page 9 of 15
CY7C1012DV33
Truth Table
CE1 CE2 CE3
OE
WE
I/O0–I/O7
I/O8–I/O15
I/O16–I/O23
Mode
Power
H
H
H
X
X
High Z
High Z
High Z
Power Down
Standby (ISB)
L
H
H
L
H
Data Out
High Z
High Z
Read
Active (ICC)
H
L
H
L
H
High Z
Data Out
High Z
Read
Active (ICC)
H
H
L
L
H
High Z
High Z
Data Out
Read
Active (ICC)
L
L
L
L
H
Full Data Out
Full Data Out
Full Data Out
Read
Active (ICC)
L
H
H
X
L
Data In
High Z
High Z
Write
Active (ICC)
H
L
H
X
L
High Z
Data In
High Z
Write
Active (ICC)
H
H
L
X
L
High Z
High Z
Data In
Write
Active (ICC)
L
L
L
X
L
Full Data In
Full Data In
Full Data In
Write
Active (ICC)
L
L
L
H
H
High Z
High Z
High Z
Selected, Outputs Active (ICC)
Disabled
Document Number: 38-05610 Rev. *G
Page 10 of 15
CY7C1012DV33
Ordering Information
Speed
(ns)
10
Ordering Code
CY7C1012DV33-10BGXI
Package
Name
Package Type
51-85115 119-ball Plastic Ball Grid Array (14 × 22 × 2.4 mm) (Pb-free)
Operating
Range
Industrial
Ordering Code Definitions
CY 7 C 1
01
2
D V33 - 10
BG X
I
Temperature Range:
I = Industrial
Pb-free
Package Type:
BG = 119-ball PBGA
Speed: 10 ns
Voltage range: V33 = 3 V to 3.6 V
Process Technology: D = C9, 90 nm
Bus width: × 24
01 = 12-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05610 Rev. *G
Page 11 of 15
CY7C1012DV33
Package Diagram
Figure 9. 119-ball PBGA (14 × 22 × 2.4 mm) BG119 Package Outline, 51-85115
51-85115 *D
Document Number: 38-05610 Rev. *G
Page 12 of 15
CY7C1012DV33
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
chip enable
CMOS
complementary metal oxide semiconductor
°C
degree Celsius
I/O
input/output
MHz
megahertz
OE
output enable
A
microampere
PBGA
plastic ball grid array
s
microsecond
SRAM
static random access memory
mA
milliampere
TTL
transistor-transistor logic
mm
millimeter
WE
write enable
ns
nanosecond

ohm
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 38-05610 Rev. *G
Symbol
Unit of Measure
Page 13 of 15
CY7C1012DV33
Document History Page
Document Title: CY7C1012DV33, 12-Mbit (512 K × 24) Static RAM
Document Number: 38-05610
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
250650
SYT
See ECN
New data sheet
*A
469517
NXR
See ECN
Converted from Advance Information to Preliminary
Corrected typo in the Document Title
Removed -10 and -12 speed bins from product offering
Changed J7 ball of BGA from DNU to NC
Removed Industrial Operating range from product offering
Included the Maximum ratings for Static Discharge Voltage and Latch Up
Current on page 3
Changed ICC(Max) from 220 mA to 150 mA
Changed ISB1(Max) from 70 mA to 30 mA
Changed ISB2(Max) from 40 mA to 25 mA
Specified the Overshoot specification in footnote 1
Updated the Truth Table
Updated the Ordering Information table
*B
499604
NXR
See ECN
Added note 1 for NC pins
Changed ICC specification from 150 mA to 185 mA
Updated Test Condition for ICC in DC Electrical Characteristics table
Added note for tACE, tLZCE, tHZCE, tPU, tPD, and tSCE in AC Switching Characteristics Table on page 4
*C
1462585
VKN
See ECN
Converted from preliminary to final
Updated block diagram
Changed ICC specification from 185 mA to 225 mA
Updated thermal specs
*D
2604677
VKN /
PYRS
11/12/08
Removed Commercial operating range, Added Industrial operating range
Removed 8 ns speed bin, Added 10 ns speed bin,
Modified footnote# 3
*E
3104943
AJU
12/08/2010
Added Ordering Code Definitions.
Updated Package Diagram.
*F
3417829
TAVA
10/21/2011
Updated DC Electrical Characteristics.
Updated Switching Waveforms.
Added Acronyms and Units of Measure.
Updated in new template.
*G
4574311
TAVA
11/19 /2014 Added related documentation hyperlink in page 1.
Updated Figure 9 in Package Diagram (spec 51-85115 *C to *D).
Document Number: 38-05610 Rev. *G
Description of Change
Page 14 of 15
CY7C1012DV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
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© Cypress Semiconductor Corporation, 2004-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05610 Rev. *G
Revised November 20, 2014
All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 15 of 15