CY7C1049BN 512 K × 8 Static RAM 512 K × 8 Static RAM Features Functional Description ■ High speed ❐ tAA = 17 ns The CY7C1049BN is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). ■ Low active power ❐ 1073 mW (max.) ■ Low CMOS standby power ❐ 2.75 mW (max.) ■ 2.0 V data retention (400 W at 2.0 V retention) ■ Automatic power-down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expansion with CE and OE features Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1049BN is available in a standard 400-mil-wide 36-pin SOJ package with center power and ground (revolutionary) pinout. For a complete list of related documentation, click here. Logic Block Diagram I/O0 INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 I/O2 512K x 8 ARRAY SENSE AMPS ROW DECODER I/O1 I/O3 I/O4 I/O5 COLUMN DECODER CE POWER DOWN I/O7 A 11 A 12 A 13 A14 A15 A16 A17 A18 WE OE Cypress Semiconductor Corporation Document Number: 001-76449 Rev. *B I/O6 • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 18, 2014 CY7C1049BN Contents Pinouts .............................................................................. 3 Selection Guide ................................................................ 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 5 Data Retention Waveform ................................................ 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 7 Truth Table ...................................................................... 10 Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Document Number: 001-76449 Rev. *B Package Diagram ............................................................ 12 Acronyms ........................................................................ 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC® Solutions ...................................................... 15 Cypress Developer Community ................................. 15 Technical Support ..................................................... 15 Page 2 of 15 CY7C1049BN Pinouts Figure 1. 36-pin SOJ pinout (Top View) SOJ Top View A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O7 I/O6 GND VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC Selection Guide Description CY7C1049BNL-17 Maximum Access Time (ns) 17 Maximum Operating Current (mA) 195 Maximum CMOS Standby Current (mA) 0.5 Document Number: 001-76449 Rev. *B Page 3 of 15 CY7C1049BN DC Input Voltage [1] ............................ –0.5 V to VCC + 0.5 V Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Static Discharge Voltage (per MIL-STD-883, Method 3015) ........................... >2001 V Storage Temperature ............................... –65 C to +150 C Latch-Up Current .................................................... >200 mA Ambient Temperature with Power Applied ......................................... –55 C to +125 C Operating Range Supply Voltage on VCC to Relative GND [1] ...............................–0.5 V to +7.0 V Range DC Voltage Applied to Outputs in High Z State [1] ................................ –0.5 V to VCC + 0.5 V Ambient Temperature VCC 0 C to +70 C 4.5 V–5.5 V Commercial L Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage [1] 7C1049B-17 Unit Min Max 2.4 – V – 0.4 V 2.2 VCC + 0.3 V VIL Input LOW Voltage –0.3 0.3 V IIX Input Load Current GND < VI < VCC –1 +1 A IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 A ICC VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC – 195 mA ISB1 Automatic CE Power-Down Current – TTL Inputs Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – 40 mA ISB2 Automatic CE Power-Down Current – CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3 V, f = 0, Commercial – 0.5 mA Note 1. Minimum voltage is–2.0V for pulse durations of less than 20 ns. Document Number: 001-76449 Rev. *B Page 4 of 15 CY7C1049BN Capacitance Parameter [2] Description CIN Input capacitance COUT I/O capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 5.0 V Max. Unit 8 pF 8 pF AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms R1 481 5V R1 481 5V OUTPUT 3.0V OUTPUT R2 255 30 pF INCLUDING JIG AND SCOPE (a) R2 255 5 pF GND INCLUDING JIG AND SCOPE (b) ALL INPUT PULSES 90% 90% 10% 10% 3 ns 3 ns THÉVENIN EQUIVALENT 167 1.73V OUTPUT Equivalent to: Data Retention Characteristics Over the Operating Range Parameter VDR Min Max Unit 2.0 – V VCC = VDR = 3.0 V, – 200 A Chip Deselect to Data Retention Time CE > VCC – 0.3 V, 0 – ns Operation Recovery Time VIN > VCC – 0.3 V or VIN < 0.3 V tRC – ns VCC for Data Retention ICCDR tCDR Conditions [3] Description Data Retention Current [2] tR[4] Commercial L Data Retention Waveform Figure 3. Data Retention Waveform DATA RETENTION MODE VCC 3.0 V VDR > 2 V tCDR 3.0 V tR CE Notes 2. Tested initially and after any design or process changes that may affect these parameters. 3. No input may exceed VCC + 0.5 V. 4. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds. Document Number: 001-76449 Rev. *B Page 5 of 15 CY7C1049BN Switching Characteristics Over the Operating Range Parameter [5] Description CY7C1049BNL-17 Min Max Unit Read Cycle tpower VCC(typical) to the First Access [6] 1 – ms tRC Read Cycle Time 17 – ns tAA Address to Data Valid – 17 ns tOHA Data Hold from Address Change 3 – ns tACE CE LOW to Data Valid – 17 ns tDOE OE LOW to Data Valid – 8 ns 0 – ns – 7 ns 3 – ns – 7 ns tLZOE OE LOW to Low Z [7] [7, 8] tHZOE OE HIGH to High Z tLZCE CE LOW to Low Z [7] [7, 8] tHZCE CE HIGH to High Z tPU CE LOW to Power-Up 0 – ns tPD CE HIGH to Power-Down – 17 ns Write Cycle [9, 10] tWC Write Cycle Time 17 – ns tSCE CE LOW to Write End 12 – ns tAW Address Set-Up to Write End 12 – ns tHA Address Hold from Write End 0 – ns tSA Address Set-Up to Write Start 0 – ns tPWE WE Pulse Width 12 – ns tSD Data Set-Up to Write End 8 – ns tHD Data Hold from Write End 0 – ns WE HIGH to Low Z [7] 3 – ns WE LOW to High Z [7, 8] – 8 ns tLZWE tHZWE Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. tpower time has to be provided initially before a read/write operation is started. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 9. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 001-76449 Rev. *B Page 6 of 15 CY7C1049BN Switching Waveforms Figure 4. Read Cycle No. 1 [11, 12] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled) [12, 13] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZCE HIGH IMPEDANCE DATA VALID tPD tPU 50% 50% ICC ISB Notes 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document Number: 001-76449 Rev. *B Page 7 of 15 CY7C1049BN Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (CE Controlled) [14, 15] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Figure 7. Write Cycle No. 2 (WE Controlled, OE HIGH during Write) [14, 15] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 16 tHZOE Notes 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 16. During this period the I/Os are in the output state and input signals should not be applied. Document Number: 001-76449 Rev. *B Page 8 of 15 CY7C1049BN Switching Waveforms (continued) Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [17, 18] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 19 tHD DATA VALID tHZWE tLZWE Notes 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 18. The minimum write cycle pulse width should be equal to sum of tSD and tHZWE. 19. During this period the I/Os are in the output state and input signals should not be applied. Document Number: 001-76449 Rev. *B Page 9 of 15 CY7C1049BN Truth Table CE WE OE Inputs/Outputs H X X High Z Power-down Standby (ISB) L H L Data Out Read Active (ICC) L L X Data In Write Active (ICC) L H H High Z Selected, Output disabled Active (ICC) Document Number: 001-76449 Rev. *B Mode Power Page 10 of 15 CY7C1049BN Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Speed (ns) 17 Ordering Code CY7C1049BNL-17VC Package Diagram Operating Range Package Type 51-85090 36-pin (400-Mil) Molded SOJ Commercial L Ordering Code Definitions CY 7 C 1 04 9 BN L - 17 V C Temperature Grade: C = Commercial Package Type: V = 36-pin Molded SOJ Speed Grade: 17 ns Low Power Process Technology: BN = 180 nm Bus width: 9 = × 8 Density: 04 = 4-Mbit Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-76449 Rev. *B Page 11 of 15 CY7C1049BN Package Diagram Figure 9. 36-pin SOJ V36.4 (Molded) Package Outline, 51-85090 51-85090 *F Document Number: 001-76449 Rev. *B Page 12 of 15 CY7C1049BN Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable µA microampere SRAM Static Random Access Memory mA milliampere Write Enable mV millivolt mW milliwatt ns nanosecond WE Document Number: 001-76449 Rev. *B Symbol Unit of Measure pF picofarad V volt W watt Page 13 of 15 CY7C1049BN Document History Page Document Title: CY7C1049BN, 512 K × 8 Static RAM Document Number: 001-76449 Revision ECN Orig. of Change Submission Date ** 3539227 TAVA 03/01/2012 New data sheet. *A 4371513 VINI 05/06/2014 Updated Switching Waveforms: Added Note 18 and referred the same note in Figure 8. Updated in new template. Completing Sunset Review. *B 4573121 VINI 11/18/2014 Added related documentation hyperlink in page 1. Document Number: 001-76449 Rev. *B Description of Change Page 14 of 15 CY7C1049BN Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory PSoC Touch Sensing cypress.com/go/memory cypress.com/go/psoc PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2012-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-76449 Rev. *B Revised November 18, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 15 of 15