CY7C1049DV33 4-Mbit (512 K × 8) Static RAM 4-Mbit (512 K × 8) Static RAM Features Functional Description ■ Pin and function compatible with CY7C1049CV33 The CY7C1049DV33 is a high performance CMOS Static RAM organized as 512K words by 8-bits. Easy memory expansion is provided by an Active LOW Chip Enable (CE), an Active LOW Output Enable (OE), and tristate drivers. You can write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A18). ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 90 mA at 10 ns ■ Low CMOS standby power ❐ ISB2 = 10 mA ■ 2.0 V data retention ■ Automatic power down when deselected ■ TTL compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in Pb-free 36-pin (400 Mil) molded SOJ and 44-pin TSOP II packages You can read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The eight input or output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1049DV33 is available in standard 400 Mil wide 36 -pin SOJ package and 44-pin TSOP II package with center power and ground (revolutionary) pinout. For a complete list of related documentation, click here. Logic Block Diagram IO0 INPUT BUFFER IO1 512K x 8 ARRAY IO3 IO4 IO5 IO6 CE COLUMN DECODER WE IO7 POWER DOWN A11 A12 A13 A14 A15 A16 A17 A18 OE Cypress Semiconductor Corporation Document Number: 38-05475 Rev. *I IO2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 20, 2014 CY7C1049DV33 Contents Pin Configuration ............................................................. 3 Selection Guide ................................................................ 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 5 AC Switching Characteristics ......................................... 6 Switching Waveforms ...................................................... 7 Truth Table ........................................................................ 9 Document Number: 38-05475 Rev. *I Ordering Information ........................................................ 9 Ordering Code Definitions ........................................... 9 Package Diagrams .......................................................... 10 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14 Page 2 of 14 CY7C1049DV33 Pin Configuration 44-pin TSOP II Top View 36-pin SOJ Top View A0 A1 A2 A3 A4 CE IO0 IO1 VCC GND IO2 IO3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE IO7 IO6 GND VCC IO5 IO4 A14 A13 A12 A11 A10 NC NC NC A0 A1 A2 A3 A4 CE IO0 IO1 VCC VSS IO2 IO3 WE A5 A6 A7 A8 A9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A18 A17 A16 A15 OE IO7 IO6 VSS VCC IO5 IO4 A14 A13 A12 A11 A10 NC NC NC Selection Guide Description -10 (Industrial) Unit Maximum access time 10 ns Maximum operating current 90 mA Maximum CMOS standby current 10 mA Document Number: 38-05475 Rev. *I Page 3 of 14 CY7C1049DV33 DC input voltage[1] .............................. –0.3 V to VCC + 0.3 V Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. User guidelines are not tested. Current into outputs (LOW) ........................................ 20 mA Static discharge voltage .......................................... > 2001 V Storage temperature ................................ –65 C to +150 C (MIL-STD-883, Method 3015) Ambient temperature with power applied .......................................... –55 C to +125 C Latch up current ..................................................... > 200 mA Operating Range Supply voltage on VCC to relative GND[1] .................................–0.3 V to +4.6 V Ambient Temperature Range DC voltage applied to outputs in High Z State[1] ................................. –0.3 V to VCC + 0.3 V Industrial VCC Speed –40 C to +85 C 3.3 V 0.3 V 10 ns Electrical Characteristics Over the Operating Range -10 (Industrial) Parameter Description Test Conditions VOH Output HIGH voltage VCC = Min, IOH = –4.0 mA VOL Output LOW voltage VCC = Min, IOL = 8.0 mA VIH[1] Input HIGH voltage voltage[1] Min Max Unit 2.4 – V – 0.4 V 2.0 VCC + 0.3 V –0.3 0.8 V VIL[1] Input LOW IIX Input leakage current GND < VI < VCC –1 +1 A IOZ Output leakage current GND < VOUT < VCC, Output Disabled –1 +1 A ICC VCC operating supply current VCC = Max, f = fMAX = 1/tRC 100 MHz – 90 mA 83 MHz – 80 mA 66 MHz – 70 mA 40 MHz – 60 mA ISB1 Automatic CE Power down current —TTL Inputs Max VCC, CE > VIH; VIN > VIH or VIN < VIL, f = fMAX – 20 mA ISB2 Automatic CE Power down current —CMOS Inputs Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f=0 – 10 mA Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input capacitance COUT I/O capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V Max Unit 8 pF 8 pF Note 1. VIL (min.) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. Document Number: 38-05475 Rev. *I Page 4 of 14 CY7C1049DV33 Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description JA Thermal resistance (Junction to Ambient) JC Thermal resistance (Junction to Case) 36-pin SOJ Package Test Conditions Still Air, soldered on a 3 × 4.5 inch, two layer printed circuit board 44-pin TSOP II Package Unit 57.91 50.66 C/W 36.73 17.17 C/W AC Test Loads and Waveforms Figure 1. AC Test Loads and Waveforms [4] 10 ns device Z = 50 ALL INPUT PULSES 3.0 V 90% OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 30 pF* GND 90% 10% 10% 1.5 V Rise Time: 1 V/ns (a) High Z characteristics: (b) Fall Time: 1 V/ns R 317 3.3 V OUTPUT R2 351 5 pF (c) Data Retention Characteristics Over the Operating Range Parameter Conditions [4] Description VDR VCC for data retention ICCDR Data retention current VCC = VDR = 2.0 V, CE > VCC – 0.3 V Min Max Unit 2.0 – V – 10 mA 0 – ns tRC – ns VIN > VCC – 0.3 V or VIN < 0.3 V tCDR[2] tR Chip deselect to data retention time [5] Operation recovery time Figure 2. Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR VDR > 2V 3.0V tR CE Notes 2. Tested initially and after any design or process changes that may affect these parameters. 3. AC characteristics (except High Z) are tested using the load conditions shown in Figure 1 (a). High Z characteristics are tested for all speeds using the test load shown in Figure 1 (c). 4. No input may exceed VCC + 0.3 V. 5. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. Document Number: 38-05475 Rev. *I Page 5 of 14 CY7C1049DV33 AC Switching Characteristics Over the Operating Range [6] -10 (Industrial) Parameter Description Min Max Unit Read Cycle tpower[7] VCC (typical) to the first access 100 – s tRC Read cycle time 10 – ns tAA Address to data valid – 10 ns tOHA Data hold from address change 3 – ns tACE CE LOW to data valid – 10 ns tDOE OE LOW to data valid – 5 ns tLZOE OE LOW to Low Z[8] 0 – ns – 5 ns ns ns tHZOE OE HIGH to High Z[8, 9] Z[8] tLZCE CE LOW to Low 3 – tHZCE CE HIGH to High Z[8, 9] – 5 tPU CE LOW to power up 0 – ns tPD CE HIGH to power down – 10 ns tWC Write cycle time 10 – ns Write Cycle[10, 11] tSCE CE LOW to write end 7 – ns tAW Address setup to write end 7 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns ns tPWE WE pulse width 7 – tSD Data setup to write end 5 – ns tHD Data hold from write end tLZWE tHZWE 0 – ns WE HIGH to Low Z[8] 3 – ns WE LOW to High Z[8, 9] – 5 ns Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30 pF load capacitance. 7. tPOWER gives the minimum amount of time that the power supply must be at stable, typical VCC values until the first memory access is performed. 8. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of Figure 1 on page 5. Transition is measured when the outputs enter a high impedance state. 10. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set up and hold timing must be referred to the leading edge of the signal that terminates the write. 11. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05475 Rev. *I Page 6 of 14 CY7C1049DV33 Switching Waveforms Figure 3. Read Cycle No. 1[12, 13] tRC ADDRESS tOHA DATA I/O tAA PREVIOUS DATA VALID DATAOUT VALID Figure 4. Read Cycle No. 2 (OE Controlled)[13, 14] ADDRESS tRC CE tACE OE tHZOE tDOE DATA I/O tHZCE tLZOE HIGH IMPEDANCE DATAOUT VALID tLZCE tPD tPU VCC SUPPLY CURRENT HIGH IMPEDANCE 50% 50% ICC ISB Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During Write)[15, 16] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 16 tHZOE Notes 12. Device is continuously selected. OE, CE = VIL. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE transition LOW. 15. Data I/O is high impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 38-05475 Rev. *I Page 7 of 14 CY7C1049DV33 Switching Waveforms (continued) Figure 6. Write Cycle No. 2 (WE Controlled, OE LOW)[17] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 18 tHD DATAIN VALID tLZWE tHZWE Figure 7. Write Cycle No. 3 (CE Controlled)[17, 19] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATAIN VALID Notes 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. 18. During this period the I/Os are in the output state and input signals must not be applied. 19. Data I/O is high impedance if OE = VIH. Document Number: 38-05475 Rev. *I Page 8 of 14 CY7C1049DV33 Truth Table CE H OE X WE X L L H IO0–IO7 Mode Power High Z Power down Standby (ISB) Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 Ordering Code Package Name Package Type CY7C1049DV33-10VXI 51-85090 36-pin (400-Mil) Molded SOJ (Pb-free) CY7C1049DV33-10ZSXI 51-85087 44-pin TSOP II (Pb-free) Operating Range Industrial Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 7 C 1 04 9 D V33 - XX XX X X Temperature Range: X = I I = Industrial Pb-free Package Type: XX = V or ZS V = 36-pin (400-Mil) Molded SOJ ZS = 44-pin TSOP II Speed: XX = 10 ns V33 = Voltage range (3 V to 3.6 V) D = C9, 90 nm Technology 9 = Data width × 8-bits 04 = 4-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Document Number: 38-05475 Rev. *I Page 9 of 14 CY7C1049DV33 Package Diagrams Figure 8. 36-pin (400-Mil) Molded SOJ V36.4, (51-85090) 51-85090 *F Document Number: 38-05475 Rev. *I Page 10 of 14 CY7C1049DV33 Package Diagrams (continued) Figure 9. 44-pin TSOP Z44-II, (51-85087) 51-85087 *E Document Number: 38-05475 Rev. *I Page 11 of 14 CY7C1049DV33 Acronyms Acronym Document Conventions Description Units of Measure CE chip enable CMOS complementary metal oxide semiconductor °C degree Celcius I/O input/output MHz megahertz OE output enable µA microamperes SOJ small outline J-lead µs microseconds SRAM static random access memory mA milliamperes TSOP thin small outline package mm millimeter TTL transistor-transistor logic ms milliseconds WE write enable ns nanoseconds ohms % percent pF pico Farad V Volts W Watts Document Number: 38-05475 Rev. *I Symbol Unit of Measure Page 12 of 14 CY7C1049DV33 Document History Page Document Title: CY7C1049DV33, 4-Mbit (512 K × 8) Static RAM Document Number: 38-05475 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 201560 See ECN SWI Advance Datasheet for C9 IPP *A 233729 See ECN SYT 1.AC, DC parameters are modified as per EROS (Specification # 01-2165) 2.Pb-free offering in the Ordering Information Table *B 351096 See ECN PCI Changed from Advance to Preliminary Removed 20 ns Speed bin Corrected DC voltage (min) value in maximum ratings section from - 0.5 to - 0.3V Redefined ICC values for Com’l and Ind’l temperature ranges ICC (Com’l): Changed from 100, 80, and 67 mA to 90, 80 and, 75 mA for 8, 10, and 12ns speed bins respectively ICC (Ind’l): Changed from 80 and 67 mA to 90 and 85 mA for 10 and 12ns speed bins respectively Added VIH(max) specification in Note# 2 Changed reference voltage level for measurement of High Z parameters from 500 mV to 200 mV Added Data Retention Characteristics, Waveform, and footnotes 11 and 12 Changed Package Diagram name from 44-pin TSOP II Z44 to 44-pin TSOP II ZS44 Changed part names from Z to ZS in the Ordering Information Table Added 8 ns parts in the Ordering Information Table Added Pb-free Ordering Information Shaded Ordering Information Table *C 446328 See ECN NXR Converted from Preliminary to Final Removed -8 speed bin Removed Commercial Operating Range product information Added Automotive Operating Range product information Updated Thermal Resistance table Updated footnote #8 on High Z parameter measurement Replaced Package Name column with Package Diagram in the Ordering Information table *D 1274726 See ECN VKN/AESA Corrected typo in the 44-Pin TSOP II pinout *E 2899972 03/29/2010 AJU *F 3059162 10/14/2010 PRAS Added Ordering Code Definitions. Updated Package Diagrams. *G 3266084 05/28/2011 PRAS Updated Functional Description (Removed “Refer to the Cypress application note AN1064, SRAM System Guidelines for best practice recommendations.”). Added Acronyms and Units of Measure. Updated in new template. *H 3440302 11/16/2011 TAVA Removed automotive part information from the datasheet. Updated read and write waveforms. *I 4574311 11/19/2014 TAVA Added related documentation hyperlink in page 1. Updated Figure 8 in Package Diagrams (spec 51-85090 *E to *F). Document Number: 38-05475 Rev. *I Updated Package Diagrams. Page 13 of 14 CY7C1049DV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive Clocks & Buffers cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory Optical & Image Sensing cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05475 Rev. *I Revised November 20, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 14 of 14