CY7C1046D 4-Mbit (1 M × 4) Static RAM 4-Mbit (1 M × 4) Static RAM Features provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O0 through I/O3) is then written into the location specified on the address pins (A0 through A19). ■ Pin- and function-compatible with CY7C1046B ■ High speed ❐ tAA = 10 ns ■ CMOS for optimum speed and power ■ Low active power ❐ ICC = 90 mA at 10 ns ■ Low CMOS standby power ❐ ISB2 = 10 mA ■ Data retention at 2.0 V ■ Automatic power-down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in lead-free 400-mil-wide 32-pin SOJ package Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The four input/output pins (I/O0 through I/O3) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1046D is available in a standard 400-mil-wide 32-pin SOJ package with center power and ground (revolutionary) pinout. Functional Description The CY7C1046D is a high-performance CMOS static RAM organized as 1M words by 4 bits. Easy memory expansion is The CY7C1046D device is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that require CMOS I/P levels. Please see Electrical Characteristics on page 4 for more details and suggested alternatives. For a complete list of related documentation, click here. Logic Block Diagram INPUT BUFFER ROW DECODER I/O0 1M x 4 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 I/O1 I/O2 I/O3 COLUMN DECODER CE POWER DOWN A 11 A 12 A 13 A14 A15 A16 A17 A18 A19 WE OE Cypress Semiconductor Corporation Document Number: 38-05705 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 20, 2014 CY7C1046D Contents Selection Guide ................................................................ 3 Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Document Number: 38-05705 Rev. *G Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagrams .......................................................... 13 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC® Solutions ...................................................... 16 Cypress Developer Community ................................. 16 Technical Support ..................................................... 16 Page 2 of 16 CY7C1046D Selection Guide –10 Unit Maximum Access Time Description 10 ns Maximum Operating Current 90 mA Maximum CMOS Standby Current (mA) 10 mA Pin Configuration Figure 1. 32-pin SOJ pinout (Top View) A0 A1 A2 A3 A4 CE I/O0 VCC GND I/O1 WE A5 A6 A7 A8 A9 Document Number: 38-05705 Rev. *G 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A19 A18 A17 A16 A15 OE I/O3 GND VCC I/O2 A14 A13 A12 A11 A10 NC Page 3 of 16 CY7C1046D DC input voltage [1] ............................. –0.5 V to VCC + 0.5 V Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 C to +150 C Ambient temperature with power applied .......................................... –55 C to +125 C Current into outputs (LOW) ........................................ 20 mA Static discharge voltage (per MIL-STD-883, method 3015) .......................... > 2001 V Latch up current ..................................................... > 200 mA Operating Range Supply voltage on VCC to relative GND [1] ................................–0.5 V to +6.0 V DC voltage applied to outputs in high Z state [1] .................................. –0.5 V to VCC + 0.5 V Range Ambient Temperature VCC –40 C to +85 C 4.5 V–5.5 V Industrial Electrical Characteristics Over the Operating Range Parameter VOH Description Output HIGH voltage VOL Output LOW voltage -10 Test Conditions VCC = Min, IOH = –4.0 mA Min Max 2.4 – 3.4 Unit V [2] VCC = Max, IOH = –0.1 mA – VCC = Min, IOL = 8.0 mA – 0.4 V VIH Input HIGH voltage 2.0 VCC + 0.5 V VIL Input LOW voltage [1] –0.5 0.8 V IIX Input leakage current GND < VIN < VCC –1 +1 A IOZ Output leakage current GND < VOUT < VCC, output disabled –1 +1 A ICC VCC operating supply current VCC = Max, f = fMAX = 1/tRC mA 100 MHz – 90 83 MHz – 80 66 MHz – 70 40 MHz – 60 ISB1 Automatic CE Power-Down Current – TTL inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – 20 mA ISB2 Automatic CE Power-Down Current – CMOS inputs Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 – 10 mA Notes 1. VIL (min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. 2. Please note that the maximum VOH limit does not exceed minimum CMOS VIH of 3.5V. If you are interfacing this SRAM with 5V legacy processors that require a minimum VIH of 3.5V, please refer to Application Note AN6081 for technical details and options you may consider. Document Number: 38-05705 Rev. *G Page 4 of 16 CY7C1046D Capacitance Parameter [3] Description CIN Input capacitance COUT I/O capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 5.0 V Max Unit 8 pF 8 pF Thermal Resistance Parameter [3] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions SOJ Package Unit Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 53.44 C/W 38.25 C/W AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms [4] Z = 50 ALL INPUT PULSES 3V OUTPUT 90% 50 30 pF* GND 1.5 V * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT (a) 10%VCC Rise Time:1 V/ns (b) R1 481 Fall Time: 1 V/ns 5V OUTPUT 5 pF High Z Characteristics: 90%VCC 10% INCLUDING JIG AND SCOPE (c) R2 255 Equivalent to: THÉVENIN EQUIVALENT 167 1.73 V OUTPUT Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. AC characteristics (except high Z) are tested using the load conditions shown in (a). High Z characteristics are tested for all speeds using the test load shown in (c). Document Number: 38-05705 Rev. *G Page 5 of 16 CY7C1046D Data Retention Characteristics Over the Operating Range Parameter Conditions [5] Description VDR VCC for data retention ICCDR Data retention current tCDR[6] Chip deselect to data retention time tR [7] Operation recovery time VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Min Max Unit 2.0 – V – 10 mA 0 – ns tRC – ns Data Retention Waveform Figure 3. Data Retention Waveform DATA RETENTION MODE VCC 4.5 V VDR > 2 V tCDR 4.5 V tR CE Notes 5. No inputs may exceed VCC + 0.3 V. 6. Tested initially and after any design or process changes that may affect these parameters. 7. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s. Document Number: 38-05705 Rev. *G Page 6 of 16 CY7C1046D Switching Characteristics Over the Operating Range Parameter [8] Description 7C1046D-10 Min Max Unit Read Cycle tpower VCC(typical) to the first access[9] 100 – s tRC Read cycle time 10 – ns tAA Address to data valid – 10 ns tOHA Data hold from address change 3 – ns tACE CE LOW to data valid – 10 ns tDOE OE LOW to data valid – 5 ns 0 – ns – 5 ns Z[11] tLZOE OE LOW to low tHZOE OE HIGH to high Z[10, 11] Z[11] tLZCE CE LOW to low 3 – ns tHZCE CE HIGH to high Z[10, 11] – 5 ns tPU CE LOW to power-up 0 – ns tPD CE HIGH to power-down – 10 ns Write Cycle[12, 13] tWC Write cycle time 10 – ns tSCE CE LOW to write end 7 – ns tAW Address set-up to write end 7 – ns tHA Address hold from write end 0 – ns tSA Address set-up to write start 0 – ns tPWE WE pulse width 7 – ns tSD Data set-up to write end 6 – ns tHD Data hold from write end 0 – ns WE HIGH to low Z[11] 3 – ns WE LOW to high Z[10, 11] – 5 ns tLZWE tHZWE Notes 8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V. 9. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed. 10. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads.Transition is measured when the outputs enter a high impedance state. 11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 12. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 13. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05705 Rev. *G Page 7 of 16 CY7C1046D Switching Waveforms Figure 4. Read Cycle No. 1 [14, 15] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled) [15, 16] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZCE HIGH IMPEDANCE DATA VALID tPD tPU 50% ICC 50% ISB Notes 14. Device is continuously selected. OE, CE = VIL. 15. WE is HIGH for read cycle. 16. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05705 Rev. *G Page 8 of 16 CY7C1046D Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (CE Controlled) [17, 18] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Figure 7. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [17, 18] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 19 tHZOE Notes 17. Data I/O is high impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 19. During this period the I/Os are in the output state and input signals should not be applied. Document Number: 38-05705 Rev. *G Page 9 of 16 CY7C1046D Switching Waveforms (continued) Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [20] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 21 tHD DATA VALID tHZWE tLZWE Notes 20. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 21. During this period the I/Os are in the output state and input signals should not be applied. Document Number: 38-05705 Rev. *G Page 10 of 16 CY7C1046D Truth Table CE OE WE H X X High Z Power-down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, outputs disabled Active (ICC) Document Number: 38-05705 Rev. *G I/O0–I/O3 Mode Power Page 11 of 16 CY7C1046D Ordering Information Speed (ns) 10 Ordering Code CY7C1046D-10VXI Package Diagram 51-85033 Package Type 32-pin (400-Mil) Molded SOJ (Pb-free) Operating Range Industrial Please contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 7 C 1 04 6 D - 10 VX I Temperature Range: I = Industrial Package Type: VX = 32-pin (400-Mil) Molded SOJ (Pb-free) Speed: 10 ns D = C9, 90 nm Technology Data width: 6 = × 4-bits Density: 04 = 4-Mbit density Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05705 Rev. *G Page 12 of 16 CY7C1046D Package Diagrams Figure 9. 32-pin SOJ (400 Mils) V32.4 (Molded SOJ V33) Package Outline, 51-85033 51-85033 *E Document Number: 38-05705 Rev. *G Page 13 of 16 CY7C1046D Acronyms Acronym Document Conventions Description Units of Measure CMOS Complementary Metal Oxide Semiconductor CE Chip Enable °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable µs microsecond SOJ Small-Outline J-leaded µA microampere SRAM Static Random Access Memory mA milliampere TTL Transistor-Transistor Logic ns nanosecond WE Write Enable % percent Document Number: 38-05705 Rev. *G Symbol Unit of Measure pF picofarad V volt W watt Page 14 of 16 CY7C1046D Document History Page Document Title: CY7C1046D, 4-Mbit (1 M × 4) Static RAM Document Number: 38-05705 Rev. ECN No. Issue Date Orig. of Change ** 307613 See ECN RKF New data sheet. *A 399070 See ECN NXR Changed from Advance to Preliminary Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Removed -20 speed bin Removed L-Version Redefined ICC values for Com’l and Ind’l temperature ranges ICC (Com’l): Changed from 70 and 55 mA to 75 and 70 mA for 12 and 15 ns speed bins respectively ICC (Ind’l): Changed from 80, 70 and 55 mA to 90, 85 and 80 mA for 10, 12 and 15 ns speed bins respectively Added Industrial Operating Range Changed reference voltage level for measurement of Hi-Z parameters from 500 mV to 200 mV Changed VCC to 3 V in the Input pulse waveform at the AC Test Loads and Waveforms on page # 3 Changed tSCE from 8 to 7 ns for -10 speed bin Added Truth Table Added 10 ns parts in the Ordering Information table Changed part names from V33 to V324 in the Ordering Information Table Shaded Ordering Information Table *B 459072 See ECN NXR Converted from Preliminary to Final. Removed -12 and -15 Speed bins Removed Commercial Operating Range product information. Changed Maximum Rating for supply voltage from 7V to 6V Changed the Capacitance value of input pins and I/O pins from 6 pF to 8 pF Updated the Thermal Resistance table. Changed tHZWE from 6 ns to 5 ns Added footnote #4 and 11 Updated footnote #7 on High-Z parameter measurement Updated the Ordering Information and replaced Package Name column with Package Diagram in the Ordering Information table. *C 3059162 10/14/2010 PRAS Added Ordering Code Definitions. Updated Package Diagrams. *D 3098812 12/01/2010 PRAS Added Acronyms and Units of Measure. Minor edits and updated in new template. *E 3446913 11/24/2011 TAVA Removed Note referring to SRAM System Guidelines application note on page 1. Updated test conditions for IIX parameter. *F 4039540 06/25/2013 MEMJ Updated Functional Description. Updated Electrical Characteristics: Added one more Test Condition “VCC = Max, IOH = –0.1 mA” for VOH parameter and added maximum value corresponding to that Test Condition. Added Note 2 and referred the same note in maximum value for VOH parameter corresponding to Test Condition “VCC = Max, IOH = –0.1 mA”. *G 4574311 11/20/2014 MEMJ Added related documentation hyperlink in page 1. Updated Figure 9 in Package Diagrams (spec 51-85033 *D to *E). Document Number: 38-05705 Rev. *G Description of Change Page 15 of 16 CY7C1046D Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/support cypress.com/go/touch USB Controllers Wireless/RF Technical Support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2005-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05705 Rev. *G Revised November 20, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 16 of 16