CY7C10612G CY7C10612GE PRELIMINARY 16-Mbit (1 M × 16) Static RAM 16-Mbit (1 M × 16) Static RAM Features Functional Description ■ High speed ❐ tAA = 10 ns ■ Embedded error-correcting code (ECC) for single-bit error correction ■ Low active power ❐ ICC = 90 mA typical ■ Low CMOS standby power ❐ ISB2 = 20 mA typical ■ Operating voltages of 3.3 ± 0.3 V ■ 1.0 V data retention ■ Transistor-transistor logic (TTL) compatible inputs and outputs ■ ERR pin to indicate 1-bit error detection and correction ■ Available in Pb-free 54-pin TSOP II package The CY7C10612G and CY7C10612GE are high performance CMOS fast static RAM devices with embedded ECC. both device are offered in single chip enable option. The CY7C10612GE device includes an error indication pin that signals an error-detection and correction event during a read cycle. To write to the device, take Chip Enables (CE) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See Truth Table on page 14 for a complete description of Read and Write modes. The input or output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). On the CY7C10612GE devices the detection and correction of a single-bit error in the accessed location is indicated by the assertion of the ERR output (ERR = high). See the Truth Table on page 14 for a complete description of read and write modes. The CY7C10612G and CY7C10612GE are available in a 54-pin TSOP II package. For a complete list of related documentation, click here. Cypress Semiconductor Corporation Document Number: 001-88702 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 12, 2015 CY7C10612G CY7C10612GE PRELIMINARY Logic Block Diagram – CY7C10612G 1M x 16 ARRAY SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER I/O0 – I/O7 I/O8 – I/O15 A10 A11 A 12 A 13 A 14 A15 A16 A17 A18 A19 COLUMN DECODER BHE WE CE OE BLE Logic Block Diagram – CY7C10612GE Document Number: 001-88702 Rev. *C Page 2 of 19 PRELIMINARY CY7C10612G CY7C10612GE Contents Selection Guide ................................................................ 4 Pin Configurations ........................................................... 4 Maximum Ratings ............................................................. 6 Operating Range ............................................................... 6 DC Electrical Characteristics .......................................... 6 Capacitance ...................................................................... 7 Thermal Resistance .......................................................... 7 AC Test Loads and Waveforms ....................................... 7 Data Retention Characteristics ....................................... 8 Data Retention Waveform ................................................ 8 AC Switching Characteristics ......................................... 9 Switching Waveforms .................................................... 10 Truth Table ...................................................................... 14 ERR Output – CY7C10612GE ........................................ 14 Document Number: 001-88702 Rev. *C Ordering Information ...................................................... 15 Ordering Code Definitions ......................................... 15 Package Diagrams .......................................................... 16 Acronyms ........................................................................ 17 Document Conventions ................................................. 17 Units of Measure ....................................................... 17 Document History Page ................................................. 18 Sales, Solutions, and Legal Information ...................... 19 Worldwide Sales and Design Support ....................... 19 Products .................................................................... 19 PSoC® Solutions ...................................................... 19 Cypress Developer Community ................................. 19 Technical Support ..................................................... 19 Page 3 of 19 CY7C10612G CY7C10612GE PRELIMINARY Selection Guide Description -10 Unit Maximum Access Time 10 ns Maximum Operating Current 110 mA Maximum CMOS Standby Current 30 mA Pin Configurations Figure 1. 54-pin TSOP II Pinout (Top View) [1] CY7C10612G I/O12 VCC I/O13 I/O14 VSS I/O15 A4 A3 A2 A1 A0 BHE CE VCC WE NC A19 A18 A17 A16 A15 I/O0 VCC I/O1 I/O2 VSS I/O3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 45 44 I/O11 VSS I/O10 I/O9 VCC I/O8 A5 A6 A7 A8 A9 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 NC OE VSS NC BLE A10 A11 A12 A13 A14 I/O7 VSS I/O6 I/O5 VCC I/O4 54 53 52 51 50 49 48 47 46 Note 1. NC pins are not connected on the die. Document Number: 001-88702 Rev. *C Page 4 of 19 PRELIMINARY CY7C10612G CY7C10612GE Pin Configurations (continued) Figure 2. 54-pin TSOP II Pinout with ERR (Top View) [2, 3] CY7C10612GE Note 2. NC pins are not connected on the die. 3. ERR is an Output pin. If not used, this pin should be left floating. Document Number: 001-88702 Rev. *C Page 5 of 19 CY7C10612G CY7C10612GE PRELIMINARY DC Input Voltage [4] ............................ –0.5 V to VCC + 0.5 V Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ............................... –65 C to +150 C Ambient Temperature with Power Applied ......................................... –55 C to +125 C Supply Voltage on VCC Relative to GND [4] ...................... –0.5 V to VCC + 0.5 V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (MIL-STD-883, Method 3015) ..... ............................> 2001 V Latch Up Current ................................................... > 200 mA Operating Range DC Voltage Applied to Outputs in High Z State [4] ................................ –0.5 V to VCC + 0.5 V Range Ambient Temperature VCC Industrial –40 C to +85 C 3.3 V 0.3 V DC Electrical Characteristics Over the operating range of –40 C to 85 C Parameter Description Test Conditions 10 ns Min Typ[5] Max VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA VOL Output LOW Voltage VCC = Min, IOL = 8 mA 2.2 – – – – 0.4 VIH[4] Input HIGH Voltage – 2.0 – VCC + 0.3 VIL[4] Input LOW Voltage – –0.3 – 0.8 IIX Input Leakage Current GND < VIN < VCC –1.0 – +1.0 IOZ Output Leakage Current GND < VOUT < VCC, Output disabled –1.0 – +1.0 f = 100 MHz – 90.0 110.0 f = 66.7 MHz – 70.0 80.0 – – 40.0 – 20.0 30.0 VCC = Max, ICC Operating Supply Current IOUT = 0 mA, Unit V A CMOS levels ISB1 Automatic CE Power-down Current – TTL Inputs ISB2 Automatic CE Power-down Current – CMOS Inputs Max VCC, CE > VIH [5], VIN > VIH or VIN < VIL, f = fMAX Max VCC, CE > VCC – 0.2 V [5], VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0 mA Notes 4. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 2 ns. 5. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V), VCC = 3 V (for a VCC range of 2.2 V–3.6 V), and VCC = 5 V (for a VCC range of 4.5 V–5.5 V), TA = 25 °C. Document Number: 001-88702 Rev. *C Page 6 of 19 CY7C10612G CY7C10612GE PRELIMINARY Capacitance Parameter [6] Description CIN Input Capacitance COUT I/O Capacitance Test Conditions 54-pin TSOP II Unit TA = 25 C, f = 1 MHz, VCC = 3.3 V 10 pF Thermal Resistance Parameter [6] Description JA Thermal Resistance (junction to ambient) JC Thermal Resistance (junction to case) Test Conditions 54-pin TSOP II Unit Still air, soldered on a 3 × 4.5 inch, four layer printed circuit board 93.63 C/W 21.58 AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms [7] HIGH Z CHARACTERISTICS: R1 317 3.3 V 50 VTH = 1.5 V OUTPUT Z0 = 50 OUTPUT 30 pF* 5 pF* INCLUDING JIG AND SCOPE (b) (a) * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT R2 351 ALL INPUT PULSES 3.0 V GND 90% 90% 10% RISE TIME: > 1 V/ns 10% (c) FALL TIME: > 1 V/ns Notes 6. Tested initially and after any design or process changes that may affect these parameters. 7. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC (min) and 100-µs wait time after VCC stabilizes to its operational value. Document Number: 001-88702 Rev. *C Page 7 of 19 CY7C10612G CY7C10612GE PRELIMINARY Data Retention Characteristics Over the Operating Range –45 C to 85 C Parameter Description Conditions Min Typ [8] Max Unit – 1.0 – – V – – 30.0 mA VDR VCC for Data Retention ICCDR Data Retention Current tCDR [9] Chip Deselect to Data Retention Time – 0.0 – – Operation Recovery Time – 10.0 – – tR [9, 10] VCC = 2 V, CE VCC – 0.2 V, VIN VCC – 0.2 V or VIN 0.2 V ns Data Retention Waveform Figure 4. Data Retention Waveform DATA RETENTION MODE VCC 3.0 V tCDR VDR > 1 V 3.0 V tR CE Notes 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 9. This parameter is guaranteed by design and is not tested. 10. Full device operation requires linear VCC ramp from VDR to VCC(min.) 100 s or stable at VCC(min.) 100 s. Document Number: 001-88702 Rev. *C Page 8 of 19 CY7C10612G CY7C10612GE PRELIMINARY AC Switching Characteristics Over the Operating Range Parameter [11] Description -10 Min Max Unit Read Cycle tPOWER VCC to the first access [12] 100.0 – tRC Read cycle time 10.0 – tAA Address to data valid – 10.0 tOHA Data hold from address change 3.0 – tACE CE LOW to data valid – 10.0 tDOE OE LOW to data valid – 5.0 0.0 – – 5.0 3.0 – – 5.0 0.0 – – 10.0 tLZOE tHZOE OE LOW to low Z[13, 14, 15] OE HIGH to high Z [13, 14, 15] [13, 14, 15] tLZCE CE LOW to low Z tHZCE CE HIGH to high Z [13, 14, 15] tPU CE LOW to power-up [16] [16] tPD CE HIGH to power-down tDBE Byte enable to data valid – 5.0 tLZBE Byte enable to low Z 1.0 – Byte disable to high Z – 6.0 tHZBE Write Cycle µs ns [17, 18] tWC Write cycle time 10.0 – tSCE CE LOW to write end 7.0 – tAW Address setup to write end 7.0 – tHA Address hold from write end 0.0 – tSA Address setup to write start 0.0 – tPWE WE pulse width 7.0 – tSD Data setup to write end 5.0 – tHD Data hold from write end 0.0 – [13, 14, 15] tLZWE WE HIGH to low Z tHZWE WE LOW to high Z [13, 14, 15] tBW Byte enable to end of write 3.0 – – 5.0 7.0 – ns Notes 11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use output loading shown in part a) of Figure 3 on page 7, unless specified otherwise. 12. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 13. tHZOE, tHZCE, tHZWE, tHZBE , tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 3 on page 7. Transition is measured 200 mV from steady state voltage. 14. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 15. Tested initially and after any design or process changes that may affect these parameters. 16. These parameters are guaranteed by design and are not tested. 17. The internal write time of the memory is defined by the overlap of WE, CE = VIL. Chip enable must be active and WE and byte enables must be LOW to initiate a write, and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 18. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 001-88702 Rev. *C Page 9 of 19 PRELIMINARY CY7C10612G CY7C10612GE Switching Waveforms Figure 5. Read Cycle No. 1 (Address Transition Controlled) for CY7C10612G [19, 20] tRC RC ADDRESS tOHA DATA I/O tAA PREVIOUS DATA VALID DATA OUT VALID Figure 6. Read Cycle No. 1 (Address Transition Controlled) for CY7C10612GE [20, 21] Notes 19. The device is continuously selected. OE, CE = VIL, BHE, BLE or both = VIL. 20. WE is HIGH for read cycle. 21. Address valid before or similar to CE transition LOW. Document Number: 001-88702 Rev. *C Page 10 of 19 CY7C10612G CY7C10612GE PRELIMINARY Switching Waveforms (continued) Figure 7. Read Cycle No. 2 (OE Controlled) [22, 23] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE tLZOE BHE/ BLE tDBE tLZBE DATA I/O HIGH IMPEDANCE tHZBE DATAOUT VALID HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU ISB Notes 22. WE is HIGH for read cycle. 23. Address valid before or similar to CE transition LOW. Document Number: 001-88702 Rev. *C Page 11 of 19 CY7C10612G CY7C10612GE PRELIMINARY Switching Waveforms (continued) Figure 8. Write Cycle No. 1 (CE Controlled) [24, 25, 26] tWC ADDRESS tSA CE tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA IN VALID DATA I/O Figure 9. Write Cycle No. 2 (WE Controlled, OE LOW) [24, 25, 26] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE DATA I/O Note 27 tSD tHD DATA IN VALID tLZWE Notes 24. Data I/O is high impedance if OE, BHE, and/or BLE = VIH. 25. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 26. The minimum write cycle pulse width should be equal to the sum of tHZWE and tSD. 27. During this period the I/Os are in output state. Do not apply input signals. Document Number: 001-88702 Rev. *C Page 12 of 19 CY7C10612G CY7C10612GE PRELIMINARY Switching Waveforms (continued) Figure 10. Write Cycle No. 3 (BLE or BHE Controlled) [28, 29] tWC ADDRESS tSA tBW BHE, BLE tAW tHA tPWE WE tSCE CE Note 30 DATA I/O tSD tHD DATA IN VALID Notes 28. Data I/O is high impedance if OE, BHE, and/or BLE = VIH. 29. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 30. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 001-88702 Rev. *C Page 13 of 19 CY7C10612G CY7C10612GE PRELIMINARY Truth Table I/O0–I/O7 I/O8–I/O15 Mode Power CE OE WE BLE BHE H X X X X High Z High Z Power-down Standby (ISB) L L H L L Data Out Data Out Read all bits Active (ICC) L L H L H Data Out High Z Read lower bits only Active (ICC) L L H H L High Z Data Out Read upper bits only Active (ICC) L X L L L Data In Data In Write all bits Active (ICC) L X L L H Data In High Z Write lower bits only Active (ICC) L X L H L High Z Data In Write upper bits only Active (ICC) L H H X X High Z High Z Selected, outputs disabled Active (ICC) ERR Output – CY7C10612GE Output [31] 0 1 High-Z Mode Read Operation, no error in the stored data. Read Operation, single-bit error detected and corrected. Device deselected or Outputs disabled or Write Operation. Note 31. ERR is an Output pin. If not used, this pin should be left floating. Document Number: 001-88702 Rev. *C Page 14 of 19 CY7C10612G CY7C10612GE PRELIMINARY Ordering Information Speed (ns) Ordering Code CY7C10612G30-10ZSXI 10 CY7C10612GE30-10ZSXI Package Diagram Package Type Operating Range 51-85160 54-pin TSOP II (Pb-free) Industrial Ordering Code Definitions CY 7 C 1 06 1 2 G E 30 - 10 ZS X I Temperature Grade: I = Industrial Pb-free Package Type: ZS = 54-pin TSOP II Speed Grade: 10 ns Voltage range: 3 V to 3.6 V ECC Process Technology: 65nm Single chip enable Bus width = × 16 Density = 16-Mbit Fast asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-88702 Rev. *C Page 15 of 19 PRELIMINARY CY7C10612G CY7C10612GE Package Diagrams Figure 11. 54-pin TSOP Type II (22.4 × 11.84 × 1.0 mm) Z54-II Package Outline, 51-85160 51-85160 *E Document Number: 001-88702 Rev. *C Page 16 of 19 CY7C10612G CY7C10612GE PRELIMINARY Acronyms Document Conventions Table 1. Acronyms Used in this Document Units of Measure Acronym Description Table 2. Units of Measure BHE Byte High Enable BLE Byte Low Enable °C degree Celsius CE Chip Enable MHz megahertz CMOS Complementary Metal Oxide Semiconductor µA microampere I/O Input/Output s microsecond OE Output Enable mA milliampere SRAM Static Random Access Memory mm millimeter TSOP Thin Small Outline Package mV millivolt TTL Transistor-Transistor Logic WE Write Enable Document Number: 001-88702 Rev. *C Symbol Unit of Measure ns nanosecond ohm % percent pF picofarad V volt W watt Page 17 of 19 CY7C10612G CY7C10612GE PRELIMINARY Document History Page Document Title: CY7C10612G/CY7C10612GE, 16-Mbit (1 M × 16) Static RAM Document Number: 001-88702 Rev. ECN No. Orig. of Change Submission Date ** 4104325 VINI 08/26/2013 New data sheet. *A 4525600 VINI 10/06/2014 Updated Features: Changed value of ISB2 from “10 mA typical” to “20 mA typical”. Replaced “1.5 V data retention” with “1 V data retention”. Updated Logic Block Diagram – CY7C10612GE. Updated Selection Guide: Changed value of Maximum CMOS Standby Current from 10 mA to 20 mA. Updated DC Electrical Characteristics: Added a column “Typ” and added details in that column. Added Note 5 and referred the same note in “Typ” column. Added Note 5 and referred the same note in Test Conditions of ISB1 and ISB2 parameters. Updated AC Switching Characteristics: Added tPOWER parameter and its details. Changed minimum value of tLZOE parameter from 1 ns to 0 ns. Updated Switching Waveforms: Removed Note “For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.” and its reference in Figure 7. Updated Package Diagrams: spec 51-85160 – Changed revision from *D to *E. Completing Sunset Review. Description of Change *B 4571739 VINI 11/16/2015 Added related documentation hyperlink in page 1. *C 4571766 NILE 02/12/2015 Updated Selection Guide: Changed value of Maximum Active current from 90 mA to 110 mA. Changed value of Maximum Standby current from 20 mA to 30 mA. Updated Pin Configurations: Added Note 3 and referred the same note in Figure 2. Updated Maximum Ratings: Updated ratings corresponding to “Supply Voltage on VCC Relative to GND”. Updated AC Test Loads and Waveforms: Updated Note 7. Updated Data Retention Characteristics: Updated Note 9. Referred Note 9 in tR parameter. Updated AC Switching Characteristics: Referred Note 12 in description of tPOWER parameter. Added Notes 14, 15 and referred the same notes in description of tLZOE, tHZOE, tLZCE, tHZCE, tLZWE, tHZWE parameters. Updated Switching Waveforms: Updated Note 25. Added Notes 26, 27 and referred the same notes in Figure 9. Added Notes 29, 30 and referred the same notes in Figure 10. Document Number: 001-88702 Rev. *C Page 18 of 19 PRELIMINARY CY7C10612G CY7C10612GE Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2013-2015. The information contained herein is subject to change without notice. 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Document Number: 001-88702 Rev. *C Revised February 12, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 19 of 19