Q3 - 2002

CYPRESS
QUALITY & RELIABILITY
2002 Q3 RELIABILITY REPORT
TABLE OF CONTENTS
1.0 OVERVIEW OF CYPRESS SEMICONDUCTOR TOTAL QUALITY
MANAGEMENT SYSTEM
2.0 EARLY FAILURE RATE SUMMARY
3.0 LONG TERM FAILURE RATE SUMMARY
4.0 PRESSURE COOKER TEST
5.0 HAST (Highly Accelerated Stress Test)
6.0 TEMPERATURE CYCLE
Note: All the results reported here are for Quarter 3 2002.
CYPRESS
QUALITY & RELIABILITY
1.0 OVERVIEW OF CYPRESS SEMICONDUCTOR TOTAL QUALITY MANAGEMENT SYSTEM
This report summarizes Cypress Semiconductor Product Reliability for the period of the 3rd quarter of
2002. It includes data from product fabricated at the San Jose, California; Round Rock, Texas; and
Bloomington, Minnesota facilities.
Cypress Semiconductor has established aggressive reliability objectives to assure that all products
exhibit reliability which exceeds customer reliability requirements for purchased components. The
quality standard at Cypress is zero defects resulting in a culture requiring continuous improvement in
quality and reliability.
Product reliability is assured by a total quality management system. The quality management system
is described in detail in the Cypress Semiconductor Quality Manual (Cypress Semiconductor
Document Number 90-00001). Key reliability-related programs of the total quality management
system are: (1) design rule review and approval; (2) control of raw materials and vendor quality; (3)
manufacturing statistical process controls; (4) manufacturing identification of "Maverick Lot" yield
limits; (5) formal training and certification of manufacturing personnel; (6) qualification of new products
and manufacturing processes; (7) continuous reliability monitoring; (8) formal failure analysis and
corrective action; and (9) competitive benchmarking.
Product Reliability data is accumulated as a result of new product Qualification Test Plan activities
(Cypress Semiconductor Document Number 25-00040) as well as from the Reliability Monitor Program
(Cypress Semiconductor Document Number 25-00008). All reliability test samples are obtained from
standard production material. Sample selection is based on generic product families. These generic
products are designed with very similar design rules and manufactured from a core set of processes.
Reliability strategy requires that every failure which occurs during reliability testing be subjected to
failure analysis (Cypress Semiconductor Document Number 25-00039) to determine the failure
mechanism. Corrective action is then implemented to prevent future failures, resulting in continuous
improvement in product reliability.
Copies of the Cypress Semiconductor documents referenced herein are available through your
Cypress Semiconductor sales representative. Questions about product reliability may be addressed to
the undersigned.
____________________
Director of Reliability
___________________
Director of Quality
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134-1599
Cypress Quality Fax: (408) 943-2165
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QUALITY & RELIABILITY
CYPRESS
2.0 EARLY FAILURE RATE SUMMARY
Early Failure Rate Determination: High Temperature Operating Life testing (HTOL), for as long as 96
hours, is used to estimate device early failure rate.
Test:
Conditions:
Duration:
Failure:
Fit Rate:
High Temperature Operating Life Test (HTOL)
Dynamic Operating Conditions, VCC nominal + 15%, 150°C or 125°C.
48 hours HTOL at 150°C or 96 hours at 125°C.
A failure is any device that fails to meet data sheet electrical requirements.
Derated to 55° C ambient, with 60% upper confidence bound for 0 failures,
Ea =0.7ev
Early Failure Rate Summary
Technology
# Failed
FIT Rate
B53
Device
Hours
244452
1
24
Ram 2
Rem 3
Ram 4
30774
49760
964998
0
0
2
12
Ram 5
3742711
6
9
Ram 6
Ram 7
495085
3745398
1
6
12
9
S4
TSMC 0.15
TSMC 0.18
TSMC 0.25
TSMC 0.50
275320
124565
56985
64126
62720
1
0
0
0
0
21
Note: Data reported is a 4 quarter rolling average.
Failure Mode
Transistor Breakdown (1
unit)
Insufficient Data
Insufficient Data
Polyamide Residue , No
anomaly
Poly residue (3 units)
Cause Unknown (3 units)
Multiple Bits
Cause Unknown (3 units)
Particle on LI (1 unit)
Metal Damage (1 unit)
Single Bit (1 unit)
Contact spike
Insufficient Data
Insufficient Data
Insufficient Data
Insufficient Data
QUALITY & RELIABILITY
CYPRESS
3.0 LONG TERM FAILURE RATE SUMMARY
Long Term Failure Rate Determination A High Temperature Operating Life test (HTOL) is used to
estimate long term reliability. By operating the devices at accelerated temperature and voltage,
hundreds of thousands of use hours can be compressed into hundreds of test hours.
Test:
High Temperature Operating Life Test (HTOL)
Conditions: Dynamic Operating Conditions, VCC nominal +15% 150°C or 125°C.
Duration: A minimum of 80 hours at 150°C or 168 hours at 125°C
Generally 500 hours at 150°C or 1000 hours at 125°C.
Failure:
A failure is any device that fails to meet data sheet electrical requirements.
Fit Rate:
Derated to 55° C ambient, with 60% upper confidence bound for 0 failures,
Ea =0.7ev
Long Term Failure Rate Summary
Technology
# Failed
FIT Rate
B53
Device
Hours
@150°c
874258
4
27
FL28
HYNIX 0.35
HYNIX P26
L28
P20
P26
Ram 2
Ram 3
Ram 4
Ram 5
Ram 6
Ram 7
S4
TSMC 0.15
TSMC 0.18
TSMC 0.25
TSMC 0.50
77500
75000
382456
139360
200315
50000
140167
241760
620530
2366513
1226011
4376984
226472
101721
111699
72258
177500
0
0
0
0
0
0
0
0
1
1
3
2
0
1
0
0
0
Note: Data reported is a 4 quarter rolling average.
14
27
39
22
9
3
14
3
24
58
30
Failure Mode
Excess Intemetallic
Cause Unknown
Insufficient Data
Insufficient Data
None
Insufficient Data
None
Insufficient Data
None
None
Excessive Intermetallics
Functional
Via Void
Short on VCC pins
None
Metal Short (1)
Insufficient Data
Insufficient Data
None
QUALITY & RELIABILITY
CYPRESS
4.0 PRESSURE COOKER TEST (PCT)
The Pressure Cooker Test is a highly accelerated packaging stress test used to ensure environmental
durability of epoxy packaged parts. Passivation cracks, ionic contamination and corrosion
susceptibility are all accelerated by this stress.
Test:
Conditions:
Pre-Conditioning:
Failure:
Pressure Cooker Test (PCT)
15 PSIG, 121°C, No bias, for a minimum of 168 hours.
5 cycles Temperature Cycles –65/+150, 24 hr Bake 125°C, Moisture loading
to qualified MSL level
A failure is any device that fails to meet data sheet electrical requirements.
Pressure Cooker Test Failure Rate Summary
Package
TQFP
BGA
FBGA (1.0)
PBGA (1.27)
FBGA (0.75)
PLCC
MLF
PQFP
PQFP
(Thermal)
SSOP
PDIP
SOIC
SOJ
TSOP
TSOPI
TSOPII
Sample
Size
1249
724
369
146
93
373
100
97
144
# Failed
Defects %
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Failure
Mode
None
None
None
None
None
None
None
None
None
1180
892
1016
703
1005
44
246
0
0
0
0
0
0
0
0
0
0
0
0
0
0
None
None
None
None
None
None
None
Note: Data reported is a 4 quarter rolling average.
QUALITY & RELIABILITY
CYPRESS
5.0 HIGHLY ACCELERATED STRESS TEST (HAST)
Cypress uses HAST to accelerate temperature, humidity, bias failure mechanisms. This change was
necessary because our package reliability had improved to the point where the old 85°C/85% R.H.
temperature-humidity-bias testing would not induce failures. Failures are necessary to judge progress
and compare packaging changes. HAST testing has been shown to be at least twenty times more
accelerated then 85°C/85% R.H. temperature-humidity-bias testing.
Test:
Conditions:
Highly Accelerated Stress Test (HAST)
Present Conditions: 130°C / 85% RH minimum power dissipation, for a
minimum of 128 hours.
Pre-Conditioning: 5 cycles Temperature Cycles –65/+150, 24 hr Bake 125°C, Moisture loading
to qualified MSL level
Failure:
A failure is any device that fails to meet data sheet electrical requirements.
Highly Accelerated Stress Test (HAST) Failure Rate Summary
Package
TQFP
FBGA (0.75-0.8)
FBGA (1.0)
PBGA (1.27)
VFBGA
PLCC
PQFP
PAFP (Thermal)
SSOP
PDIP
SOIC
SNC
SOJ
TSOP
TSOPI
TSOP (Reverse)
TSOP II
Sample
Size
842
626
237
98
49
224
45
46
240
45
479
432
470
486
91
43
360
# Failed
Defects %
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0.3%
Note: Data reported is a 4 quarter rolling average.
Failure
Mode
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Cut Wedge
QUALITY & RELIABILITY
CYPRESS
6.0 TEMPERATURE CYCLE TEST (TC)
Differences in thermal expansion coefficients are accentuated by cycling devices through temperature
extremes. If the materials do not expand and contract equally, large stresses can develop. The
Temperature Cycle test stresses mechanical integrity by exposing a device to alternating temperature
extremes. Weakness and thermal expansion mismatches in die interconnections, die attach, and wire
bonds are often detected with this acceleration test.
Test:
Condition:
Pre-Condition:
Duration:
Failure:
Temperature Cycle
MIL-STD -883D, Method 1010, Condition C, -65°C to 150°C.
JEDEC 22-A104 Condition B, -40°C to 125°C
5 cycles Temperature Cycles –65/+150, 24 hr Bake 125°C, Moisture loading
to qualified MSL level
300 cycles minimum at Condition C, 1000 cycles minimum at Condition B
A failure is any device that fails to meet data sheet electrical requirements.
Temperature Cycling Failure Rate Summary
Package
TQFP
TQFP(10X10)
TQFP (Thermal)
FBGA (0.75-0.8)
FBGA(1.0)
PBGA (1.27)
VFBGA
PLCC
MLF
PQFP
PQFP (Thermal)
SSOP
PDIP
SOIC
SNC
SOJ
TSOP
TSOPI
TSOPII
Sample
Size
1798
47
214
1029
969
391
143
380
148
96
305
1305
783
1405
683
959
1748
150
430
# Failed
Defects %
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0.4%
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Note: Data reported is a 4 quarter rolling average.
Failure
Mode
None
None
None
Cut Wedges
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None