QUALITY & RELIABILITY CYPRESS 2004 Q2 RELIABILITY REPORT TABLE OF CONTENTS 1.0 OVERVIEW OF CYPRESS SEMICONDUCTOR TOTAL QUALITY MANAGEMENT SYSTEM 2.0 EARLY FAILURE RATE SUMMARY 3.0 LONG TERM FAILURE RATE SUMMARY 4.0 PRESSURE COOKER TEST 5.0 HAST (Highly Accelerated Stress Test) 6.0 TEMPERATURE CYCLE Note: The results reported herein are for 2nd Quarter 2004. 2004 Q2 RELIABILITY REPORT Page 1 of 7 QUALITY & RELIABILITY CYPRESS 1. OVERVIEW OF CYPRESS SEMICONDUCTOR, INC. TOTAL QUALITY MANAGEMENT SYSTEM This report summarizes Cypress Semiconductor Product Reliability for the period of the 2nd quarter of 2004. It includes data from product fabricated at the San Jose, California; Round Rock, Texas; and Bloomington, Minnesota facilities. Cypress Semiconductor has established aggressive reliability objectives to assure that all products exhibit reliability, which exceeds customer reliability requirements for purchased components. The quality standard at Cypress is zero defects resulting in a culture requiring continuous improvement in quality and reliability. Product reliability is assured by a total quality management system. The quality management system is described in detail in the Cypress Semiconductor Quality Manual (Cypress Semiconductor Document Number 90-00001). Key reliability-related programs of the total quality management system are: (1) design rule review and approval; (2) control of raw materials and vendor quality; (3) manufacturing statistical process controls; (4) manufacturing identification of "Maverick Lot" yield limits; (5) formal training and certification of manufacturing personnel; (6) qualification of new products and manufacturing processes; (7) continuous reliability monitoring; (8) formal failure analysis and corrective action; and (9) competitive benchmarking. Product Reliability data is accumulated as a result of new product Qualification Test Plan activities (Cypress Semiconductor Document Number 25-00040) as well as from the Reliability Monitor Program (Cypress Semiconductor Document Number 25-00008). All reliability test samples are obtained from standard production material. Sample selection is based on generic product families. These generic products are designed with very similar design rules and manufactured from a core set of processes. Reliability strategy requires that every failure that occurs during reliability testing be subjected to failure analysis (Cypress Semiconductor Document Number 25-00039) to determine the failure mechanism. Corrective action is then implemented to prevent future failures, resulting in continuous improvement in product reliability. Copies of the Cypress Semiconductor documents referenced herein are available through your Cypress Semiconductor sales representative. Questions about product reliability may be addressed to the undersigned. Director of Reliability Director of Quality Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134-1599 Cypress Quality Fax: (408) 943-2165 2004 Q2 RELIABILITY REPORT Page 2 of 7 QUALITY & RELIABILITY CYPRESS 2. EARLY FAILURE RATE SUMMARY Early Failure Rate Determination: High Temperature Operating Life testing (HTOL), for as long as 96 hours, is used to estimate device early failure rate. Test: Conditions: Duration: Failure: Fit Rate: High Temperature Operating Life Test (HTOL) Dynamic Operating Conditions, VCC nominal + 15%, 150°C or 125°C. 48 hours HTOL at 150°C or 96 hours at 125°C. A failure is any device that fails to meet data sheet electrical requirements. Derated to 55° C ambient, with 60% upper confidence bound for 0 failures, Ea =0.7ev Early Failure Rate Summary Technology B5 HYNIX P26 L28 NEC 0.25 P20 PROMOS R28 R42 R52 R6 R7 Device Hours 209,791 36,790 23,904 72,000 80,998 46 257,638 195,371 1,330,648 4,800 1,720,165 # Failed 0 0 0 0 0 0 0 0 0 0 3 FIT Rate 26 Insufficient Insufficient Insufficient Insufficient Insufficient 21 28 4 Insufficient 7 R8 1,764,404 2 5 S4 STARM TOWER .165 TSMC 0.15 TSMC 0.18 431,197 35,226 432,079 90,890 31,401 0 0 0 0 0 12 Insufficient 12 Insufficient Insufficient Failure Mechanism None None None None None None None None None None 1 - Polyprotrusion 1 - Nitride Particle 1 - Non-visual 1 - Polyprotrusion 1 - Non-visual None None None None None Notes: Data reported is a 4-quarter rolling average. Insufficient data – interpret as insufficient accumulated life-time hours to project a 60% confidence bound for a zero-fails sample. 2004 Q2 RELIABILITY REPORT Page 3 of 7 QUALITY & RELIABILITY CYPRESS 3. LONG TERM FAILURE RATE SUMMARY Long Term Failure Rate Determination A High Temperature Operating Life test (HTOL) is used to estimate long-term reliability. By operating the devices at accelerated temperature and voltage, hundreds of thousands of use hours can be compressed into hundreds of test hours. Test: High Temperature Operating Life Test (HTOL) Conditions: Dynamic Operating Conditions, VCC nominal +15% 150°C or 125°C. Duration: A minimum of 80 hours at 150°C or 168 hours at 125°C Generally 500 hours at 150°C or 1000 hours at 125°C. Failure: A failure is any device that fails to meet data sheet electrical requirements. Fit Rate: Derated to 55° C ambient, with 60% upper confidence bound for 0 failures, Ea =0.7ev Long Term Failure Rate Summary Technology B5 L28 NEC 0.25 P20 PROMOS R28 R42 R52 R6 R7 R8 S4 STARM TOWER .165 TSMC 0.18 Device Hours 232,085 150,000 108,052 70,893 471,820 628,729 626,409 665,435 75,000 2,423,620 1,539,413 403,726 106,782 373,871 78,039 # Failed 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIT Rate 23 36 Insufficient Insufficient 11 9 9 8 Insufficient 2 3 13 Insufficient 14 Insufficient Failure Mechanism None None None None None None None None None None None None None None None Notes: Data reported is a 4-quarter rolling average. Insufficient data – interpret as insufficient accumulated life-time hours to project a 60% confidence bound for a zero-fails sample 2004 Q2 RELIABILITY REPORT Page 4 of 7 QUALITY & RELIABILITY CYPRESS 4. PRESSURE COOKER TEST (PCT) The Pressure Cooker Test is a highly accelerated packaging stress test used to ensure environmental durability of epoxy-packaged parts. Passivation cracks, ionic contamination, and corrosion susceptibility are all accelerated by this stress. Test: Conditions: Pre-Conditioning: Failure: Pressure Cooker Test (PCT) 15 PSIG, 121°C, No bias, for a minimum of 168 hours. 5 cycles Temperature Cycles –65/+150, 24 hr Bake 125°C, Moisture loading to qualified MSL level A failure is any device that fails to meet data sheet electrical requirements. Pressure Cooker Test Failure Rate Summary Package BV (24 ) FBGA (0.75-0.8) FBGA (1.0) PBGA (1.27) PBGA (Cavity/Heatsink) PDIP PLCC PQFP QFN (Punch Type) SOIC (Gull Wing, Exposed Pad) SOIC (GullWing) SOIC (GullWing, 450 footprint) SOIC (J lead) SSOP TQFP (10x10) TQFP TQFP (Thermal) TSOP (Exposed Pad) TSOP I TSOP II TSOP/ TSSOP TSSOP (Pb-Free) Sample Size 1,267 595 564 179 47 815 808 332 149 135 1,596 419 936 971 147 1,841 134 92 98 400 1,189 50 # Failed 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 Defect % 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% Failure Mechanism 1 - Non-visual None None None None None None None None None None None None 2 - Non-visual None None None None None None None None Note: Data reported is a 4-quarter rolling average. 2004 Q2 RELIABILITY REPORT Page 5 of 7 QUALITY & RELIABILITY CYPRESS 5. HIGHLY ACCELERATED STRESS TEST (HAST) Cypress uses HAST to accelerate temperature, humidity, bias failure mechanisms. This change was necessary because our package reliability had improved to the point where the old 85°C/85% R.H. Temperature-humidity-bias testing would not induce failures. Failures are necessary to judge progress and compare packaging changes. HAST testing has been shown to be at least twenty times more accelerated then 85°C/85% R.H. temperature-humidity-bias testing. Test: Conditions: Highly Accelerated Stress Test (HAST) Present Conditions: 130°C / 85% RH minimum power dissipation, for a minimum of 128 hours. Pre-Conditioning: 5 cycles Temperature Cycles –65/+150, 24 hr Bake 125°C, Moisture loading to qualified MSL level Failure: A failure is any device that fails to meet data sheet electrical requirements. Highly Accelerated Stress Test (HAST) Failure Rate Summary Package TQFP (10x10) TQFP TQFP (Thermal) FBGA (0.75-0.8) FBGA (1.0) BV PLCC QFN (Punch PQFP SSOP PDIP SOIC (GullWing) SOIC (Gull Wing, Exposed Pad) SOIC (GullWing, 450 footprint) SOIC (J lead) TSOP/ TSSOP TSOP I TSSOP (Pb-Free) Sample Size 1,069 143 90 445 96 798 523 98 100 541 428 1,280 195 357 757 989 100 332 # Failed 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Defect % 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% Failure Mechanism None None None None None None None None None None None None None None None None None None Note: Data reported is a 4-quarter rolling average. 2004 Q2 RELIABILITY REPORT Page 6 of 7 QUALITY & RELIABILITY CYPRESS 6. TEMPERATURE CYCLE TEST (TC) Differences in thermal expansion coefficients are accentuated by cycling devices through temperature extremes. If the materials do not expand and contract equally, large stresses can develop. The Temperature Cycle test stresses mechanical integrity by exposing a device to alternating temperature extremes. Weakness and thermal expansion mismatches in die interconnections, die attach, and wire bonds are often detected with this acceleration test. Test: Condition: Pre-Condition: Duration: Failure: Temperature Cycle MIL-STD-883D, Method 1010, Condition C, -65°C to 150°C. JEDEC 22-A104 Condition B, -40°C to 125°C 5 cycles Temperature Cycles –65/+150, 24 hr Bake 125°C, Moisture loading to qualified MSL level 300 cycles minimum at Condition C, 1000 cycles minimum at Condition B A failure is any device that fails to meet data sheet electrical requirements. Temperature Cycling Failure Rate Summary Package BV FBGA (0.75-0.8) FBGA (1.0) PBGA (1.27) PBGA (Cavity/Heatsink) PDIP PDIP (Pb-Free) PLCC PQFP PQFP (Thermal) QFN (Punch Type) SOIC (Gull Wing, Exposed Pad) SOIC (GullWing) SOIC (GullWing, 450 footprint) SOIC (J lead) SSOP TQFP (10x10) TQFP TQFP (Thermal) TSOP (Exposed Pad) TSOP (Reverse) TSOP I TSOP II TSOP/ TSSOP TSSOP (Pb-Free) Sample Size 1,329 935 769 189 142 761 100 911 367 100 266 343 2,128 421 990 1,307 143 2,615 182 94 50 100 473 1,663 50 # Failed 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Defect % 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% Failure Mechanism None None None None None None None 1- PO Metal Crack None None None None None None None None None None None None None None None None None Note: Data reported is a 4-quarter rolling average. 2004 Q2 RELIABILITY REPORT Page 7 of 7