Q2 - 2003

CYPRESS
QUALITY & RELIABILITY
2003 Q2 RELIABILITY REPORT
TABLE OF CONTENTS
1.0 OVERVIEW OF CYPRESS SEMICONDUCTOR TOTAL QUALITY
MANAGEMENT SYSTEM
2.0 EARLY FAILURE RATE SUMMARY
3.0 LONG TERM FAILURE RATE SUMMARY
4.0 PRESSURE COOKER TEST
5.0 HAST (Highly Accelerated Stress Test)
6.0 TEMPERATURE CYCLE
Note: The results reported herein are for 2nd Quarter 2003.
CYPRESS
QUALITY & RELIABILITY
1.0 OVERVIEW OF CYPRESS SEMICONDUCTOR TOTAL QUALITY MANAGEMENT SYSTEM
This report summarizes Cypress Semiconductor Product Reliability for the period of the 2nd quarter of
2003. It includes data from product fabricated at the San Jose, California; Round Rock, Texas; and
Bloomington, Minnesota facilities.
Cypress Semiconductor has established aggressive reliability objectives to assure that all products
exhibit reliability, which exceeds customer reliability requirements for purchased components. The
quality standard at Cypress is zero defects resulting in a culture requiring continuous improvement in
quality and reliability.
Product reliability is assured by a total quality management system. The quality management system
is described in detail in the Cypress Semiconductor Quality Manual (Cypress Semiconductor
Document Number 90-00001). Key reliability-related programs of the total quality management
system are: (1) design rule review and approval; (2) control of raw materials and vendor quality; (3)
manufacturing statistical process controls; (4) manufacturing identification of "Maverick Lot" yield
limits; (5) formal training and certification of manufacturing personnel; (6) qualification of new products
and manufacturing processes; (7) continuous reliability monitoring; (8) formal failure analysis and
corrective action; and (9) competitive benchmarking.
Product Reliability data is accumulated as a result of new product Qualification Test Plan activities
(Cypress Semiconductor Document Number 25-00040) as well as from the Reliability Monitor Program
(Cypress Semiconductor Document Number 25-00008). All reliability test samples are obtained from
standard production material. Sample selection is based on generic product families. These generic
products are designed with very similar design rules and manufactured from a core set of processes.
Reliability strategy requires that every failure that occurs during reliability testing be subjected to failure
analysis (Cypress Semiconductor Document Number 25-00039) to determine the failure mechanism.
Corrective action is then implemented to prevent future failures, resulting in continuous improvement
in product reliability.
Copies of the Cypress Semiconductor documents referenced herein are available through your
Cypress Semiconductor sales representative. Questions about product reliability may be addressed to
the undersigned.
____________________
Director of Reliability
___________________
Director of Quality
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134-1599
Cypress Quality Fax: (408) 943-2165
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
QUALITY & RELIABILITY
CYPRESS
2.0 EARLY FAILURE RATE SUMMARY
Early Failure Rate Determination: High Temperature Operating Life testing (HTOL), for as long as 96
hours, is used to estimate device early failure rate.
Test:
Conditions:
Duration:
Failure:
Fit Rate:
High Temperature Operating Life Test (HTOL)
Dynamic Operating Conditions, VCC nominal + 15%, 150°C or 125°C.
48 hours HTOL at 150°C or 96 hours at 125°C.
A failure is any device that fails to meet data sheet electrical requirements.
Derated to 55° C ambient, with 60% upper confidence bound for 0 failures,
Ea =0.7ev
Early Failure Rate Summary
Technology
B5
FL28
L28
NEC 0.25
P20
P26
Promos .17
R28
R32
R42
R52
Device Hours
237,545
24,906
50,104
122,700
20,075
15,456
292,706
253,172
359,216
294,152
1,589,385
# Failed
1
0
0
0
0
0
1
0
0
0
6
FIT Rate
41
Insufficient
Insufficient
Insufficient
Insufficient
Insufficient
62
21
15
18
27
R6
R7
191,009
2,570,421
0
3
28
10
R8
885,795
3
28
S4
TO15
TSMC 0.15
TSMC 0.18
TSMC 0.25
TSMC 0.50
399,386
72,960
97,200
33,244
146,160
308,224
1
0
0
0
0
0
30
Insufficient
Insufficient
Insufficient
37
17
Failure Mode
(1 unit) particle
None
None
None
None
None
(1 unit) non-visual
None
None
None
(3 units) poly protrusion
(2 units) unknown
(1 unit) scratched metal line
None
(2 units) poly protrusion
(1 unit) particle
(2 units) non-visual
(1 unit) ILD crack
(1 unit) non-visual
None
None
None
None
None
Notes: Data reported is a 4-quarter rolling average.
Insufficient data – interpret as insufficient accumulated life-time hours to project a 60%
confidence bound for a zero-fails sample.
QUALITY & RELIABILITY
CYPRESS
3.0 LONG TERM FAILURE RATE SUMMARY
Long Term Failure Rate Determination A High Temperature Operating Life test (HTOL) is used to
estimate long-term reliability. By operating the devices at accelerated temperature and voltage,
hundreds of thousands of use hours can be compressed into hundreds of test hours.
Test:
High Temperature Operating Life Test (HTOL)
Conditions: Dynamic Operating Conditions, VCC nominal +15% 150°C or 125°C.
Duration: A minimum of 80 hours at 150°C or 168 hours at 125°C
Generally 500 hours at 150°C or 1000 hours at 125°C.
Failure:
A failure is any device that fails to meet data sheet electrical requirements.
Fit Rate:
Derated to 55° C ambient, with 60% upper confidence bound for 0 failures,
Ea =0.7ev
Long Term Failure Rate Summary
Technology
B5
FL28
L28
NEC
P20
P26
Promos 0.17
R28
R32
R42
R52
R6
Device Hours
@150°c
600,404
94,655
128,032
227,316
105,525
84,000
947,440
200,000
199,160
1,091,788
1,683,105
568,267
# Failed
FIT Rate
Failure Mode
0
0
0
0
0
0
0
0
0
0
1
0
9
Insufficient
Insufficient
24
Insufficient
Insufficient
6
27
27
5
7
9
None
None
None
None
None
None
None
None
None
None
(1 unit)
None
(1 unit)
(1 unit)
(2 units)
(4 units)
(1 unit)
None
None
None
None
R7
1,940,849
2
9
R8
S4
TO15
TSMC 0.18
TSMC 0.25
TSMC 0.50
1,940,100
533,712
182,460
116,426
119,000
458,000
6
1
0
0
0
0
22
22
30
Insufficient
Insufficient
12
non-visual
blocked contact
poly protrusion
poly protrusion
non-visual
non-visual
Notes: Data reported is a 4-quarter rolling average.
Insufficient data – interpret as insufficient accumulated lifetime hours to project a 60%
confidence bound for a zero-fails sample.
QUALITY & RELIABILITY
CYPRESS
4.0 PRESSURE COOKER TEST (PCT)
The Pressure Cooker Test is a highly accelerated packaging stress test used to ensure environmental
durability of epoxy-packaged parts.
Passivation cracks, ionic contamination, and corrosion
susceptibility are all accelerated by this stress.
Test:
Conditions:
Pre-Conditioning:
Failure:
Pressure Cooker Test (PCT)
15 PSIG, 121°C, No bias, for a minimum of 168 hours.
5 cycles Temperature Cycles –65/+150, 24 hr Bake 125°C, Moisture loading
to qualified MSL level
A failure is any device that fails to meet data sheet electrical requirements.
Pressure Cooker Test Failure Rate Summary
Package
Sample Size # Failed
Defects %
Failure Mode
FBGA (0.75-0.8)
947
0
0
None
FBGA (1.0)
194
0
0
None
MLF (3 )
148
0
0
None
PBGA
96
0
0
None
PDIP
550
0
0
None
PLCC
858
0
0
None
PQFP
295
0
0
None
SOIC (GullWing)
1021
0
0
None
SOIC (GullWing,
300)
SOIC (J)
285
0
0
None
668
0
0
None
SSOP
1435
1
0.1
(1 unit) cut wedge
T
90
0
0
None
TQFP (10x10)
50
0
0
None
TQFP
1096
0
0
None
TQFP (Thermal)
148
0
0
None
TSOP
1013
0
0
None
TSOP (Reverse)
48
0
0
None
TSOP I
138
0
0
None
TSOP II
323
0
0
None
Unknown (1 )
45
0
0
None
Unknown (2 )
94
0
0
None
VFBGA (0.75-0.8)
142
0
0
None
ZE
97
0
0
None
Note: Data reported is a 4-quarter rolling average.
QUALITY & RELIABILITY
CYPRESS
5.0 HIGHLY ACCELERATED STRESS TEST (HAST)
Cypress uses HAST to accelerate temperature, humidity, bias failure mechanisms. This change was
necessary because our package reliability had improved to the point where the old 85°C/85% R.H.
Temperature-humidity-bias testing would not induce failures. Failures are necessary to judge
progress and compare packaging changes. HAST testing has been shown to be at least twenty times
more accelerated then 85°C/85% R.H. temperature-humidity-bias testing.
Test:
Conditions:
Highly Accelerated Stress Test (HAST)
Present Conditions: 130°C / 85% RH minimum power dissipation, for a
minimum of 128 hours.
Pre-Conditioning: 5 cycles Temperature Cycles –65/+150, 24 hr Bake 125°C, Moisture loading
to qualified MSL level
Failure:
A failure is any device that fails to meet data sheet electrical requirements.
Highly Accelerated Stress Test (HAST) Failure Rate Summary
Package
Sample Size # Failed
Defects %
Failure Mode
TQFP
546
0
0
None
TQFP (10x10)
231
1
0.4
(1 unit) lifted ball bond
TQFP (Thermal)
141
0
0
None
FBGA (0.75-0.8)
696
1
0.1
(1unit) die crack
FBGA (1.0)
94
0
0
None
FBGA
85
0
0
None
VFBGA (0.75-0.8)
91
0
0
None
PLCC
519
0
0
None
MLF
100
0
0
None
PQFP
45
0
0
None
SSOP
537
0
0
None
PDIP
100
0
0
None
SOIC (GullWing)
808
0
0
None
SOIC (GullWing, 300) 275
0
0
None
SOIC (J)
419
0
0
None
TSOP
366
0
0
None
TSOP I
136
0
0
None
TSOP (Reverse)
37
0
0
None
TSOP II
355
1
0.3
(1 unit) cut wedge & lifted
ball bond
Note: Data reported is a 4-quarter rolling average.
QUALITY & RELIABILITY
CYPRESS
6.0 TEMPERATURE CYCLE TEST (TC)
Differences in thermal expansion coefficients are accentuated by cycling devices through temperature
extremes. If the materials do not expand and contract equally, large stresses can develop. The
Temperature Cycle test stresses mechanical integrity by exposing a device to alternating temperature
extremes. Weakness and thermal expansion mismatches in die interconnections, die attach, and wire
bonds are often detected with this acceleration test.
Test:
Condition:
Pre-Condition:
Duration:
Failure:
Temperature Cycle
MIL-STD-883D, Method 1010, Condition C, -65°C to 150°C.
JEDEC 22-A104 Condition B, -40°C to 125°C
5 cycles Temperature Cycles –65/+150, 24 hr Bake 125°C, Moisture loading
to qualified MSL level
300 cycles minimum at Condition C, 1000 cycles minimum at Condition B
A failure is any device that fails to meet data sheet electrical requirements.
Temperature Cycling Failure Rate Summary
Package
# Failed
Defects %
Failure Mode
FBGA (0.75-0.8)
Sample
Size
1485
4
0.3
(4 units) cut wedge
FBGA (1.0)
392
0
0
None
MLF
300
0
0
None
PBGA
190
0
0
None
PDIP
783
0
0
None
PLCC
865
0
0
None
PQFP
192
0
0
None
SOIC (GullWing)
1312
0
0
None
SOIC (GullWing, 300)
375
0
0
None
SOIC (J)
758
0
0
None
SSOP
1805
0
0
None
TQFP (10x10)
49
0
0
None
TQFP
1392
0
0
None
TQFP (Thermal)
200
0
0
None
TSOP
1600
0
0
None
TSOP (Reverse)
146
0
0
None
TSOP I
245
0
0
None
TSOP II
591
0
0
None
VFBGA (0.75-0.8)
137
0
0
None
VFBGA (0.75-0.8)
270
0
0
None
ZE
98
0
0
None
Note: Data reported is a 4-quarter rolling average.