QUALITY & RELIABILITY CYPRESS 2001 Q3 RELIABILITY REPORT TABLE OF CONTENTS 1.0 OVERVIEW OF CYPRESS MANAGEMENT SYSTEM SEMICONDUCTOR 2.0 EARLY FAILURE RATE SUMMARY 2.1 Early Failure Rate Determination 3.0 LONG TERM FAILURE RATE SUMMARY 3.1 Long Term Failure Rate Determination 4.0 PROCESS ENVIRONMENTAL TESTS 4.1 Pressure Cooker Test (PCT) 4.2 Highly Accelerated Stress Test (HAST) 4.3 Temperature Cycle Test (TC) Note: All the results reported here are for Quarter 3 2001. TOTAL QUALITY CYPRESS QUALITY & RELIABILITY 1.0 OVERVIEW OF CYPRESS SEMICONDUCTOR TOTAL QUALITY MANAGEMENT SYSTEM This report summarizes Cypress Semiconductor Product Reliability for the period of the 3rd quarter of 2001. Cypress Semiconductor has established aggressive reliability objectives to assure that all products exhibit reliability which exceeds customer reliability requirements for purchased components. In addition, the quality standard at Cypress is zero defects which results in a culture requiring continuous improvement in quality and reliability. This report includes data from product fabricated at the San Jose, California; Round Rock, Texas; and Bloomington, Minnesota facilities. Product reliability is assured by a total quality management system. The quality management system is described in detail in the Cypress Semiconductor Quality Manual (Cypress Semiconductor Document Number 90-00001). Key reliability-related programs of the total quality management system are: (1) design rule review and approval; (2) control of raw materials and vendor quality; (3) manufacturing statistical process controls; (4) manufacturing identification of "Maverick Lot" yield limits; (5) formal training and certification of manufacturing personnel; (6) qualification of new products and manufacturing processes; (7) continuous reliability monitoring; (8) formal failure analysis and corrective action; and (9) competitive benchmarking. Product Reliability data is accumulated as a result of new product Qualification Test Plan activities (Cypress Semiconductor Document Number 25-00040) as well as from the Reliability Monitor Program (Cypress Semiconductor Document Number 25-00008). All reliability test samples are obtained from standard production material. Sample selection is based on generic product families. These generic products are designed with very similar design rules and manufactured from a core set of processes. Reliability strategy requires that every failure which occurs during reliability testing be subjected to failure analysis (Cypress Semiconductor Document Number 25-00039) to determine the failure mechanism. Corrective action is then implemented to prevent future failures. The result is continuous improvement in product reliability. Copies of the Cypress Semiconductor documents referenced herein are available through your Cypress Semiconductor sales representative. Questions about product reliability may be addressed to the undersigned. Director of Reliability Director of Quality Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134-1599 Cypress Quality Fax: (408) 943-2165 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- QUALITY & RELIABILITY CYPRESS 2.0 EARLY FAILURE RATE SUMMARY 2.1 Early Failure Rate Determination High Temperature Operating Life testing (HTOL), for as long as 96 hours, is used to estimate device early failure rate. Test: High Temperature Operating Life Test (HTOL) Conditions: Dynamic Operating Conditions, VCC nominal + 15%, 150°C or 125°C. Duration: Early Failure Rate samples are tested 48 hours HTOL at 150°C (EFR) or up to 96 hours at 125°C (EFR2). Failure: A failure is any device that fails to meet data sheet electrical requirements. Fit Rate: Derated to 55° C ambient, with 60% upper confidence bound for 0 failures, Ea =0.7ev Early Failure Rate Summary Technology Device Hours 173656 88831 # Failed Ram 2 Ram 4 436447 1768238 0 4 31 Insufficient Data 12.3 13.3 Ram 5 5908077 16 15.9 Ram 6 77280 0 Ram 7 0.25 um 0.25 WT 208413 202575 93654 0 0 0 ATMEL355 S4 140736 224321 0 2 Insufficient Data 25.9 26.6 Insufficient Data 38.3 52.4 CLO15LP 92996 0 HYNIX P26 P26 FIT Rate 0 0 Insufficient Data Failure Mode None None None Blocked LIContact Poly defects, Scratches, Single bit None None None None None Missing L1 Contact None Note: Data reported is a 4 quarter rolling average. 3.0 LONG TERM FAILURE RATE SUMMARY 3.1 Long Term Failure Rate Determination A High Temperature Operating Life test (HTOL) is used to estimate long term reliability. By operating the devices at accelerated temperature and voltage, hundreds of thousands of use hours can be compressed into hundreds of test hours. Test: High Temperature Operating Life Test (HTOL) Conditions: Dynamic Operating Conditions, VCC nominal +15% 150°C or 125°C. Duration: A minimum of 80 hours at 150°C or 168 hours at 125°C. Tested to 500 hours at 150°C or 1000 hours at 125°C. Failure: A failure is any device that fails to meet data sheet electrical requirements. Fit Rate: Derated to 55° C ambient, with 60% upper confidence bound for 0 failures, QUALITY & RELIABILITY CYPRESS Ea =0.7ev Long Term Failure Rate Summary Technology Device Hours @150°c 141000 # Failed FL28 75000 0 HYNIX P26 P26 Ram 2 Ram 3 Ram 4 Ram 5 TSMC 0.50 Ram 6 Ram 7 0.25 um 0.5 um 0.65 um 323473 304113 288235 506871 1497158 3758830 238996 764440 782265 1101625 119000 75000 1 0 0 0 0 8 0 2 1 1 0 0 Atmel355 B53 CLO15LP S4 1995840 423199 581060 591360 0 0 1 1 CMOS FIT Rate 0 Insufficient Data Insufficient Data 18.2 17.7 18.7 10.6 3.6 12.5 22.6 15.4 7.5 7.5 22.6 Insufficient Data 2.7 12.7 10.1 9.9 Failure Mode None None Pin Leakage None None None None Poly Defects None None Single Bit Single Bit None None None None Metal Short Poly Defect Note: Data reported is a 4 quarter rolling average. 4.0 PROCESS ENVIRONMENTAL TESTS Cypress Semiconductor Reliability qualifies and continuously monitors packaging reliability to ensure exceptional resistance to environmental stress. Package reliability stress testing and failure rates are summarized in the following section. 4.1 Pressure Cooker Test (PCT) Test: Pressure Cooker Test (PCT) Conditions: 15 PSIG, 121°C, No bias, for a minimum of 168 hours. Pre-Conditioning: 5 cycles Temperature Cycles –65/+150, 24 hr Bake 125°C, Moisture loading to qualified MSL level Purpose: The Pressure Cooker Test is a highly accelerated packaging stress test used to ensure environmental durability of epoxy packaged parts. Passivation cracks, ionic contamination and corrosion susceptibility are all accelerated by this stress. Failure: A failure is any device that fails to meet data sheet QUALITY & RELIABILITY CYPRESS electrical requirements. Pressure Cooker Test Failure Rate Summary Package # Failed TQFP PPGA PLCC PQFP SSOP PDIP SOIC SOJ Sample Size 1457 1151 708 603 540 596 1411 1308 Defects % 0 4 0 0 0 0 0 3 0 0.34 0 0 0 0 0 0.22 TSOP 1252 0 0 Failure Mode None Cratering None None None None None Top side damage None Note: Data reported is a 4 quarter rolling average. 4.2 Highly Accelerated Stress Test (HAST) Cypress uses HAST to accelerate temperature, humidity, bias failure mechanisms. This change was necessary because our package reliability had improved to the point where the old 85°C/85% R.H. temperature-humidity-bias testing would not induce failures. Failures are necessary to judge progress and compare packaging changes. HAST testing has been shown to be at least twenty times more accelerated then 85°C/85% R.H. temperature-humidity-bias testing. Test: Conditions: Highly Accelerated Stress Test (HAST) Present Conditions: 130°C / 85% RH minimum power dissipation, for a minimum of 128 hours. Pre-Conditioning: 5 cycles Temperature Cycles –65/+150, 24 hr Bake 125°C, Moisture loading to qualified MSL level Purpose: HAST is an accelerated biased humidity test that provides an acceleration of at least 20 over 85°C/85% R.H. temperature-humidity bias testing. This test provides rapid feedback regarding the quality of the epoxy package process. Failure: A failure is any device that fails to meet data sheet electrical requirements. Highly Accelerated Stress Test (HAST) Failure Rate Summary Package TQFP PPGA PLCC PQFP SSOP PDIP SOIC SOJ TSOP Sample Size 1127 428 622 285 295 50 1112 1132 711 # Failed 0 0 0 0 0 0 0 0 5 Defects % 0 0 0 0 0 0 0 0 0.7 Failure Mode None None None None None None None None Pad Corrosion QUALITY & RELIABILITY CYPRESS Note: Data reported is a 4 quarter rolling average. 4.3 Temperature Cycle Test (TC) Differences in thermal expansion coefficients are accentuated by cycling devices through temperature extremes. If the materials do not expand and contract equally, large stresses can develop. Test: Condition: Pre-Condition: Purpose: Duration: Failure: Temperature Cycle MIL-STD-883D, Method 1010, Condition C, -65°C to 150°C. JEDEC 22-A104 Condition B, -40°C to 125°C 5 cycles Temperature Cycles –65/+150, 24 hr Bake 125°C, Moisture loading to qualified MSL level The Temperature Cycle test stresses mechanical integrity by exposing a device to alternating temperature extremes. Weakness and thermal expansion mismatches in die interconnections, die attach, and wire bonds are often detected with this acceleration test. 300 cycles minimum at Condition C, 1000 cycles minimum at Condition B A failure is any device that fails to meet data sheet electrical requirements. Temperature Cycling Failure Rate Summary Package # Failed TQFP PPGA PLCC PQFP Sample Size 2226 2129 509 960 Defects % 0 0 0 6 0 0 0 0.62 SSOP PDIP SOIC 756 630 2169 0 0 2 0 0 0.09 SOJ TSOP 1515 1966 5 1 0.33 0.05 Note: Data reported is a 4 quarter rolling average. Failure Mode None None None Broken Bonds None None Top side crack Wedge cut Poly particles