INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT534 Octal D-type flip-flop; positive edge-trigger; 3-state; inverting Product specification Supersedes data of September 1993 File under Integrated Circuits, IC06 1998 Apr 10 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state; inverting 74HC/HCT534 The 74HC/HCT534 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and inverting 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. FEATURES • 3-state inverting outputs for bus oriented applications • 8-bit positive, edge-triggered register • Common 3-state output enable input • Output capability: bus driver The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. • ICC category: MSI. GENERAL DESCRIPTION The 74HC/HCT534 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The “534” is functionally identical to the “374”, but has inverted outputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay CP to Qn fmax maximum clock frequency CI input capacitance CPD power dissipation capacitance per flip-flop CL = 15 pF; VCC = 5 V notes 1 and 2 HCT 12 13 ns 61 40 MHz 3.5 3.5 pF 19 19 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz. fo = output frequency in MHz. ∑ (CL × VCC2 × fo) = sum of outputs. CL = output load capacitance in pF. VCC = supply voltage in V. 2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V. ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION 74HC534 SO20 74HC534 DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1 74HCT534 SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74HCT534 DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1 1998 Apr 10 plastic small outline package; 20 leads; body width 7.5 mm VERSION 2 SOT163-1 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state; inverting 74HC/HCT534 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 OE 3-state output enable input (active LOW) 2, 5, 6, 9, 12, 15, 16, 19 Q0 to Q7 3-state outputs 3, 4, 7, 8, 13, 14, 17, 18 D0 to D7 data inputs 10 GND ground (0 V) 11 CP clock input (LOW-to-HIGH, edge-triggered) 20 VCC positive supply voltage fpage fpage 20 VCC OE 1 11 page Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 8 15 Q5 13 534 Q2 6 CP 3 4 7 14 14 D5 D2 7 13 D4 D3 8 Q3 9 12 Q4 11 CP GND 10 1 11 17 18 D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 OE 1 Q7 EN C1 2 2 5 3 6 4 5 9 7 6 8 9 13 12 14 15 17 16 18 19 12 1D 15 16 19 MGM955 MGM956 MGM954 Fig.1 Pin configuration. 1998 Apr 10 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state; inverting 74HC/HCT534 handbook, halfpage 3 D0 Q0 2 4 D1 Q1 5 7 D2 Q2 6 8 D3 Q3 9 13 D4 14 D5 Q5 15 17 D6 Q6 16 18 D7 Q7 19 FF1 to FF8 3-STATE OUTPUTS Q4 12 11 CP 1 OE MGM957 Fig.4 Functional diagram. FUNCTION TABLE INPUTS OUTPUTS OPERATING MODES load and read register load register and disable outputs INTERNAL FLIP-FLOPS OE CP Dn Q0 to Q7 L ↑ l L H L ↑ h H L H ↑ l L Z H ↑ h H Z Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition Z = high impedance OFF-state; ↑ = LOW-to-HIGH clock transition. 1998 Apr 10 4 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state; inverting D0 handbook, full pagewidth D1 D Q D2 D CP FF 1 Q D3 D CP FF 2 Q D4 D CP FF 3 74HC/HCT534 Q D5 D CP FF 4 Q D6 D CP FF 5 Q D7 D CP FF 6 Q D CP FF 7 Q CP FF 8 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MGM958 Fig.5 Logic diagram. 1998 Apr 10 5 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state; inverting 74HC/HCT534 DC CHARACTERISTICS FOR 74HC For the DC characteristics see chapter “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI. AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 min. typ. max. min. tPHL/ tPLH tPZH/ tPZL tPHZ/ tPLZ tTHL/ tTLH tW tsu th fmax 1998 Apr 10 propagation delay nCP to nQn max. −40 to +125 UNIT V WAVEFORMS CC (V) min. max. 41 165 205 250 15 33 41 50 4.5 12 28 35 43 6.0 3-state output enable time OE to Qn 33 150 190 225 12 30 38 45 4.5 10 26 33 38 6.0 3-state output disable time OE to Qn 41 150 190 225 15 30 38 45 4.5 12 26 33 38 6.0 output transition time 14 60 75 90 5 12 15 18 4.5 4 10 13 15 6.0 clock pulse width HIGH or LOW set-up time Dn to CP hold time Dn to CP maximum clock pulse frequency ns ns ns ns 2.0 2.0 2.0 80 19 100 120 16 7 20 24 4.5 14 6 17 20 6.0 60 6 75 90 12 2 15 18 4.5 10 2 13 15 6.0 5 −3 5 5 5 −1 5 5 4.5 5 −1 5 5 6.0 6.0 18 4.8 4.0 30 55 24 20 4.5 35 66 28 24 6.0 6 ns 2.0 ns ns MHz 2.0 2.0 2.0 2.0 Fig.6 Fig.7 Fig.7 Fig.6 Fig.6 Fig.8 Fig.8 Fig.6 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state; inverting 74HC/HCT534 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see chapter “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI. Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT OE 1.25 CP 0.90 Dn 0.35 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 −40 to +85 min. typ. max min. max. −40 to +125 min. UNIT VCC (V) WAVEFORMS max. tPHL/ tPLH propagation delay CP to Qn 16 30 38 45 ns 4.5 Fig.6 tPZH/ tPZL 3-state output enable time OE to Qn 16 30 38 45 ns 4.5 Fig.7 tPHZ/ tPLZ 3-state output disable time OE to Qn 18 30 38 45 ns 4.5 Fig.7 tTHL/ tTLH output transition time 5 12 15 18 ns 4.5 Fig.6 tW clock pulse width HIGH or LOW 23 14 29 35 ns 4.5 Fig.6 tsu set-up time Dn to CP 12 4 15 18 ns 4.5 Fig.8 th hold time Dn to CP 5 −1 5 5 ns 4.5 Fig.8 fmax maximum clock pulse frequency 22 36 18 15 MHz 4.5 Fig.6 1998 Apr 10 7 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state; inverting 74HC/HCT534 AC WAVEFORMS 1/fmax dbook, full pagewidth VM(1) CP INPUT tW tPHL tPLH VM(1) Qn OUTPUT tTLH tTHL MGM959 (1) HC: VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency. tr andbook, full pagewidth tf 90% VM(1) OE INPUT 10% tPLZ Qn OUTPUT LOW-to-OFF OFF-to-LOW tPZL VM(1) 10% tPHZ tPZH 90% Qn OUTPUT HIGH-to-OFF OFF-to-HIGH VM(1) outputs enabled outputs disabled outputs enabled MGM961 (1) HC: VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the 3-state enable and disable times. 1998 Apr 10 8 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state; inverting 74HC/HCT534 handbook, full pagewidth CP INPUT VM(1) tsu tsu th Dn INPUT th VM(1) VM(1) Qn OUTPUT MGM960 The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC: VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the data set-up and hold times for Dn input. 1998 Apr 10 9 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state; inverting 74HC/HCT534 PACKAGE OUTLINES DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 ME seating plane D A2 A A1 L c e Z b1 w M (e 1) b MH 11 20 pin 1 index E 1 10 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 inches 0.17 0.020 0.13 0.068 0.051 0.021 0.015 0.014 0.009 1.060 1.045 D e e1 L ME MH w Z (1) max. 6.40 6.22 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.0 0.25 0.24 0.10 0.30 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.078 (1) E (1) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT146-1 1998 Apr 10 REFERENCES IEC JEDEC EIAJ SC603 10 EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-05-24 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state; inverting 74HC/HCT534 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013AC 1998 Apr 10 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-24 97-05-22 11 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state; inverting Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. WAVE SOLDERING This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (order code 9398 652 90011). Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. DIP • The longitudinal axis of the package footprint must be parallel to the solder flow. SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. • The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1998 Apr 10 74HC/HCT534 12 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state; inverting 74HC/HCT534 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Apr 10 13