INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT109 Dual JK flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of December 1990 File under Integrated Circuits, IC06 1997 Nov 25 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74HC/HCT109 (SD) and reset (RD) inputs; also complementary Q and Q outputs. FEATURES • J, K inputs for easy D-type flip-flop The set and reset are asynchronous active LOW inputs and operate independently of the clock input. • Toggle flip-flop or “do nothing” mode • Output capability: standard The J and K inputs control the state changes of the flip-flops as described in the mode select function table. • ICC category: flip-flops The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The JK design allows operation as a D-type flip-flop by tying the J and K inputs together. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP) inputs, set QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH HCT propagation delay nCP to nQ, nQ nSD to nQ, nQ nRD to nQ, nQ CL = 15 pF; VCC = 5 V 15 17 ns 12 14 ns 12 15 ns fmax maximum clock frequency 75 61 MHz CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per flip-flop 20 22 pF notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V. ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. 1997 Nov 25 2 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74HC/HCT109 PIN DESCRIPTION PIN NO. SYMBOL 1, 15 1RD, 2RD asynchronous reset-direct input (active LOW) 2, 14, 3, 13 1J, 2J, 1K, 2K synchronous inputs; flip-flops 1 and 2 4, 12 1CP, 2CP clock input (LOW-to-HIGH, edge-triggered) 5, 11 1SD, 2SD asynchronous set-direct input (active LOW) 6, 10 1Q, 2Q true flip-flop outputs 7, 9 1Q, 2Q complement flip-flop outputs 8 GND ground (0 V) 16 VCC positive supply voltage Fig.1 Pin configuration. 1997 Nov 25 NAME AND FUNCTION Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74HC/HCT109 FUNCTION TABLE OPERATING MODE INPUTS OUTPUTS SD RD CP J K Q Q asynchronous set L H X X X H L asynchronous reset H L X X X L H undetermined L L X X X H H toggle H H ↑ h l q q load “0” (reset) H H ↑ l l L H load “1” (set) H H ↑ h h H L hold “no change” H H ↑ l h q q Notes Fig.4 Functional diagram. 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition X = don’t care ↑ = LOW-to-HIGH CP transition handbook, full pagewidth Q C C C C K Q J C C C C S R C CP MBK217 C Fig.5 Logic diagram (one flip-flop). PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. 1997 Nov 25 4 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74HC/HCT109 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: flip-flops AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) SYMBOL 74HC PARAMETER +25 min. min. 75 15 13 95 19 16 110 22 19 80 16 14 80 set or reset pulse 16 width HIGH or LOW 14 70 removal time 14 nSD, nRD to nCP 12 70 set-up time 14 nJ, nK to nCP 12 5 hold time 5 nJ, nK to nCP 5 6.0 30 35 22 68 81 propagation delay nSD to nQ tPHL propagation delay nRD to nQ tPLH propagation delay nRD to nQ tTHL/ tTLH output transition time tW clock pulse width HIGH or LOW maximum clock pulse frequency 1997 Nov 25 UNIT ns ns ns ns ns ns 100 20 17 100 20 17 90 18 15 90 18 15 5 5 5 120 24 20 120 24 20 105 21 18 105 21 18 5 5 5 ns 5.0 24 28 4.0 20 24 MHz 5 VCC WAVEFORMS (V) max. 19 7 6 19 7 6 14 5 4 19 7 6 17 6 5 0 0 0 tPHL fmax max. 265 53 45 180 36 31 235 47 40 280 56 48 255 51 43 propagation delay nSD to nQ th min. 220 44 37 150 30 26 195 39 33 230 46 39 215 43 37 tPLH tsu max. −40 to +125 175 35 30 120 24 20 155 31 26 185 37 31 170 34 29 propagation delay nCP to nQ, nQ trem typ. −40 to +85 50 18 14 30 11 9 41 15 12 41 15 12 39 14 11 tPHL/ tPLH tW TEST CONDITIONS ns ns ns ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 Fig.7 Fig.7 Fig.7 Fig.7 Fig.6 Fig.6 Fig.7 Fig.7 Fig.6 Fig.6 Fig.6 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74HC/HCT109 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: flip-flops AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) SYMBOL 74HCT PARAMETER +25 min. tPHL/ tPLH tPLH tPHL tPHL tPLH tTHL/ tTLH tW tW trem tsu th fmax propagation delay nCP to nQ, nQ propagation delay nSD to nQ propagation delay nSD to nQ propagation delay nRD to nQ propagation delay nRD to nQ output transition time clock pulse width 18 HIGH or LOW set or reset pulse width 16 HIGH or LOW removal time 16 nSD, nRD to nCP set-up time nJ, nK to nCP hold time nJ, nK to nCP maximum clock pulse frequency 1997 Nov 25 TEST CONDITIONS typ. −40 to +85 max. min. max. −40 to +125 min. UNIT VCC WAVEFORMS (V) max. 20 35 44 53 ns 4.5 Fig.6 13 26 33 39 ns 4.5 Fig.7 19 35 44 53 ns 4.5 Fig.7 19 35 44 53 ns 4.5 Fig.7 16 32 40 48 ns 4.5 Fig.7 7 15 19 22 ns 4.5 Fig.6 9 23 27 ns 4.5 Fig.6 8 20 24 ns 4.5 Fig.7 8 20 24 ns 4.5 Fig.7 18 8 23 27 ns 4.5 Fig.6 3 −3 3 3 ns 4.5 Fig.6 27 55 22 18 MHz 4.5 Fig.6 6 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74HC/HCT109 AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance. Fig.6 Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nJ, nK to nCP set-up, the nCP to nJ, nK hold times, the output transition times and the maximum clock pulse frequency. handbook, full pagewidth VM(1) nCP INPUT trem nSD INPUT VM(1) tW trem tW VM(1) nRD INPUT tPLH nQ OUTPUT tPHL VM(1) tPLH tPHL nQ OUTPUT VM(1) MBK216 (1) HC: VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths and the nRD, nSD to nCP removal time. 1997 Nov 25 7 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74HC/HCT109 Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. WAVE SOLDERING Wave soldering can be used for all SO packages. Wave soldering is not recommended for SSOP and TSSOP packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). If wave soldering is used - and cannot be avoided for SSOP and TSSOP packages - the following conditions must be observed: DIP • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. • The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions: The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. • Only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). REPAIRING SOLDERED JOINTS During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. • Do not consider wave soldering TSSOP packages with 48 leads or more, that is TSSOP48 (SOT362-1) and TSSOP56 (SOT364-1). Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. SO, SSOP and TSSOP A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REFLOW SOLDERING Reflow soldering techniques are suitable for all SO, SSOP and TSSOP packages. REPAIRING SOLDERED JOINTS Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. 1997 Nov 25 8 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74HC/HCT109 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1997 Nov 25 9