AT93C56B and AT93C66B 3-wire Serial EEPROM 2K (256 x 8 or 128 x 16) and 4K (512 x 8 or 256 x 16) DATASHEET Features Low-voltage operation VCC = 1.7V to 5.5V User-selectable internal organization 2K: 256 x 8 or 128 x 16 4K: 512 x 8 or 256 x 16 3-wire serial interface Sequential Read operation 2MHz clock rate (5V) Self-timed write cycle (5ms max) High reliability Endurance: 1,000,000 write cycles Data retention: 100 years 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-pad XDFN, and 8-ball VFBGA packages Description The Atmel® AT93C56B/66B provides 2,048/4,096 bits of Serial Electrically Erasable Programmable Read-Only Memory (EEPROM) organized as 128/256 words of 16 bits each (when the ORG pin is connected to VCC) and 256/512 words of 8 bits each (when the ORG pin is tied to ground). The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. The AT93C56B/66B is available in space-saving 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-pad XDFN, and 8-ball VFBGA packages. The AT93C56B/66B is enabled through the Chip Select pin (CS) and accessed via a 3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a Read instruction at DI, the address is decoded, and the data is clocked out serially on the DO pin. The write cycle is completely self-timed, and no separate erase cycle is required before Write. The write cycle is only enabled when the part is in the Erase/Write Enable state. When CS is brought high following the initiation of a write cycle, the DO pin outputs the Ready/Busy status of the part. The AT93C56B/66B operates from 1.7V to 5.5V. Atmel-8735B-SEEPROM-AT93C56B-66B-Datasheet_042013 1. Pin Configurations and Pinouts Table 1-1. Pin Configurations 8-lead SOIC 8-lead TSSOP Pin Name Function CS Chip Select CS 1 8 VCC SK Serial Data Clock SK 2 7 NC 6 Serial Data Input DI 3 DI ORG DO 4 5 GND DO Serial Data Output GND Ground VCC Power Supply ORG Internal Organization NC No Connect 1 2 3 4 8 7 6 5 VCC NC ORG GND Top View Top View 8-ball VFBGA 8-pad UDFN/XDFN VCC 8 1 CS NC 7 2 SK ORG 6 3 DI GND 5 4 DO GND Bottom View Note: 2. CS SK DI DO VCC 8 1 CS NC 7 2 SK ORG 6 3 DI 5 4 DO Bottom View Drawings are not to scale. Absolute Maximum Ratings* Operating Temperature 55C to +125C Storage Temperature 65C to +150C Voltage on any pin with respect to ground1.0V to +7.0V Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V DC Output Current. . . . . . . . . . . . . . . . . . . . . . . 5.0mA *Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Atmel AT93C56B/66B [Datasheet] Atmel-8735B-SEEPROM-AT93C56B-66B-Datasheet_042013 2 3. Block Diagram VCC GND Memory Array ORG 256/512 x 8 or 128/256 x 16 Address Decoder Data Register Output Buffer DI CS SK Note: Mode Decode Logic Clock Generator DO When the ORG pin is connected to VCC, the x 16 organization is selected. When it is connected to ground, the x 8 organization is selected. If the ORG pin is left unconnected, and the application does not load the input beyond the capability of the internal 1M pull-up resistor, then the x 16 organization is selected. Atmel AT93C56B/66B [DATASHEET] Atmel-8735B-SEEPROM-AT93C56B-66B-Datasheet_042013 3 4. Memory Organization 4.1 Pin Capacitance(1) Applicable over recommended operating range from TA = 25C, f = 1.0MHz, VCC = 5.0V (unless otherwise noted). Symbol Test Conditions COUT CIN Note: 4.2 1. Max Units Conditions Output Capacitance (DO) 5 pF VOUT = 0V Input Capacitance (CS, SK, DI) 5 pF VIN = 0V This parameter is characterized, and is not 100% tested. DC Characteristics Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = 1.7V to 5.5V (unless otherwise noted). Symbol Parameter VCC1 Supply Voltage VCC2 Test Condition Min Typ Max Unit 1.7 5.5 V Supply Voltage 2.5 5.5 V VCC3 Supply Voltage 4.5 5.5 V ICC Supply Current VCC = 5.0V ISB1 Standby Current ISB2 Read at 1.0MHz 0.5 2.0 mA Write at 1.0MHz 0.5 2.0 mA VCC = 1.7V CS = 0V 0.4 1.0 μA Standby Current VCC = 2.5V CS = 0V 6.0 10.0 μA ISB3 Standby Current VCC = 5.0V CS = 0V 10.0 15.0 μA IIL Input Leakage VIN = 0V to VCC 0.1 3.0 μA IOL Output Leakage VIN = 0V to VCC 0.1 3.0 μA VIL1(1) Input Low Voltage 2.5V VCC 5.5V 0.6 0.8 V VIH1(1) Input High Voltage 2.5V VCC 5.5V 2.0 VCC + 1 V VIL2(1) Input Low Voltage 1.7V VCC 2.5V 0.6 VCC x 0.3 V VIH2(1) Input High Voltage 1.7V VCC 2.5V VCC x 0.7 VCC + 1 V VOL1 Output Low Voltage 2.5V VCC 5.5V IOL = 2.1mA 0.4 V VOH1 Output High Voltage 2.5V VCC 5.5V IOH = 0.4mA VOL2 Output Low Voltage 1.7V VCC 2.5V IOL = 0.15mA VOH2 Output High Voltage 1.7V VCC 2.5V IOH = 100μA Note: 1. 2.4 V 0.2 VCC 0.2 V V VIL min and VIH max are reference only, and are not tested. Atmel AT93C56B/66B [Datasheet] Atmel-8735B-SEEPROM-AT93C56B-66B-Datasheet_042013 4 4.3 AC Characteristics Applicable over recommended operating range from TAI = 40°C to + 85°C, VCC = as specified, CL = 1 TTL gate and 100pF (unless otherwise noted). Symbol Parameter fSK SK Clock Frequency Test Condition Min Max Units 4.5V VCC 5.5V 0 2 MHz 2.5V VCC 5.5V 0 1 MHz 1.7V VCC 5.5V 0 250 kHz 2.5V VCC 5.5V 250 ns 1.7V VCC 5.5V 1000 ns 2.5V VCC 5.5V 250 ns 1.7V VCC 5.5V 1000 ns 2.5V VCC 5.5V 250 ns 1.7V VCC 5.5V 1000 ns 2.5V VCC 5.5V 50 ns 1.7V VCC 5.5V 200 ns 2.5V VCC 5.5V 100 ns 1.7V VCC 5.5V 400 ns 0 ns 2.5V VCC 5.5V 100 ns 1.7V VCC 5.5V 400 ns tSKH SK High Time tSKL SK Low Time tCS Minimum CS Low Time tCSS CS Setup Time Relative to SK tDIS DI Setup Time Relative to SK tCSH CS Hold Time Relative to SK tDIH DI Hold Time Relative to SK tPD1 Output Delay to 1 AC Test tPD0 Output Delay to 0 AC Test tSV CS to Status Valid AC Test tDF CS to DO in High-impedance tWP Write Cycle Time Endurance(1) 5.0V, 25°C Note: 1. 2.5V VCC 5.5V 250 ns 1.7V VCC 5.5V 1000 ns 2.5V VCC 5.5V 250 ns 1.7V VCC 5.5V 1000 ns 2.5V VCC 5.5V 250 ns 1.7V VCC 5.5V 1000 ns AC Test 2.5V VCC 5.5V 150 ns CS = VIL 1.7V VCC 5.5V 400 ns 1.7V VCC 5.5V 5 ms 1,000,000 Write Cycles This parameter is characterized, and is not 100% tested. Atmel AT93C56B/66B [DATASHEET] Atmel-8735B-SEEPROM-AT93C56B-66B-Datasheet_042013 5 4.4 AT93C56B/66B Instruction Set Address SB Opcode x 8(1) x 16(1) READ 1 10 A8 – A0 A7 – A0 EWEN 1 00 ERASE 1 11 A8 – A0 A7 – A0 WRITE 1 01 A8 – A0 A7 – A0 ERAL 1 00 10XXXXXXX 10XXXXXX WRAL 1 00 01XXXXXXX 01XXXXXX EWDS 1 00 00XXXXXXX 00XXXXXX Instruction Note: 1. Data x8 x 16 Comments Reads data stored in memory at specified address. Write Enable must precede all programming modes. 11XXXXXXX 11XXXXXX Erases memory location AN – A0. D7 – D 0 D15 – D0 Writes memory location AN – A0. Erases all memory locations. Valid only at VCC3 (Section 4.2, “DC Characteristics” on page 4). D7 – D 0 D15 – D0 Writes all memory locations. Valid only at VCC3 (Section 4.2) and Disable Register cleared. Disables all programming instructions. The Xs in the address field represent don’t care values, and must be clocked. Atmel AT93C56B/66B [Datasheet] Atmel-8735B-SEEPROM-AT93C56B-66B-Datasheet_042013 6 5. Functional Description The AT93C56B/66B is accessed via a simple and versatile 3-wire serial communication interface. Device operation is controlled by seven instructions issued by the Host processor. A valid instruction starts with a rising edge of CS and consists of a Start bit (Logic 1), followed by the appropriate opcode, and the desired memory address location. Read: The Read instruction contains the address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory location is available at the Serial Output pin, DO. Output data changes are synchronized with the rising edges of the Serial Clock pin, SK. It should be noted that a dummy bit (Logic 0) precedes the 8-bit or 16-bit data output string. The AT93C56B/66B supports sequential Read operations. The device will automatically increment the internal address pointer and clock out the next memory location as long as Chip Select (CS) is held high. In this case, the dummy bit (Logic 0) will not be clocked out between memory locations, thus allowing for a continuous stream of data to be read. Erase/Write Enable (EWEN): To ensure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Note: Once in the EWEN state, programming remains enabled until an EWDS instruction is executed, or VCC power is removed from the part. Erase: The Erase instruction programs all bits in the specified memory location to the Logic 1 state. The self-timed erase cycle starts once the Erase instruction and address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of tCS. A Logic 1 at the DO pin indicates that the selected memory location has been erased, and the part is ready for another instruction. Write: The Write instruction contains the 8-bits or 16-bits of data to be written into the specified memory location. The self-timed programming cycle, tWP, starts after the last bit of data is received at Serial Data Input pin DI. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of tCS. A Logic 0 at DO indicates that programming is still in progress. A Logic 1 indicates that the memory location at the specified address has been written with the data pattern contained in the instruction, and the part is ready for further instructions. A Ready/Busy status cannot be obtained if CS is brought high after the end of the self-timed programming cycle, tWP. Erase All (ERAL): The Erase All (ERAL) instruction programs every bit in the Memory Array to the Logic 1 state and is primarily used for testing purposes. The DO pin outputs the ready/busy status of the part if CS is brought high after being kept low for a minimum of tCS. The ERAL instruction is valid only at VCC3 (Section 4.2, “DC Characteristics” on page 4). Write All (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of tCS. The WRAL instruction is valid only at VCC3 (Section 4.2). Erase/Write Disable (EWDS): To protect against accidental data disturbance, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the Read instruction is independent of both the EWEN and EWDS instructions and can be executed at any time. Atmel AT93C56B/66B [DATASHEET] Atmel-8735B-SEEPROM-AT93C56B-66B-Datasheet_042013 7 6. Timing Diagrams Figure 6-1. Synchronous Data Timing CS SK VIH VIL tSKL tCSH VIH VIL tDIS DI tSKH tCSS tDIH VIH VIL tPD0 DO (Read) tPD1 VOH VOL tDF tSV DO (Program) VOH Status Valid VOL Table 6-1. tDF Organization Key for Timing Diagrams AT93C56B (2K) AT93C66B (4K) I/O x8 x 16 x8 x 16 AN A8(1) A7(2) A8 A7 DN D7 D15 D7 D15 Notes: 1. A8 is a don’t-care value, but the extra clock is required. 2. A7 is a don’t-care value, but the extra clock is required. Atmel AT93C56B/66B [Datasheet] Atmel-8735B-SEEPROM-AT93C56B-66B-Datasheet_042013 8 Figure 6-2. Read Timing tCS CS SK DI DO 1 1 0 AN A0 High-impedance 0 DN D0 Figure 6-3. EWEN Timing tCS CS SK DI 1 0 0 1 1 ... Figure 6-4. EWDS Timing tCS CS SK DI 1 0 0 0 0 ... Atmel AT93C56B/66B [DATASHEET] Atmel-8735B-SEEPROM-AT93C56B-66B-Datasheet_042013 9 Figure 6-5. Write Timing tCS CS SK 1 DI 0 1 AN ... A0 DN ... D0 High-impedance DO Busy Ready tWP Figure 6-6. WRAL Timing(1) tCS CS SK 1 DI 0 0 0 1 ... DN ... D0 High-impedance DO Busy Ready tWP Note: 1. Valid only at VCC3 (Section 4.2, “DC Characteristics” on page 4). Atmel AT93C56B/66B [Datasheet] Atmel-8735B-SEEPROM-AT93C56B-66B-Datasheet_042013 10 Figure 6-7. Erase Timing tCS Standby Check Status CS SK 1 DI 1 1 AN AN-1 AN-2 ... A0 tDF tSV High-impedance DO High-impedance Busy Ready tWP Figure 6-8. ERAL Timing(1) tCS Standby Check Status CS SK 1 DI 0 0 1 0 tDF tSV High-impedance DO High-impedance Busy Ready tWP Note: 1. Valid only at VCC3 (Section 4.2, “DC Characteristics” on page 4). Atmel AT93C56B/66B [DATASHEET] Atmel-8735B-SEEPROM-AT93C56B-66B-Datasheet_042013 11 7. Ordering Code Detail AT 9 3 C 5 6 B - S S H M - B Atmel Designator Shipping Carrier Option B or blank = Bulk (Tubes) T = Tape and Reel Product Family Operating Voltage M = 1.7V to 5.5V Device Density 56 = 2k 66 = 4k Device Revision Package Device Grade or Wafer/Die Thickness H = Green, NiPdAu Lead Finish Industrial Temperature Range (-40°C to +85°C) U = Green, Matte Sn Lead Finish Industrial Temperature Range (-40°C to +85°C) 11 = 11mil Wafer Thickness Package Option SS = JEDEC SOIC X = TSSOP MA = UDFN ME = XDFN C = VFBGA WWU = Wafer Unsawn Atmel AT93C56B/66B [Datasheet] Atmel-8735B-SEEPROM-AT93C56B-66B-Datasheet_042013 12 8. Part Markings AT93C56B and AT93C66B: Package Marking Information 8-lead TSSOP 8-lead SOIC 8-pad UDFN 2.0 x 3.0 mm Body ### H%@ YXX ATHYWW ###% @ AAAAAAA ATMLHYWW ###% @ AAAAAAAA 8-pad XDFN 8-ball VFBGA 1.8 x 2.2 mm Body 1.5 x 2.0 mm Body ### YXX ###U YMXX PIN 1 Note 1: designates pin 1 Note 2: Package drawings are not to scale Catalog Number Truncation AT93C56B Truncation Code ###: 56B AT93C66B Truncation Code ###: 66B Date Codes Y = Year 3: 2013 4: 2014 5: 2015 6: 2016 Voltages 7: 2017 8: 2018 9: 2019 0: 2020 M = Month A: January B: February ... L: December WW = Work Week of Assembly 02: Week 2 04: Week 4 ... 52: Week 52 Country of Assembly Lot Number @ = Country of Assembly AAA...A = Atmel Wafer Lot Number Trace Code % = Minimum Voltage M: 1.7V min Grade/Lead Finish Material U: Industrial/Matte Tin/SnAgCu H: Industrial/NiPdAu Atmel Truncation XX = Trace Code (Atmel Lot Numbers Correspond to Code) Example: AA, AB.... YZ, ZZ AT: Atmel ATM: Atmel ATML: Atmel 3/22/13 TITLE Package Mark Contact: [email protected] 93C56-66BSM, AT93C56B and AT93C66B Package Marking Information DRAWING NO. REV. 93C56-66BSM B Atmel AT93C56B/66B [DATASHEET] Atmel-8735B-SEEPROM-AT93C56B-66B-Datasheet_042013 13 9. Ordering Information Atmel Ordering Code Lead Finish Package Voltage Operation Range 1.7V to 5.5V Industrial Temperature (40C to 85C) 1.7V to 5.5V Industrial Temperature (40C to 85C) AT93C56B-SSHM-B(1) 8S1 AT93C56B-SSHM-T(2) AT93C56B-XHM-B(1) AT93C56B-XHM-T (2) NiPdAu (Lead-free/Halogen-free) 8X (2) AT93C56B-MAHM-T 8MA2 AT93C56B-MEHM-T(2) 8ME1 AT93C56B-CUM-T(2) SnAgCu (Lead-free/Halogen-free) 8U3-1 — Wafer Sale AT93C56B-WWU11M(3) AT93C66B-SSHM-B(1) 8S1 AT93C66B-SSHM-T(2) AT93C66B-XHM-B(1) AT93C66B-XHM-T (2) NiPdAu (Lead-free/Halogen-free) 8X (2) AT93C66B-MAHM-T 8MA2 AT93C66B-MEHM-T(2) 8ME1 AT93C66B-CUM-T(2) SnAgCu (Lead-free/Halogen-free) 8U3-1 — Wafer Sale AT93C66B-WWU11M(3) Notes: 1. 2. 3. B = Bulk T = Tape and Reel SOIC = 4k per reel TSSOP, UDFN, XDFN, and VFBGA = 5k per reel For wafer sales, please contact Atmel sales. Package Type 8S1 8-lead, 0.150” wide, Plastic Gull Wing, Small Outline (JEDEC SOIC) 8X 8-lead, 0.170” wide, Thin Shrink Small Outline (TSSOP) 8MA2 8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Ultra Thin Dual No Lead (UDFN) 8ME1 8-pad, 1.80mm x 2.20mm body, Extra Thin Dual No Lead (XDFN) 8U3-1 8-ball, 1.50mm x 2.00mm body, 0.50mm pitch, Small Die Ball Grid Array (VFBGA) Atmel AT93C56B/66B [Datasheet] Atmel-8735B-SEEPROM-AT93C56B-66B-Datasheet_042013 14 10. Packaging Information 10.1 8S1 — 8-lead JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 D SIDE VIEW Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. SYMBOL MIN A 1.35 NOM MAX – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e NOTE 1.27 BSC L 0.40 – 1.27 Ø 0° – 8° 6/22/11 Package Drawing Contact: [email protected] TITLE 8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) GPC SWB DRAWING NO. REV. 8S1 G Atmel AT93C56B/66B [DATASHEET] Atmel-8735B-SEEPROM-AT93C56B-66B-Datasheet_042013 15 10.2 8X — 8-lead TSSOP C 1 Pin 1 indicator this corner E1 E L1 H N L Top View End View A b A1 e A2 MIN NOM MAX A - - 1.20 A1 0.05 - 0.15 A2 0.80 1.00 1.05 D 2.90 3.00 3.10 2, 5 SYMBOL D Side View Notes: COMMON DIMENSIONS (Unit of Measure = mm) 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25mm (0.010in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07mm. 5. Dimension D and E1 to be determined at Datum Plane H. E NOTE 6.40 BSC E1 4.30 4.40 4.50 3, 5 b 0.19 – 0.30 4 e 0.65 BSC L 0.45 L1 C 0.60 0.75 1.00 REF 0.09 - 0.20 12/8/11 TITLE Package Drawing Contact: [email protected] 8X, 8-lead 4.4mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) GPC TNR DRAWING NO. 8X Atmel AT93C56B/66B [Datasheet] Atmel-8735B-SEEPROM-AT93C56B-66B-Datasheet_042013 REV. E 16 10.3 8MA2 — 8-pad UDFN E 1 8 Pin 1 ID 2 7 3 6 4 5 D C A2 A A1 E2 COMMON DIMENSIONS (Unit of Measure = mm) b (8x) 8 1 7 2 Pin#1 ID 6 D2 3 5 4 e (6x) L (8x) SYMBOL MIN NOM MAX D 1.90 2.00 2.10 E 2.90 3.00 3.10 D2 1.40 1.50 1.60 E2 1.20 1.30 1.40 A 0.50 0.55 0.60 A1 0.0 0.02 0.05 A2 – – 0.55 C K L NOTE 0.152 REF 0.30 e 0.35 0.40 0.50 BSC b 0.18 0.25 0.30 K 0.20 – – 3 9/6/12 Package Drawing Contact: [email protected] TITLE 8MA2, 8-pad, 2 x 3 x 0.6 mm Body, Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN) GPC YNZ DRAWING NO. 8MA2 Atmel AT93C56B/66B [DATASHEET] Atmel-8735B-SEEPROM-AT93C56B-66B-Datasheet_042013 REV. C 17 10.4 8ME1 — 8-pad XDFN D 7 8 6 5 E PIN #1 ID 2 1 3 4 A1 Top View A Side View e1 b L COMMON DIMENSIONS (Unit of Measure = mm) 0.10 PIN #1 ID 0.15 b e End View SYMBOL MIN NOM MAX A – – 0.40 A1 0.00 – 0.05 D 1.70 1.80 1.90 E 2.10 2.20 2.30 b 0.15 0.20 0.25 e 0.40 TYP e1 1.20 REF L 0.26 0.30 NOTE 0.35 9/10/2012 Package Drawing Contact: [email protected] TITLE GPC DRAWING NO. REV. 8ME1, 8-pad (1.80mm x 2.20mm body) Extra Thin DFN (XDFN) DTP 8ME1 B Atmel AT93C56B/66B [Datasheet] Atmel-8735B-SEEPROM-AT93C56B-66B-Datasheet_042013 18 10.5 8U3-1 — 8-ball VFBGA E D 2. b PIN 1 BALL PAD CORNER A1 A2 TOP VIEW A SIDE VIEW PIN 1 BALL PAD CORNER 3 2 1 4 d (d1) 8 7 6 5 COMMON DIMENSIONS (Unit of Measure - mm) e (e1) SYMBOL MIN NOM MAX BOTTOM VIEW A 0.73 0.79 0.85 8 SOLDER BALLS A1 0.09 0.14 0.19 A2 0.40 0.45 0.50 Notes: b 0.20 0.25 0.30 1. This drawing is for general information only. D 2. Dimension ‘b’ is measured at maximum solder ball diameter. 3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu. NOTE 2 1.50 BSC E 2.0 BSC e 0.50 BSC e1 0.25 REF d 1.00 BSC d1 0.25 REF 3/27/12 Package Drawing Contact: [email protected] TITLE GPC DRAWING NO. 8U3-1, 8-ball, 1.50mm x 2.00mm body, 0.50mm pitch, VFBGA Package GXU 8U3-1 Atmel AT93C56B/66B [DATASHEET] Atmel-8735B-SEEPROM-AT93C56B-66B-Datasheet_042013 REV. E 19 11. Revision History Revision No. Date Comments Correct Synchronous Data Timing figure and remove note. 8735B 04/2013 Update TSSOP package option from 8A2 to 8X. Update UDFN package option from 8Y6 to 8MA2. Update template and Atmel logos. 8735A 01/2011 Initial document release. Atmel AT93C56B/66B [Datasheet] Atmel-8735B-SEEPROM-AT93C56B-66B-Datasheet_042013 20 X X X X Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2013 Atmel Corporation. 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