ATMEL AT93C46DN-SH-T

Features
• Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8V to 5.5V)
• User-selectable Internal Organization
– 1K: 128 x 8 or 64 x 16
Three-wire Serial Interface
2 MHz Clock Rate (5V)
Self-timed Write Cycle (5 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3), 8-lead
TSSOP and 8-ball dBGA2 Packages
• Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers
•
•
•
•
Three-wire
Serial
EEPROM
1K (128 x 8 or 64 x 16)
Description
The AT93C46D provides 1024 bits of serial electrically erasable programmable readonly memory (EEPROM), organized as 64 words of 16 bits each (when the ORG pin is
connected to VCC), and 128 words of 8 bits each (when the ORG pin is tied to
ground). The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. The AT93C46D is
available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin miniMAP (MLP 2x3), 8-lead TSSOP, and 8-lead dBGA2 packages.
AT93C46D
The AT93C46D is enabled through the Chip Select pin (CS) and accessed via a
three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the
data is clocked out serially on the DO pin. The Write cycle is completely self-timed,
and no separate Erase cycle is required before Write. The Write cycle is only enabled
when the part is in the Erase/Write Enable state. When CS is brought high following
the initiation of a Write cycle, the DO pin outputs the Ready/Busy status of the part.
The AT93C46D is available in 1.8 (1.8V to 5.5V) version.
Table 0-1.
Pin Configurations
Pin Name
Function
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
Ground
VCC
Power Supply
ORG
Internal Organization
NC
No Connect
8-lead SOIC
CS
SK
DI
DO
1
2
3
4
8
7
6
5
8-lead dBGA2
VCC
NC
ORG
GND
VCC
NC
ORG
GND
8
1
7
2
6
3
5
4
CS
SK
D1
D0
Bottom View
8-lead PDIP
CS
SK
DI
DO
1
2
3
4
8
7
6
5
8-lead Ultra Thin mini-MAP (MLP 2x3)
VCC
NC
ORG
GND
VCC
NC
ORG
GND
CS
SK
3 DI
4 DO
8
1
7
2
6
5
Bottom View
8-lead TSSOP
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
5193F–SEEPR–1/08
1. Absolute Maximum Ratings*
Operating Temperature......................................−55°C to +125°C
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground ........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
DC Output Current........................................................ 5.0 mA
Figure 1-1.
Notes:
Block Diagram
1. When the ORG pin is connected to VCC, the “x 16” organization is selected. When it is connected to ground, the “x 8” organization is selected. If the ORG pin is left unconnected and the
application does not load the input beyond the capability of the internal 1 Meg ohm pullup, then
the “x 16” organization is selected.
2. For the AT93C46D, if the “x 16” organization is the mode of choice and pin 6 (ORG) is left
unconnected, Atmel® recommends using AT93C46E device. For more details, see the
AT93C46E datasheet.
2
AT93C46D
5193F–SEEPR–1/08
AT93C46D
Table 1-1.
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V (unless otherwise noted)
Symbol
Test Conditions
COUT
CIN
Note:
Max
Units
Conditions
Output Capacitance (DO)
5
pF
VOUT = 0V
Input Capacitance (CS, SK, DI)
5
pF
VIN = 0V
1. This parameter is characterized and is not 100% tested.
Table 1-2.
DC Characteristics
Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted)
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Test Condition
Min
Typ
Max
Unit
1.8
5.5
V
Supply Voltage
2.7
5.5
V
VCC3
Supply Voltage
4.5
5.5
V
ICC
Supply Current
ISB1
Standby Current
ISB2
READ at 1.0 MHz
0.5
2.0
mA
WRITE at 1.0 MHz
0.5
2.0
mA
VCC = 1.8V
CS = 0V
0.4
1.0
µA
Standby Current
VCC = 2.7V
CS = 0V
6.0
10.0
µA
ISB3
Standby Current
VCC = 5.0V
CS = 0V
10.0
15.0
µA
IIL
Input Leakage
VIN = 0V to VCC
0.1
1.0
µA
Output Leakage
VIN = 0V to VCC
0.1
1.0
µA
IOL
VIL1
(1)
Input Low Voltage
VIH1(1)
Input High Voltage
VIL2(1)
Input Low Voltage
(1)
VIH2
Input High Voltage
VOL1
Output Low Voltage
VOH1
Output High Voltage
VOL2
Output Low Voltage
VOH2
Output High Voltage
Note:
VCC = 5.0V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 2.7V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 2.7V
−0.6
0.8
2.0
VCC + 1
−0.6
VCC x 0.3
VCC x 0.7
VCC + 1
IOL = 2.1 mA
IOH = −0.4 mA
0.4
2.4
IOL = 0.15 mA
IOH = −100 µA
V
V
V
0.2
VCC – 0.2
V
V
V
1. VIL min and VIH max are reference only and are not tested.
3
5193F–SEEPR–1/08
Table 1-3.
AC Characteristics
Applicable over recommended operating range from TAI = −40°C to + 85°C, VCC = +2.7V to +5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol
Parameter
Test Condition
fSK
SK Clock
Frequency
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
0
0
0
tSKH
SK High Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tSKL
SK Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tCS
Minimum CS
Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tCSS
CS Setup Time
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
50
50
200
ns
tDIS
DI Setup Time
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
100
400
ns
tCSH
CS Hold Time
Relative to SK
0
ns
tDIH
DI Hold Time
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
100
400
ns
tPD1
Output Delay to “1”
AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tPD0
Output Delay to “0”
AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tSV
CS to Status Valid
AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
250
1000
ns
tDF
CS to DO in High
Impedance
AC Test
CS = VIL
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
150
400
ns
5
ms
tWP
Write Cycle Time
Endurance
Note:
4
(1)
5.0V, 25°C
Min
1.8V ≤ VCC ≤ 5.5V
0.1
1M
Typ
3
Max
Units
2
1
0.25
MHz
Write Cycles
1. This parameter is ensured by characterization.
AT93C46D
5193F–SEEPR–1/08
AT93C46D
Table 1-4.
Instruction Set for the AT93C46D
Address
Data
SB
Op
Code
x8
x 16
READ
1
10
A6 – A0
A5 – A0
EWEN
1
00
11XXXXX
11XXXX
ERASE
1
11
A6 – A0
A5 – A0
WRITE
1
01
A6 – A0
A5 – A0
ERAL
1
00
10XXXXX
10XXXX
WRAL
1
00
01XXXXX
01XXXX
EWDS
1
00
00XXXXX
00XXXX
Instruction
Note:
x8
x 16
Comments
Reads data stored in memory, at
specified address
Write enable must precede all
programming modes
Erases memory location An – A0
D7 – D0
D15 – D0
Writes memory location An – A0
Erases all memory locations. Valid
only at VCC = 4.5V to 5.5V
D7 – D0
D15 – D0
Writes all memory locations. Valid
only at VCC = 4.5V to 5.5V
Disables all programming instructions
The Xs in the address field represent DON’T CARE values and must be clocked.
2. Functional Description
The AT93C46D is accessed via a simple and versatile three-wire serial communication interface. Device operation is controlled by seven instructions issued by the host processor. A valid
instruction starts with a rising edge of CS and consists of a start bit (logic “1”) followed by the
appropriate op code and the desired memory address location.
READ (READ): The Read (READ) instruction contains the address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory
location is available at the serial output pin DO. Output data changes are synchronized with the
rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 8- or
16-bit data output string.
ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN)
instruction must be executed first before any programming instructions can be carried out.
Please note that once in the EWEN state, programming remains enabled until an EWDS instruction is executed or VCC power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory
location to the logical “1” state. The self-timed erase cycle starts once the Erase instruction and
address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought
high after being kept low for a minimum of 250 ns (tCS). A logic “1” at pin DO indicates that the
selected memory location has been erased and the part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written
into the specified memory location. The self-timed programming cycle tWP starts after the last bit
of data is received at serial data input pin DI. The DO pin outputs the Read/Busy status of the
part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic “0” at DO
indicates that programming is still in progress. A logic “1” indicates that the memory location at
the specified address has been written with the data pattern contained in the instruction and the
5
5193F–SEEPR–1/08
part is ready for further instructions. A Ready/Busy status cannot be obtained if the CS is
brought high after the end of the self-timed programming cycle tWP.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array
to the logic “1” state and is primarily used for testing purposes. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns
(tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the
data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if
CS is brought high after being kept low for a minimum of 250 ns (tCS). The WRAL instruction is
valid only at VCC = 5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write
Disable (EWDS) instruction disables all programming modes and should be executed after all
programming operations. The operation of the Read instruction is independent of both the
EWEN and EWDS instructions and can be executed at any time.
6
AT93C46D
5193F–SEEPR–1/08
AT93C46D
3. Timing Diagrams
Figure 3-1.
Synchronous Data Timing
μs
Note:
1. This is the minimum SK period.
Table 3-1.
Organization Key for Timing Diagrams
AT93C46D (1K)
Figure 3-2.
I/O
x8
x 16
AN
A6
A5
DN
D7
D15
READ Timing
tCS
High Impedance
7
5193F–SEEPR–1/08
Figure 3-3.
EWEN Timing
tCS
CS
SK
DI
Figure 3-4.
1
0
0
1
...
1
EWDS Timing
tCS
CS
SK
DI
Figure 3-5.
1
0
0
0
...
0
WRITE Timing
tCS
CS
SK
DI
DO
1
0
1
AN
...
A0
DN
...
D0
HIGH IMPEDANCE
BUSY
READY
tWP
8
AT93C46D
5193F–SEEPR–1/08
AT93C46D
Figure 3-6.
WRAL Timing(1)
tCS
CS
SK
1
DI
DO
0
0
0
1
...
DN
...
D0
BUSY
HIGH IMPEDANCE
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
Figure 3-7.
ERASE Timing
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
1
1
1
AN AN-1 AN-2
...
A0
tDF
tSV
DO
HIGH IMPEDANCE
HIGH IMPEDANCE
BUSY
READY
tWP
9
5193F–SEEPR–1/08
Figure 3-8.
ERAL Timing(1)
tCS
CS
CHECK
STATUS
STANDBY
tSV
tDF
SK
DI
DO
1
0
0
1
0
BUSY
HIGH IMPEDANCE
HIGH IMPEDANCE
READY
tWP
Note:
10
1. Valid only at VCC = 4.5V to 5.5V.
AT93C46D
5193F–SEEPR–1/08
AT93C46D
4. AT93C46D Ordering Information
Ordering Code
AT93C46D-PU (Bulk form only)
Voltage
Package
1.8
8P3
(1)
(NiPdAu Lead finish)
1.8
8S1
(2)
(NiPdAu Lead finish)
1.8
8S1
AT93C46DN-SH-B
AT93C46DN-SH-T
AT93C46D-TH-B(1) (NiPdAu Lead finish)
1.8
8A2
AT93C46D-TH-T(2) (NiPdAu Lead finish)
1.8
8A2
AT93C46DY6-YH-T(2) (NiPdAu Lead finish)
1.8
8Y6
(2)
1.8
8U3-1
1.8
Die Sale
AT93C46DU3-UU-T
AT93C46D-W-11(3)
Notes:
Operation Range
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
Industrial
(−40°C to 85°C)
1. “-B” denotes bulk
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini MAP, and dBGA2 = 5K per reel.
3. Available in tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request.
Please contact Serial Interface Marketing.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8U3-1
8-ball, Die Ball Grid Array Package (dBGA2)
8Y6
8-lead, 2.00 mm x 3.00 mm Body, 0.50mm Pitch, Ultra-Thin Mini-MAO, Dual No Lead Package. (DFN), (MLP 2x3mm)
Options
−1.8
Low Voltage (1.8V to 5.5V)
11
5193F–SEEPR–1/08
5. Part Marking Scheme
5.1
AT93C46D 8-PDIP
TOP MARK
Seal Year
| Seal Week
|
|
|
|---|---|---|---|---|---|---|---|
A
T
M
L
U
Y
W
W
Y = SEAL YEAR
6: 2006
0: 2010
7: 2007
8: 2008
9: 2009
1: 2011
2: 2012
3: 2013
|---|---|---|---|---|---|---|---|
4
6
D
52 = Week 52
|
Pin 1 Indicator (Dot)
Lot Number to Use ALL Characters in Marking
BOTTOM MARK
No Bottom Mark
AT93C46D 8-SOIC
TOP MARK
Seal Year
| Seal Week
|
|
|
|---|---|---|---|---|---|---|---|
A
T
M
L
H
Y
W
W
Y = SEAL YEAR
6: 2006
0: 2010
7: 2007
8: 2008
9: 2009
|---|---|---|---|---|---|---|---|
4
6
D
1: 2011
2: 2012
3: 2013
WW = SEAL WEEK
02 = Week 2
04 = Week 4
:: : :::: :
:: : :::: ::
50 = Week 50
1
|---|---|---|---|---|---|---|---|
*
Lot Number
|---|---|---|---|---|---|---|---|
|
Pin 1 Indicator (Dot)
12
04 = Week 4
:: : :::: :
:: : :::: ::
50 = Week 50
1
|---|---|---|---|---|---|---|---|
*
Lot Number
|---|---|---|---|---|---|---|---|
5.2
WW = SEAL WEEK
02 = Week 2
52 = Week 52
Lot Number to Use ALL Characters in Marking
BOTTOM MARK
No Bottom Mark
AT93C46D
5193F–SEEPR–1/08
AT93C46D
5.3
AT93C46D 8-TSSOP
TOP MARK
Pin 1 Indicator (Dot)
|
|---|---|---|---|
*
H
Y
W
W
|---|---|---|---|---|
4
6
D
Y = SEAL YEAR
6:
7:
8:
9:
2006
2007
2008
2009
0:
1:
2:
3:
WW = SEAL WEEK
2010
2011
2012
2013
1 *
02
04
::
::
=
=
:
:
Week
Week
::::
::::
2
4
:
::
50 = Week 50
|---|---|---|---|---|
52 = Week 52
BOTTOM MARK
|---|---|---|---|---|---|---|
C
0
0
|---|---|---|---|---|---|---|
A
A
A
A
A
A
A
|---|---|---|---|---|---|---|
<- Pin 1 Indicator
5.4
AT93C46D 8-Ultra Thin Mini MAP
TOP MARK
Y = YEAR OF ASSEMBLY
|---|---|---|
4
6
D
|---|---|---|
H
1
XX = ATMEL LOT NUMBER TO COORESPOND WITH
NSEB TRACE CODE LOG BOOK.
(e.g. XX = AA, AB, AC,...AX, AY, AZ)
|---|---|---|
Y
X
X
|---|---|---|
*
|
Pin 1 Indicator (Dot)
Y =
6:
7:
8:
SEAL YEAR
2006
0: 2010
2007
1: 2011
2008
2: 2012
9: 2009
3: 2013
13
5193F–SEEPR–1/08
5.5
AT93C46D dBGA2
TOP MARK
LINE 1------->
LINE 2------->
Y
4:
5:
6:
46DU
YMTC
|<-- Pin 1 This Corner
= ONE DIGIT YEAR CODE
2004
7: 2007
2005
8: 2008
2006
9: 2009
M = SEAL MONTH (USE ALPHA DESIGNATOR A-L)
A = JANUARY
B = FEBRUARY
" " """""""
J = OCTOBER
K = NOVEMBER
L = DECEMBER
TC = TRACE CODE (ATMEL LOT
NUMBERS TO CORRESPOND
WITH ATK TRACE CODE LOG BOOK)
14
AT93C46D
5193F–SEEPR–1/08
AT93C46D
6. Package Information
8P3 - PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
D1
A2 A
MIN
NOM
MAX
A2
0.115
0.130
0.195
b
0.014
0.018
0.022
5
b2
0.045
0.060
0.070
6
b3
0.030
0.039
0.045
6
SYMBOL
A
b2
b3
b
4 PLCS
Side View
L
2
c
0.008
0.010
0.014
D
0.355
0.365
0.400
3
D1
0.005
E
0.300
0.310
0.325
4
E1
0.240
0.250
0.280
3
0.150
2
e
3
0.100 BSC
eA
L
Notes:
0.210
NOTE
0.300 BSC
0.115
0.130
4
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO.
REV.
8P3
B
15
5193F–SEEPR–1/08
8S1 - JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
SIDE VIEW
Note:
SYMBOL
MIN
NOM
MAX
A
1.35
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.05
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
θ
0°
–
8°
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
3/17/05
R
16
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
8S1
REV.
C
AT93C46D
5193F–SEEPR–1/08
AT93C46D
8A2 - TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
b
D
MIN
NOM
MAX
NOTE
2.90
3.00
3.10
2, 5
4.40
4.50
3, 5
E
E1
e
D
A2
6.40 BSC
4.30
A
–
–
1.20
A2
0.80
1.00
1.05
b
0.19
–
0.30
e
Side View
L
0.65 BSC
0.45
L1
Notes:
4
0.60
0.75
1.00 REF
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
DRAWING NO.
8A2
REV.
B
17
5193F–SEEPR–1/08
8U3-1 – dBGA2
E
D
1.
b
A1
PIN 1 BALL PAD CORNER
A2
Top View
A
Side View
PIN 1 BALL PAD CORNER
1
2
3
4
8
7
6
5
(d1)
d
e
COMMON DIMENSIONS
(Unit of Measure - mm)
(e1)
SYMBOL
Bottem View
8 SOLDER BALLS
1. This drawing is for general information only.
2. Dimension 'b' is measured at maximum solder ball diameter.
MIN
NOM
MAX
A
0.73
0.79
0.85
A1
0.09
0.14
0.19
A2
0.40
0.45
0.50
b
0.20
0.25
0.30
D
1.50 BSC
E
2.0 BSC
e
0.50 BSC
e1
0.25 REF
d
1.00 BSC
d1
0.25 REF
NOTE
2
5/3/05
R
18
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,
Small Die Ball Grid Array Package (dBGA2)
DRAWING NO. REV.
PO8U3-1
B
AT93C46D
5193F–SEEPR–1/08
AT93C46D
8Y6 – MLP 2x3
D2
A
b
(8X)
E
E2
Pin 1
Index
Area
Pin 1 ID
L (8X)
D
A2
e (6X)
A1
1.50 REF.
COMMON DIMENSIONS
(Unit of Measure = mm)
A3
SYMBOL
MIN
2.00 BSC
E
3.00 BSC
MAX
D2
1.40
1.50
1.60
E2
-
-
1.40
A
-
-
0.60
A1
0.0
0.02
0.05
A2
-
-
0.55
A3
L
b
NOTE
0.20 REF
0.20
e
Notes:
NOM
D
0.30
0.40
0.50 BSC
0.20
0.25
0.30
2
1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
3. Soldering the large thermal pad is optional, but not recommended. No electrical connection is accomplished to the
device through this pad, so if soldered it should be tied to ground
10/16/07
R
2325 Orchard Parkway
San Jose, CA 95131
DRAWING NO.
TITLE
8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map,
8Y6
Dual No Lead Package (DFN) ,(MLP 2x3)
REV.
D
19
5193F–SEEPR–1/08
7. Revision History
20
Doc. Rev.
Date
Comments
5193F
1/2008
Removed ‘preliminary’ status
5193E
11/2007
Modified ‘max’ value in AC Characteristics table
5193D
8/2007
Moved Pinout figure
Added new feature for Die Sales
Modified Ordering Information table layout
Modified Park Marking Schemes
5193C
6/2007
Updated to new template
Added Product Markup Scheme
Added Technical email contact
5193C
3/2007
Corrected Figures 4 and 5.
5193B
2/2007
Added ‘Ultra Thin’ description to 8-lead Mini-MAP package.
5193A
1/2007
Initial document release.
AT93C46D
5193F–SEEPR–1/08
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5193F–SEEPR–1/08