PHILIPS BUK9775-55

Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic full-pack envelope using
’trench’ technology. The device
features very low on-state resistance
and has integral zener diodes giving
ESD protection up to 2kV. It is
intended for use in automotive and
general
purpose
switching
applications.
PINNING - SOT186A
PIN
BUK9775-55
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MAX.
UNIT
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
VGS = 5 V
55
11.7
19
150
75
V
A
W
˚C
mΩ
PIN CONFIGURATION
SYMBOL
DESCRIPTION
d
case
1
gate
2
drain
3
source
case isolated
g
s
1 2 3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
±VGS
ID
ID
IDM
Ptot
Tstg, Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
RGS = 20 kΩ
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
- 55
55
55
10
11.7
7.4
47
19
150
V
V
V
A
A
A
W
˚C
MIN.
MAX.
UNIT
-
2
kV
TYP.
MAX.
UNIT
-
6.5
K/W
55
-
K/W
ESD LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
VC
Electrostatic discharge capacitor
voltage, all pins
Human body model
(100 pF, 1.5 kΩ)
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
Rth j-mb
Thermal resistance junction to
heatsink
Thermal resistance junction to
ambient
with heatsink compound
Rth j-a
April 1998
in free air
1
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9775-55
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
V(BR)DSS
Drain-source breakdown
voltage
Gate threshold voltage
VGS = 0 V; ID = 0.25 mA;
VGS(TO)
Tj = -55˚C
VDS = VGS; ID = 1 mA
Tj = 150˚C
Tj = -55˚C
IDSS
Zero gate voltage drain current
VDS = 55 V; VGS = 0 V;
IGSS
Gate source leakage current
VGS = ±5 V; VDS = 0 V
±V(BR)GSS
Gate-source breakdown
voltage
Drain-source on-state
resistance
IG = ±1 mA;
RDS(ON)
Tj = 150˚C
Tj = 150˚C
VGS = 5 V; ID = 7 A
Tj = 150˚C
MIN.
TYP.
MAX.
UNIT
55
50
1
0.6
10
1.5
0.05
0.02
-
2
2.3
10
100
1
5
-
V
V
V
V
V
µA
µA
µA
µA
V
-
58
-
75
139
mΩ
mΩ
MIN.
TYP.
MAX.
UNIT
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
gfs
Forward transconductance
VDS = 25 V; ID = 10 A
5
10
-
S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
500
110
60
650
135
85
pF
pF
pF
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 10 A;
VGS = 5 V; RG = 10 Ω
Resistive load
-
10
47
28
33
15
70
40
45
ns
ns
ns
ns
Ld
Internal drain inductance
-
4.5
-
nH
Ls
Internal source inductance
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
-
7.5
-
nH
MIN.
TYP.
MAX.
UNIT
ISOLATION LIMITING VALUE AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL
PARAMETER
VISOL
R.M.S isolation voltage from all f = 50-60Hz; sinusoidal waveform;
three terminals to external
R.H.≤65% clean & dustfree
heatsink
-
-
2500
V
CISOL
Capacitance from T2 to
external heatsink
-
10
-
pF
April 1998
CONDITIONS
f = 1 MHZ
2
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9775-55
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL
PARAMETER
IDR
IDRM
VSD
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
trr
Qrr
Reverse recovery time
Reverse recovery charge
CONDITIONS
MIN.
TYP.
MAX.
UNIT
-
-
11.7
A
IF = 11.7 A; VGS = 0 V
-
0.95
47
1.2
A
V
IF = 11.7 A; -dIF/dt = 100 A/µs;
VGS = -10 V; VR = 30 V
-
32
0.12
-
ns
µC
MIN.
TYP.
MAX.
UNIT
-
-
30
mJ
AVALANCHE LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 10 A; VDD ≤ 25 V;
VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
April 1998
3
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
Normalised Power Derating
PD%
120
BUK9775-55
10
Zth/ (K/W)
110
0.5
100
90
0.2
80
1
70
0.1
0.05
60
50
0.02
40
0.1
p
D= t
T
tp
PD
0
30
t
T
20
10
0
0
20
40
60
80
100
Tmb / C
120
0.01
140
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
0.0001
0.01
t/s
1
100
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Normalised Current Derating
ID%
120
1.0E-06
50
110
ID/A
100
90
40
10.0
8.0
VGS/V =
6.0
5.4
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
10 2.0
80
30
70
60
50
20
40
30
20
10
10
0
0
20
40
60
80
Tmb / C
100
120
140
0
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
0
2
90
8
RDS(ON)/mOhm
tp =
VGS/V =
RDS(ON) = VDS/ID
85
1 uS
4
10 uS
4.6
4.8
75
100uS
4.2
4.4
80
10
5
70
DC
1
1 mS
65
10 mS
100 mS
0.1
VDS/V 6
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
100
ID/A
4
1
10
VDS/V
60
55
100
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
April 1998
5
10
15
ID/A
20
25
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
4
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9775-55
25
VGS(TO) / V
2.5
ID/A
BUK98xx-55
max.
20
2
typ.
15
1.5
10
1
5
0.5
min.
Tj/C =
0
150
0
1
25
2
VGS/V
3
4
0
-100
5
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
15
-50
0
50
Tj / C
100
150
200
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Transconductance, gfs (S)
Sub-Threshold Conduction
1E-01
14
13
1E-02
12
11
2%
1E-03
typ
98%
10
9
1E-04
8
7
1E-05
6
5
0
5
10
15
Drain current, ID (A)
20
25
1E-05
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
2.5
BUK98XX-55
a
0
0.5
1
1.5
2
2.5
3
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
1
Rds(on) normalised to 25degC
.9
.8
Thousands pF
2
1.5
.7
.6
.5
Ciss
.4
.3
1
.2
.1
0.5
-100
-50
0
50
Tmb / degC
100
150
0
0.01
200
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 10 A; VGS = 5 V
April 1998
Coss
Crss
0.1
1
VDS/V
10
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
5
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9775-55
6
120
110
VGS/V
5
WDSS%
100
VDS = 14V
90
4
80
VDS = 44V
70
60
3
50
40
2
30
20
1
10
0
0
0
2
4
6
QG/nC
8
10
20
12
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 20 A; parameter VDS
40
60
80
100
Tmb / C
120
140
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 17 A
100
VDD
+
IF/A
80
L
VDS
60
Tj/C =
150
25
-
VGS
-ID/100
40
0
20
0
T.U.T.
R 01
shunt
RGS
0
0.5
VSDS/V
1
1.5
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD )
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
+
VDD
RD
VDS
-
VGS
0
RG
T.U.T.
Fig.17. Switching test circuit.
April 1998
6
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9775-55
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
10.3
max
4.6
max
3.2
3.0
2.9 max
2.8
Recesses (2x)
2.5
0.8 max. depth
6.4
15.8
19
max. max.
15.8
max
seating
plane
3 max.
not tinned
3
2.5
13.5
min.
1
0.4
2
3
M
1.0 (2x)
0.6
2.54
0.9
0.7
0.5
2.5
5.08
1.3
Fig.18. SOT186A; The seating plane is electrically isolated from all terminals.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for F-pack envelopes.
3. Epoxy meets UL94 V0 at 1/8".
April 1998
7
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK9775-55
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1998
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
April 1998
8
Rev 1.000