Integrated Circuit Systems, Inc. ICS9147-12 Pentium/ProTM System and Cyrix Clock Chip General Description Features The ICS9147-12 is a Clock Synthesizer chip for Pentium and PentiumPro plus Cyrix CPU based Desktop/Notebook systems that will provide all necessary clock timing. Features include four CPU, seven PCI and eight SDRAM clocks. Three reference outputs are available equal to the crystal frequency, plus the IOAPIC output powered by VDDL. Additionally, the device meets the Pentium power-up stabilization, which requires that CPU and PCI clocks be stable within 2ms after power-up. High drive PCICLK and SDRAM outputs typically provide greater than 1V/ns slew rate into 30 pF loads. CPUCLK outputs typically provide better than 1V/ns slew rate into 20 pF loads while maintaining 50 ± 5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. Generates system clocks for CPU, IOAPIC, SDRAM, PCI, plus 14.318 MHz REF(0:2), USB, Plus Super I/O Supports single or dual processor systems Supports Intel 60, 66.8MHz, Cyrix 55, 75MHz plus 83.3 and 68MHz (Turbo of 66.6) speeds. Synchronous clocks skew matched to 250ps window on CPU, SDRAM and 500ps window on PCI clocks CPU clocks to PCI clocks skew 1-4ns (CPU early) Two fixed outputs, 48MHz and 24 MHz Separate 2.5V and 3.3V supply pins - 2.5V or 3.3V output: CPU, IOAPIC - 3.3V outputs: SDRAM, PCI, REF, 48/24 MHz No power supply sequence requirements 48 pin 300 mil SSOP The ICS9147-12 accepts a 14.318MHz reference crystal or clock as its input and runs on a 3.3V supply. Pin Configuration Block Diagram 48-Pin SSOP Power Groups VDD1 = REF (0:2), X1, X2 VDD2 = PCICLK_F, PCICLK (0:5) VDD3 = SDRAM (0:7), VDD4 = 48MHz, 24MHz VDDL = IOAPIC, CPUCLK (0:3) Pentium is a trademark on Intel Corporation. 9147-12 Rev A 072597P ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9147-12 Pin Descriptions PIN NUMBER 1 PIN NAME FS2 TYPE DESCRIPTION Latched input for frequency select2 1 IN REF1 OUT Reference clock output 2 REF0 OUT Reference clock output 3, 10, 17, 24, 31, 31, 37, 43 GND PWR Ground (common) Crystal or reference input, nominally 14.318 MHz. Includes internal load cap to GND and feedback resistor from X2. 4 X1 IN 5 X2 OUT 6, 20, N/C 7, 15 VDD2 PWR Supply for PCICLK_F, and PCICLK (0:5) PCICLK_F OUT Free running PCI clock PCICLK (0:5) OUT PCI clocks 8 9, 11, 12, 13, 14, 16 Crystal output, includes internal load cap to GND. - Pins are not internally connected 18 FS0 IN Frequency select 0 input 1 19 FS1 IN Frequency select 1 input 1 21 VDD4 PWR Supply for 48MHz and 24MHz clocks 22 48MHz OUT 48MHz driver output for USB clock 23 24MHz OUT 24MHz driver output for Super I/O clock 25, 28,34 VDD3 PWR Supply for SDRAM (0:7), 26, 27, 29, 30, 32, 33, 35, 36 SDRAM (0:7) OUT SDRAMs clock at CPU speed 38, 39, 41, 42 CPUCLK (0:3) OUT CPUCLK clock output, powered by VDDL VDDL PWR 40, 46 44 PD# 45 IOAPIC 47 48 Supply for CPUCLK (0:3) & IOAPIC Power down stops all clocks low and disables oscillator and internal VCO’s.2 IN OUT IOAPIC clock output, powered by VDDL at crystal frequency REF2 OUT Reference clock output. VDD1 PWR Supply for REF (0:2), X1, X2 Note 1: Internal pull-up resistor of nomimally 100K to 120K at 3.3V on indicated inputs. Note 2: The PD# input pin has a protection diode clamp to the VDDL power supply. If VDDL is not connected to VDD, (ie VDDL=2.5V, VDD=3.3V) then this input must have a series resistor if the logic high is connected to VDD. This input series resistor provides current limit for the clamp diode. For a pullup to VDD it should be 1Kohm or more from the PD# pin to VDD. If the PD# pin is being driven by logic powered by 3.3V, then a 100Ω series resistor will be suffcient. 2 ICS9147-12 Functionality VDD = 3.3V ±5%, VDDL = 2.5V ±5% or 3.3V ±5%, TA = 0 to 70°C Crystal (X1, X2) = 14.31818 MHz FS2 FS1 FS0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CPUCLK, SDRAM (MHz) 83.3 75 83.3 68.5 55 75 60 66.8 PCICLK (MHz) 1/2 CPU 30 33.3 1/2 CPU 1/2 CPU 1/2 CPU 1/2 CPU 1/2 CPU Power Management Functionality PD# CPUCLK Outputs PCICLK(0:5) Outputs PCICLK_F, REF, 24/48MHz and SDRAM Crystal OSC VCO 0 Stopped Low Stopped Low Stopped Low Off Off 1 Running Running Running Running Running 3 ICS9147-12 Technical Pin Function Descriptions VDD(1,2,3,4) This is the power supply to the internal core logic of the device as well as the clock output buffers for REF(0:2), PCICLK, 48/24MHz and SDRAM(0:7). SDRAM(0:7) These Output Clocks are use to drive Dynamic RAMs and are low skew copies of the CPU Clocks. The voltage swing of the SDRAMs output is controlled by the supply voltage that is applied to VDD3 of the device, operating at 3.3 volts. This supply operates at 3.3 volts. Clocks from the listed buffer that it supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels for the Clocks, please consult the DC parameter table in this data sheet. 48MHz This is a fixed frequency Clock output at 48MHz that is typically used to drive USB devices. VDDL This is the power supply for the CPUCLK and IOAPIC output buffers. The voltage level for these outputs may be 2.5 or 3.3 volts. Clocks from the buffers that each supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels of these Clocks, please consult the DC parameter table in this Data Sheet. 24MHz This pin is a fixed frequency clock output typically used to drive Super I/O devices. IOAPIC This Output is a fixed frequency Output Clock that runs at the Reference Input (typically 14.31818MHz) . Its voltage level swing is controlled by VDDL and may operate at 2.5 or 3.3volts. GND This is the power supply ground (common or negative) return pin for the internal core logic and all the output buffers. REF(0:2) The REF Outputs are fixed frequency Clocks that run at the same frequency as the Input Reference Clock X1 or the Crystal (typically 14.31818MHz) attached across X1 and X2. X1 This input pin serves one of two functions. When the device is used with a Crystal, X1 acts as the input pin for the reference signal that comes from the discrete crystal. When the device is driven by an external clock signal, X1 is the device input pin for that reference clock. This pin also implements an internal Crystal loading capacitor that is connected to ground. See the data tables for the value of this capacitor. Also includes feedback resistor from X2. PCICLK_F This Output is equivalent to PCICLK(0:5) and is FREE RUNNING. PCICLK (0:5) These Output Clocks generate all the PCI timing requirements for a Pentium/Pro based system. They conform to the current PCI specification. They run at 1/2 CPU frequency, or CPU/ 2.5; see frequency table. X2 This Output pin is used only when the device uses a Crystal as the reference frequency source. In this mode of operation, X2 is an output signal that drives (or excites) the discrete Crystal. The X2 pin will also implement an internal Crystal loading capacitor that is connected to ground. See the Data Sheet for the value of this capacitor. FS0,1,2 These Input pins control the frequency of the Clocks at the CPU, PCICLK and SDRAM output pins. See frequency table. The level of FS2 is latched at power-on, defined by a series resistor (typically 10K ohm) to VDD or GND. CPUCLK (0:3) These Output pins are the Clock Outputs that drive processor and other CPU related circuitry that requires clocks which are in tight skew tolerance with the CPU clock. The voltage swing of these Clocks is controlled by the Voltage level applied to the VDDL2 pin of the device. See the Functionality Table for a list of the specific frequencies that are available for these Clocks and the selection codes to produce them. PD# This input pin stops all clocks in the low state and powers down the oscillator and VCOs. 4 ICS9147-12 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 3.3V VDD = 3.0 3.7 V, TA = 0 70° C unless otherwise stated DC Characteristics PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Current SYMBOL VIL VIH IIL IIH IOL1a IOL1b Output High Current IOH1a IOH1b IOL2a Output Low Current IOL2b Output High Current IOH2a IOH2b Output Low Voltage VOL1a VOL1b Output High Voltage VOH1a VOH1b VOL2a Output Low Voltage VOL2b VOH2a Output High Voltage VOH2b Supply Current Supply Current Note 1: IDD IDDPD TEST CONDITIONS Latched inputs and Fulltime inputs Latched inputs and Fulltime inputs VIN = 0V (Fulltime inputs) VIN=VDD (Fulltime inputs) VOL = 0.8V; CPU, SDRAM, 48MHz; VDDL = 3.3V VOL = 0.8V; CPU; VDDL = 2.5V VOH = 2.0V; CPU, SDRAM, 48MHz; VDDL = 3.3V VOH = 2.0V; CPU; VDDL = 2.5V VOL = 0.8V; 24, PCI, REF, IOAPIC; VDDL = 3.3V VOL = 0.8V; IOAPIC; VDDL = 2.5V VOH = 2.0V for IOAPIC, PCI, REF, 24MHz at VDDL = 3.3V VOH = 2.0V; IOAPIC; VDDL = 2.5V IOL = 10mA; CPU, SDRAM, 48MHz; VDDL = 3.3V IOL = 10mA; CPU; VDDL = 2.5V IOH = -10mA; CPU, SDRAM, 48MHz; VDDL = 3.3V IOH = -10mA; CPU; VDDL = 2.5V IOL = 10mA; for IOAPIC, PCI, REF, 24MHz at VDDL= 3.3V IOL = 10mA; PCI, REF, IOAPIC; VDDL = 2.5V IOH = -10mA; for IOAPIC, PCI, REF, 24MHz at VDDL = 3.3V IOH = -10mA; IOAPIC; VDDL = 2.5V @66.6 MHz; all outputs unloaded Power Down Parameter is guaranteed by design and characterization. Not 100% tested in production. 5 MIN 0.7VDD -28.0 -5.0 TYP -10.5 - MAX 0.2VDD 5.0 UNITS V V µA µA 19.0 30.0 - mA 19.0 30.0 - -26.0 -16.0 mA mA -12.5 -9.5 mA 16.0 25.0 - mA 16.0 25.0 - -40.0 -14.0 mA -13.0 -4.0 mA 0.3 0.4 V 0.3 0.4 V 2.4 2.8 - V 1.95 2.1 - 0.3 0.4 V 0.3 0.4 V 2.4 2.8 - V 1.6 2.1 - V - 120 300 180 500 mA µA - mA V ICS9147-12 Electrical Characteristics at 3.3V VDD = 3.0 3.7 V, TA = 0 70° C unless otherwise stated AC Characteristics PARAMETER SYMBOL Rise Time1 Tr1a Rise Time1 Tr1b 1 ,3 Fall Time Rise Time1 Fall Time1 Rise Time1 Fall Time1 Tf1 Tr2 Tf2 Tr3 Tf3 Rise Time1,3 Tr4 Rise Time1 Tr4a Fall Time1 ,3 Tf4 Rise Time1 Tr5 Fall Time1 Tf5 1 Duty Cycle Jitter, Cycle to Cycle1 Dt Tjc-c Jitter, One Sigma1, 2 Tj1s1 Jitter, Absolute1 , 2 Tjab1 Jitter Absolute 1 Tjab1a Jitter, One Sigma1 Tj1s2 Jitter, Absolute1 Tjab2 1 Input Frequency Logic Input Capacitance1 Crystal Oscillator Capacitance 1 Fi CIN CINX Power-on Time1 ton Clock Skew1 Tsk1 Clock Skew1 Tsk2 1 Tsk2 Clock Skew Clock Skew1,2 Tsk3 Clock Skew1 Tsk4 TEST CONDITIONS 20pF load, 0.8 to 2.0V CPU, 48MHz; VDD = 3.3V 20pF load, 0.8 to 2.0V CPU; VDDL @ 2.5V 20pF load, 2.0 to 0.8V CPU, 48MHz; 30pF load SDRAM 0.8 to 2.0V 30pF load SDRAM 2.0 to 0.8V 30pF load PCI 0.8 to 2.0V 30pF load PCI 2.0 to 0.8V 20pF load, 0.8 to 2.0V 24MHz, REF (1:2) & IOAPIC 45pF load, 0.8 to 2.0V , IOAPIC with VDDL = 2.5V 20pF load, 2.0 to 0.8V 24MHz, REF (1:2) & IOAPIC Load = 45pF 0.8 to 2.0V REF0 VDD = 3.3V Load = 45pF 2.0 to 0.8V, REF0 VDD = 3.3V 20pF load @ VOUT=1.4V CPU, VDDL = 3.0 to 3.7V CPU; Load=20pF, SDRAM & BUS Clocks Load = 30pF CPU; Load=20pF, SDRAM & PCI Clocks Load = 30pF PCI; Load=30pF REF (1:2), 48/24MHz Load=20pF, REF0 CL = 45pF REF (1:2), 48/24MHz Load=20pF, REF0 CL = 45pF Logic input pins X1, X2 pins From VDD=1.6V to 1st crossing of 66.6 MHz VDD supply ramp < 40ms CPU to CPU; Load=20pF; @1.4V (Same VDD) SDRAM to SDRAM; Load=30pF @ 1.4V PCI to PCI; Load=20pF; @1.4V CPU(20pF) to PCI (30pF); @1.4V (CPU is early) SDRAM (30pF @3.3V) to CPU (20pF @2.5V) (2.5V CPU is late) Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. Note 2: Includes VDDL = 2.5V Note 3: VDD3 = 3.3V 6 MIN TYP MAX UNITS - 0.9 1.5 ns - 1.5 2.0 ns - 0.8 1.0 0.9 1.2 1.1 1.4 1.6 1.5 2.0 1.9 ns ns ns ns ns - 0.83 1.4 ns - 2.2 2.6 ns - 0.81 1.3 ns 1.6 2.0 ns 1.6 2.0 ns 45 50 250 55 300 % ps - 50 150 ps -250 - 250 ps -500 - 500 ps - 1 3 % -5 2 5 % 12.0 - 14.318 5 18 16.0 - MHz pF pF - 2.5 4.5 ms - 150 250 ps - 150 250 ps - 300 500 ps 1 2.6 4 ns 250 400 ps ICS9147-12 Shared Pin Operation Input/Output Pins Pins 1 and 2 on the ICS9147-12 serves as dual signal functions to the device. During initial power-up, it acts as an input pin. The logic level (voltage) that is present on this pin at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for this pin to an output function. In this mode the pin produces the specified buffered clocks to external loads. Figs. 1 and 2 show the recommended means of implementing this function. In Fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the devices internal logic. Figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. These figures illustrate the optimal PCB physical layout options. These configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. The layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s). To program (load) the internal configuration register for this pin, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm(10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Fig. 1 7 ICS9147-12 Fig. 2a Fig. 2b 8 ICS9147-12 SSOP Package SYMBOL A A1 A2 B C D E e H h L N ∝ X COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .006 .0085 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0° 5° 8° .085 .093 .100 VARIATIONS AC AD MIN. .620 .720 D NOM. .625 .725 N MAX. .630 .730 48 56 This table in inches Ordering Information ICS9147F-12 Example: ICS XXXX F - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 9 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.