TC74HC40102,40103AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC40102AP,TC74HC40102AF TC74HC40103AP,TC74HC40103AF TC74HC40102AP/AF TC74HC40103AP/AF Dual BCD Programmable Down Counter 8-Bit Binary Programmable Down Counter The TC74HC40102A and TC74HC40103A are high speed CMOS PROGRAMMABLE DOWN COUNTERS fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The output terminal ( CO/ZD ) goes to an active low state when the down count reaches zero. Since the TC74HC40102A is designed as a BCD counter, programming up to 99 counts is possible. The TC74HC40103A, with its 8-bit binary construction, can be set to provide up to 255 counts. Both devices have Inhibit Clock ( CI/CE ), Asynchronous Preset Control ( APE ), Synchronous Preset ( SPE ) and Clear Control ( CLR ) inputs for setting the counter to the maximum counting mode. All inputs are equipped with protection circuits against static discharge or transient excess voltage. TC74HC40102AP, TC74HC40103AP TC74HC40102AF, TC74HC40103AF Features • High speed: fmax 40 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Output drive capability: 10 LSTTL loads • • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) Balanced propagation delays: tpLH ∼ − tpHL • Wide operating voltage range: VCC (opr) = 2 to 6 V • Pin and function compatible with 40102B, 40103B Weight DIP16-P-300-2.54A SOP16-P-300-1.27A : 1.00 g (typ.) : 0.18 g (typ.) Pin Assignment 1 2007-10-01 TC74HC40102,40103AP/AF IEC Logic Symbol TC74HC40102A TC74HC40103A Truth Table Control Inputs Mode Functional Description CLR APE SPE CI/CE H H H H Count Inhibit H H H L Regular Count H H L X Synchronous Preset H L X X Asynchronous Preset Input data is asynchronously preset to CK L X X X Clear Count is inhibited regardless of other inputs. Down count on the rising edge of CK Input data is preset on the rising edge of CK Counter is set to maximum count. X: Don’t care Maximum count: TC74HC40102A “99”, TC74HC40103A “255” 2 2007-10-01 TC74HC40102,40103AP/AF Timing Chart 3 2007-10-01 TC74HC40102,40103AP/AF System Diagram TC74HC40102A TC74HC40103A 4 2007-10-01 TC74HC40102,40103AP/AF Logic Diagram Inputs Output CLR APE SPE J TE CK Q H X X X X X L L H H H H X H L H H L H X L L L H H X H L L H L X L L L L X L Qn L L L X L Qn L L L X H X Qn Function Description The TC74HC40102A and TC74HC40103A are 8-stage presettable synchronous down counters. Carry Out/Zero Detect ( CO/ZD ) is output at the “L” level for the period of 1 bit when the readout becomes “0”. The TC74HC40102A adopts binary coded decimal notation, making setting up to 99 counts possible. While the TC74HC40103A adopts 8-bit binary counter and can set up to 255 counts. Count Operation At the “H” level of control input of CLR , SPE and APE , the counter carries out down count operation one by one at the rise of pulse given to CK input. Count operation can be inhibited by setting Carry Input/clock Enable ( CI/CE ) to the “H” level. CO/ZD is output at the “L” level when the readout becomes “0”, but is not output even if the readout becomes “0” when CI/CE is at the “H” level, thus maintaining the “H” level. Synchronous cascade operation can be carried out by using CI/CE input and CO/ZD output. The contents of count jump to maximum count (99 for the TC74HC40102A and 255 for the TC74HC40103A) if clock is given when the readout is “0”. Therefore, operation of 100-frequency division and that of 256-frequency division are carried out for the TC74HC40102A and TC74HC40103A, respectively, when clock input alone is given without various kinds of preset operation. 5 2007-10-01 TC74HC40102,40103AP/AF Preset Operation and Reset Operation When Clear ( CLR ) input is set to the “L” level, the readout is set to the maximum count independently of other inputs. When Asynchronous Preset Enable ( APE ) input is set to the “L” level, readouts given on J0 to J7 can be preset asynchronously to counter independently of inputs other than CLR input. When Synchronous Preset Enable ( SPE ) is set to the “L” level, the readouts given on J0 to J7 can be preset to counter synchronously with rise of clock. As to these operation modes, refer to the truth table. Absolute Maximum Ratings (Note 1) Characteristics Symbol Rating Unit Supply voltage range VCC −0.5 to 7 V DC input voltage VIN −0.5 to VCC + 0.5 V DC output voltage VOUT −0.5 to VCC + 0.5 V Input diode current IIK ±20 mA Output diode current IOK ±20 mA DC output current IOUT ±25 mA DC VCC/ground current ICC ±50 mA Power dissipation PD 500 (DIP) (Note 2)/180 (SOP) mW Storage temperature Tstg −65 to 150 °C Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C shall be applied until 300 mW. Operating Ranges (Note) Characteristics Symbol Rating Unit Supply voltage VCC 2 to 6 V Input voltage VIN 0 to VCC V VOUT 0 to VCC V Topr −40 to 85 °C Output voltage Operating temperature 0 to 1000 (VCC = 2.0 V) Input rise and fall time tr, tf 0 to 500 (VCC = 4.5 V) ns 0 to 400 (VCC = 6.0 V) Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. 6 2007-10-01 TC74HC40102,40103AP/AF Electrical Characteristics DC Characteristics Characteristics High-level input voltage Low-level input voltage VCC (V) Min Typ. Max Min Max 2.0 1.50 ⎯ ⎯ 1.50 ⎯ 4.5 3.15 ⎯ ⎯ 3.15 ⎯ 6.0 4.20 ⎯ ⎯ 4.20 ⎯ 2.0 ⎯ ⎯ 0.50 ⎯ 0.50 4.5 ⎯ ⎯ 1.35 ⎯ 1.35 6.0 ⎯ ⎯ 1.80 ⎯ 1.80 2.0 1.9 2.0 ⎯ 1.9 ⎯ 4.5 4.4 4.5 ⎯ 4.4 ⎯ 6.0 5.9 6.0 ⎯ 5.9 ⎯ IOH = −4 mA 4.5 4.18 4.31 ⎯ 4.13 ⎯ IOH = −5.2 mA 6.0 5.68 5.80 ⎯ 5.63 ⎯ 2.0 ⎯ 0.0 0.1 ⎯ 0.1 4.5 ⎯ 0.0 0.1 ⎯ 0.1 6.0 ⎯ 0.0 0.1 ⎯ 0.1 IOL = 4 mA 4.5 ⎯ 0.17 0.26 ⎯ 0.33 IOL = 5.2 mA 6.0 ⎯ 0.18 0.26 ⎯ 0.33 ⎯ VIH ⎯ VIL IOH = −20 μA High-level output voltage VOH VIN = VIH or VIL IOL = 20 μA Low-level output voltage VOL Ta = −40 to 85°C Ta = 25°C Test Condition Symbol VIN = VIH or VIL Unit V V V V Input leakage current IIN VIN = VCC or GND 6.0 ⎯ ⎯ ±0.1 ⎯ ±1.0 μA Quiescent supply current ICC VIN = VCC or GND 6.0 ⎯ ⎯ 4.0 ⎯ 40.0 μA Test Condition Min Typ. Max Unit ⎯ ⎯ 4 8 ns ⎯ ⎯ 25 43 ns ⎯ ⎯ 25 49 ns ⎯ ⎯ 10 19 ns tpLH ⎯ ⎯ 24 36 ns fmax ⎯ 23 40 ⎯ MHz AC Characteristics (CL = 15 pF, VCC = 5 V, Ta = 25°C, input: tr = tf = 6 ns) Characteristics Output transition time Symbol tTLH tTHL Propagation delay time tpLH (CK- CO/ZD ) tpHL Propagation delay time tpLH ( APE - CO/ZD ) tpHL Propagation delay time tpLH ( CI/CE - CO/ZD ) tpHL Propagation delay time ( CLR - CO/ZD ) Maximum clock frequency 7 2007-10-01 TC74HC40102,40103AP/AF AC Characteristics (CL = 50 pF, input: tr = tf = 6 ns) Characteristics Output transition time Symbol tTLH tTHL Propagation delay time tpLH (CK- CO/ZO ) tpHL Propagation delay time tpLH ( APE - CO/ZO ) tpHL Propagation delay time tpLH ( CI/CE - CO/ZO ) tpHL Propagation delay time tpLH fmax Input capacitance CIN Power dissipation capacitance CPD Note: (Note) Unit VCC (V) Min Typ. Max Min Max 2.0 ⎯ 30 75 ⎯ 95 4.5 ⎯ 8 15 ⎯ 19 6.0 ⎯ 7 13 ⎯ 16 2.0 ⎯ 95 245 ⎯ 305 4.5 ⎯ 28 49 ⎯ 61 6.0 ⎯ 22 42 ⎯ 52 2.0 ⎯ 100 300 ⎯ 375 4.5 ⎯ 30 60 ⎯ 75 6.0 ⎯ 25 51 ⎯ 64 2.0 ⎯ 38 115 ⎯ 145 4.5 ⎯ 13 23 ⎯ 29 6.0 ⎯ 11 20 ⎯ 25 2.0 ⎯ 85 240 ⎯ 300 4.5 ⎯ 28 48 ⎯ 60 6.0 ⎯ 23 41 ⎯ 51 2.0 4 12 ⎯ 3 ⎯ 4.5 20 36 ⎯ 16 ⎯ 6.0 24 42 ⎯ 19 ⎯ ⎯ ⎯ 5 10 ⎯ 10 pF ⎯ ⎯ 48 ⎯ ⎯ ⎯ pF ⎯ ⎯ ⎯ ⎯ ⎯ ( CLR - CO/ZO ) Maximum clock frequency Ta = −40 to 85°C Ta = 25°C Test Condition ⎯ ns ns ns ns ns ns CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD･VCC･fIN + ICC 8 2007-10-01 TC74HC40102,40103AP/AF Timing Requirements (input: tr = tf = 6 ns) Characteristics Symbol Minimum pulse width tW (H) (CK) tW (L) Minimum pulse width ( CLR , APE ) Minimum set-up time ( SPE -CK) Minimum set-up time ( CI/CE -CK) Minimum set-up time (Jn-CK) Minimum set-up time (Jn- APE ) Minimum hold time ( SPE -CK) Minimum hold time ( CI/CE -CK) Minimum hold time (Jn-CK) Minimum hold time (Jn- APE ) Minimum removal time ( CLR , APE ) Clock frequency Ta = 25°C Test Condition ⎯ ⎯ tW (L) ⎯ ts ⎯ ts ⎯ ts ⎯ ts ⎯ th ⎯ th ⎯ th ⎯ th ⎯ trem ⎯ f 9 Ta = −40 to 85°C VCC (V) Typ. Limit Limit 2.0 ⎯ 75 95 4.5 ⎯ 15 19 6.0 ⎯ 13 16 2.0 ⎯ 75 95 4.5 ⎯ 15 19 6.0 ⎯ 13 16 2.0 ⎯ 75 95 4.5 ⎯ 15 19 6.0 ⎯ 13 16 2.0 ⎯ 150 190 4.5 ⎯ 30 38 6.0 ⎯ 26 32 2.0 ⎯ 75 95 4.5 ⎯ 15 19 6.0 ⎯ 13 16 2.0 ⎯ 75 95 4.5 ⎯ 15 19 6.0 ⎯ 13 16 2.0 ⎯ 0 0 4.5 ⎯ 0 0 6.0 ⎯ 0 0 2.0 ⎯ 0 0 4.5 ⎯ 0 0 6.0 ⎯ 0 0 2.0 ⎯ 0 0 4.5 ⎯ 0 0 6.0 ⎯ 0 0 2.0 ⎯ 0 0 4.5 ⎯ 0 0 6.0 ⎯ 0 0 2.0 ⎯ 75 95 4.5 ⎯ 15 19 6.0 ⎯ 13 16 2.0 ⎯ 4 3 4.5 ⎯ 20 16 6.0 ⎯ 24 19 Unit ns ns ns ns ns ns ns ns ns ns ns MHz 2007-10-01 TC74HC40102,40103AP/AF Switching Characteristics Test Waveform (Note) Waveform 1 Waveform 2 Waveform 3 Waveform 4 Waveform 5 Waveform 6 (Note) Note: (Note) F/F output is internal signal of IC 10 2007-10-01 TC74HC40102,40103AP/AF Example of Typical Application Programmable Divide-by-N Counter Parallel Carry Cascading (Note) (Note) Note: At synchronous cascade connection, huzzerd occurs at C0 output after its second stage when digit place changes, due to delay arrival. Therefore, take gate form TC74HC32A or the like, not form C0 output at the rear stage directly. Programmable Timer (Note) Note: The above formula dose not take into account the phase of ck input. Therefore, the real pulse width is the distance between the above formula-1/fIN to the above formula. 11 2007-10-01 TC74HC40102,40103AP/AF Package Dimensions Weight: 1.00 g (typ.) 12 2007-10-01 TC74HC40102,40103AP/AF Package Dimensions Weight: 0.18 g (typ.) 13 2007-10-01 TC74HC40102,40103AP/AF RESTRICTIONS ON PRODUCT USE 20070701-EN GENERAL • The information contained herein is subject to change without notice. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. 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Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 14 2007-10-01