TD7623AFN TENTATIVE TOSHIBA BIPOLAR DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TD7623AFN 2 3-WIRE AND I C BUS SYSTEM, 2.3 GHz DIRECT TWO MODULUS-TYPE FREQUENCY SYNTHESIZER FOR CATV The TD7623AFN can be combined with a micro CPU to create a highly functional frequency synthesizer. The control data conforms to 3-wire bus and standard I2C bus formats. BUS-SW can be used to easily switch for easy tuner system set-up. FEATURES l Direct two modulus-type frequency synthesizer l Standard I2C bus format control with built-in read mode l 3-wire bus 27-bit format control l 4-bit bandswitch drive transistor l 5-level A / D converter (when I2C bus selected) l Frequency step : 50 kHz, 62.5 kHz, 250 kHz, and 333.3 kHz (at 4 MHz X'tal used) Weight: 0.07 g (Typ.) l Phase lock detector l Various function settings via program data l Four address settings via address selector (when I2C bus selected) l Power on reset circuit l Flat, compact package : SSOP16 (0.65 mm pitch) l Power on reset operation condition Bandswitch register 1 to 4 : OFF Tuning amplifier : ON Tuning Voltage output (Vt) : High Level Charge-pump output current : ±200 µA Phase comparator reference frequency divider ratio : 1 / 80 Note: These devices are easy to be damaged by high static voltage or electric fields. In regards to this, please handle with care. To input sub features items. 000707EBA1 · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 2001-03-01 1/19 TD7623AFN BLOCK DIAGRAM MAXIMUM RATINGS (Ta = 25°C) CHARACTERISTIC SYMBOL RATING UNIT Supply Voltage 1 VCC1 6.0 V Supply Voltage 2 VCC2 12 V Power Consumption PD 560 mW Operating Temperature Topr −20~85 °C Storage Temperature Tstg −55~150 °C Note 1: When using the device at above Ta = 25°C, decrease the power dissipation by 4.5 mW for each increase of 1°C. Note 2: These devices are easy to be damaged by high static voltage or electric fields. In regards to this, please handle with care. RECOMMENDED SUPPLY VOLTAGE PIN No. PIN NAME 3 VCC1 : PLL Power Supply 4 VCC2 : Band Switch Power Supply MIN TYP. MAX UNIT 4.5 5.0 5.5 V VCC1 ― 9.9 V 2001-03-01 2/19 TD7623AFN PIN INTERFACE 2001-03-01 3/19 TD7623AFN ELECTRICAL CHARACTERISTICS (Unless otherwise specified, VCC1 = 5 V, VCC2 = 9 V, Ta = 25°C) SYMBOL TEST CIRCUIT TEST CONDITION MIN TYP. MAX UNIT Supply Voltage 1 VCC1 ― ― 4.5 5.0 5.5 V Supply Current 1 ICC1 1 24 32 40 mA Supply Voltage 2 VCC2 ― VCC1 ― 9.9 V Bandswitch : 1 Band ON IBD = 20 mA (LOAD) ― 24 26 Bandswitch : 2 Band ON IBD = 30 mA (TOTAL LOAD) ― 38 42 CHARACTERISTIC ICC2-1 1 Supply Current 2 ICC2-2 Bandswitch Drive Current Bandswitch : OFF Vt : OFF ― mA IBD 3 Maximum Drive Current / 1 port ― ― 20 mA IBDMAX 3 Maximum Total Drive Current ― ― 40 mA VBD Sat 3 IBD = 20 mA ― 0.2 0.4 V X’tal Operating Range OSCfin ― ― 3.2 ― 4.5 MHz X’tal Negative Resistance OSCR 1 ― 1.0 1.5 ― kΩ X’tal External Input Level OSCin ― 3.2 MHz~4.5 MHz, Rx = 91 kΩ 250 ― 1000 mVp-p N ― 15-bit counter 1024 ― 32767 Ratio Prescaler Input Sensitivity VinRF 2 f = 500~2300 MHz −15 ― +5 dBmW Lock Output Low Voltage VLkL 1 (lock mode, 3-wire bus mode) ― ― 0.4 V Lock Output High Voltage VLkH 1 (unlock mode, 3-wire bus mode) 4.6 ― ― V Logic Input Low Voltage VBsL 1 Pins 13 to 15 −0.3 ― 1.5 V Logic Input High Voltage VBsH 1 Pins 13 to 15 2.5 ― VCC1 +0.3 V Logic Input Current (low) IBsL 1 Pins 13 to 15 −20 ― 10 Logic Input Current (high) IBsH 1 Pins 13 to 15 −10 ― 20 BUS-SW Low Input Voltage VBIL 1 ― 0.0 ― 0.8 BUS-SW High Input Voltage VBIH 1 ― 4.2 ― VCC1 BUS-SW Low Current (low) IBIL 1 ― −200 ― ― BUS-SW Low Current (high) IBIH 1 ― ― ― 200 Charge Pump Output Current Ichg 2 CP = [0] ±150 ±200 ±300 CP = [1] ±600 ±800 ±1200 VACK 1 ― ― 0.4 Bandswitch Drive Maximum LOAD Bandswitch Drive Voltage Drop Ratio Setting Range ACK Output Voltage 2 ISINK = 3 mA (I C-bus mode) 2001-03-01 µA V µA µA V 4/19 TD7623AFN CHARACTERISTIC SYMBOL TEST CIRCUIT TEST CONDITION MIN TYP. MAX Set-up Time Ts 2 ― ― Enable Hold Time TsL 2 ― ― Next Enable Stop Time TNE 6 ― ― 6 ― ― Next Clock Stop Time (3-wire bus mode) Refer to data timing chart TNC Clock Width Tc 2 ― ― Enable Set-up Time TL 10 ― ― Data Hold Time TH 2 ― ― SCL Clock Frequency fSCL ― ― 100 Bus Free Time Between a STOP and START Condition tBUF 4.7 ― ― 4.0 ― ― 4.7 ― ― 4.0 ― ― 4.7 ― ― Hold Time (Repeated) START Condition tHD;STA Low Period of the SCL Clock tLOW High Period of the SCL Clock tHIGH ― UNIT µs kHz µs 2 (I C bus mode) Refer to data timing chart Set-up Time for a Repeated START Condition tSU;STA Data Hold Time tHD;DAT 0 ― ― Data Set-up Time tSU;DAT 250 ― ― Rise Time of both SDA and SCL Signals tR ― ― 1000 Fall Time of both SDA and SCL Signals tF ― ― 300 Set-up Time for STOP Condition tSU;STO 4.0 ― ― 2001-03-01 ns µs 5/19 TD7623AFN Fig.1 Fig.2 3-wire bus data timing chart (Falling edge timing) 2 I C bus data timing chart (Falling edge timing) 2001-03-01 6/19 TD7623AFN OPERATION INSTRUCTIONS The TD7623AFN can be controlled with either the 3-wire bus or standard I2C bus. The 3-wire bus mode, the device is controlled by 27-bit serial data. The I2C bus conforms to the standard I2C bus format. The bus supports two-way bus communications control, consisting of WRITE mode where data are received and READ mode where data are transmitted. In READ mode, the voltage applied on the A / D converter input pin can be transmitted and output with 5-level resolution. (This function is only valid when the I2C bus is selected. When the 3-wire bus is selected, the A / D converter input pin function as the LOCK output pin.) Addresses can be set using the hardware bits. Three programmable addresses are supported. 3-wire bus and standard I2C bus are switches by the voltage applied on the BUS-SW pin. The power-on reset circuit is built in this product, and the detection voltage is designed about 1.4 V. If it raises to voltage of operation after making it stop for a while near the voltage of a power-on reset circuit of operation at the time of starting of a power supply, a power-on reset circuit may not operate normally. FUNCTION CHART NAME 2 3-WIRE BUS MODE I C BUS MODE BUS-SW [VCC] [GND] CL / SCL CLOCK INPUT SCL INPUT DA / SDA DATA INPUT SDA IN / OUTPUT EN / ADR ENABLE INPUT ADDRESS LOCK ADC LOCK / ADC ― 3-WIRE BUS COMMUNICATIONS CONTROL ― The 3-wire bus mode, the device is controlled by 27-bit serial data. The 3-wire bus sets the following data : (bandswitch information and programmable counter information, charge-pump current setting, reference frequency divider ratio setting, and testing item functions.) The program frequency can be calculated in the following formula : fosc = fr × N fosc : Program frequency fr : Phase comparator reference frequency (Step frequency) N : Counter total ratio 2001-03-01 7/19 TD7623AFN Figure 3. 3-wire bus data format l 27-bit DATA TRANSMISSION During a high level of the enable signal, the data is clocked into the register on the falling edge of the clock. The clock number during a high level of the enable signal must be set to 27-bit or more of clock and data transmission. The data are latched at the 27th falling edge of the clock signal, validating the previous 27-bit data. The 4-bit bandswitch data are latched at the 5th bit rising edge of the clock signal, and the data is updated. The programmable counter data are latched at the 20th bit rising edge of the clock signal, and the data is updated. The control data are latched at the 27th bit falling edge of the clock signal, and the data is updated. Details of the data timing, see the data timing chart. (Figure 1) 2001-03-01 8/19 TD7623AFN TEST DATA SPECIFICATIONS l B4~B1 : Band drive data [0] : OFF [1] : ON l N14~N0 : Programmable divider data l CP : Charge pump output current [0] : ±200 µA (Typ.) [1] : ±800 µA (Typ.) l T2, T1, T0 : Test mode setting bits CHARACTERISTIC T2 T1 T0 NOTE Normal operation 0 0 1 ― Reference signal output 1 0 0 Reference signal output : B4, Counter output : B2 1 / 2 counter divider output 1 0 1 Reference signal output : B4, 1 / 2 counter output : B2 Phase comparator test 0 0 0 Comparative signal input : DA Reference signal input : CL (check output : NF) Note: When testing the counter divider output, programmable counter data input is necessary. l RSa, RSb : X’tal Reference frequency divider ratio select bits RSa RSb DIVIDER RATIO STEP FREQUENCY TUNING FREQUENCY 0 0 1 / 12 333.3 k 500 MHz~~2300 MHz 0 1 1 / 16 250.0 k 500 MHz~2300 MHz 1 0 1 / 64 62.5 k 500 MHz~2000 MHz 1 1 1 / 80 50.0 k 500 MHz~1600 MHz l OS : Tuning amplifier control bit [0] : Tuning amp ON (Normal operation) [1] : Tuning amp OFF (Tr. Output is Low Level) l × : Don’t care 2001-03-01 9/19 TD7623AFN 2 ― I C BUS COMMUNICATIONS CONTROL― The TD7623AFN conform to standard I2C bus format. The I2C bus mode enables two-way bus communications with the WRITE mode, which receives data, and READ mode, which status data. WRITE and READ mode are set using the last bit (R / W bit) of the address byte. If the last address bit is set to [0], WRITE mode is set ; if set to [1] READ mode is set. Address can be set using the hardware bits. Three programmable address can be programmed. With this setting, multiple frequency synthesizers can be used in the same I2C bus line. The address for the hardware bit setting can be selected by applying voltage to the address setting pin (ADR : Pin 15). An address is selected according to the set bits. When the correct address byte is received, during acknowledgment, serial data (SDA) line is “Low”. If WRITE mode is set at this time, when the data byte is programmed, the serial data (SDA) line is “Low” during the next acknowledgment. a) WRITE mode (setting command) When WRITE mode is set, Byte 1 segment the address data ; Bytes 2 and 3 segment the frequency data ; Byte 4 segment the divider ratio setting and function setting data ; and Byte 5 segment the output port data. Data are latched and transferred at the end of Byte 3, Byte 4 and Byte 5. Byte 2 and Byte 3 are latched and transferred is done with a two byte set (Byte 2+Byte 3). Once a correct address is received and acknowledged, the data type is determined according to [0] or [1]set in the first bit of the next byte. That is, if the first bit is [0], the data are frequency data ; if [1], function setting or output port data. Until the I2C bus STOP CONDITION is detected, the additional data can be input without transmitting the address again. (Ex : Frequency sweep is possible with additional frequency data.) If data transmission is aborted, data programmed before the abort are valid. Byte 1 can set the hardware bit with address data. The hardware bit is set with voltage applied to the address setting pin (ADR : Pin 15). Bytes 2 and 3 are stored in the 15-bit shift register with counter data for the frequency setting, and control the 15-bit programmable counter ratio. The program frequency can be calculated in the following formula : fosc = fr × N fosc : Program frequency fr : Phase comparator reference frequency (Step frequency) N : Counter total ratio fr is calculated using the crystal oscillator frequency and the reference frequency divider ratio set in Byte 4 (control byte). (fr = X’tal oscillator frequency / reference frequency divider ratio) The reference frequency divider ratio can be set to 1 / 12, 1 / 16, 1 / 64 and 1 / 80. When using a 4 MHz crystal oscillator, fr = 333.33 kHz, 250 kHz, 62.5 kHz and 50 kHz. The step frequency are 333.33 kHz, 250 kHz, 62.5 kHz and 50 kHz. Byte 4 is a control byte used to set function. Bit 2 (CP) controls the output current of the charge-pump circuit. When bit 2 is set to [0] : the output current is set to ±200 µA ; when set to [1] , ±800 µA. Bit 3 (T2), Bit 4 (T1) and Bit 5 (T0) are used to set test mode. They are used to set the phase comparator reference signal output, and counter divider output. For details of test mode, see the test mode setting table. Bit 6 (RSa) and Bit 7 (RSb) are used to set the X’tal reference frequency divider ratio. For details of the X’tal reference frequency divider ratios, see the table for X’tal reference frequency divider ratios. Bit 8 (OS) is used to set the charge-pump drive amplifier output setting. When bit 8 is set to [0] the output is ON (Normal Use) ; when set to [1] the output is OFF (Tr. Output is Low Level). Byte 5 is used to set and control the output port (Bands 1~4). When an output port set to [0] is OFF ; when set to [1] is ON. Two output ports can be operation turned on, but be sure to keep the total output current under 40 mA. 2001-03-01 10/19 TD7623AFN b) READ mode (status request) When READ mode is set, power-on reset operation status, phase comparator lock detector output status, and 5-level A / D converter pin input voltage status are output to the master device. Bit 1 (POR) indicates the power-on reset operation status. When the power supply of VCC1 stops, bit 1 is set to [1] . The condition for reset to [0] , voltage supplied to VCC1 is 3 V or higher, transmission is requested in READ mode, and the status is output. (when VCC1 is turned on, bit 1 is also set to [1] .) Bit 2 (FL) indicates the phase comparator lock status. When locked, [1] is output ; when unlocked, [0] is output. Bit 6, 7 and 8 (A2, A1, A0) indicate the 5-level A / D converter status. The voltage applied to the A / D converter input pin (pin 12) is output through a 5-level resolution. For the voltage applied on the A / D converter input pin, 5-level resolution, and the output bits, see the table. (Ex : The AFT output voltage data can be given to the master device.) 2001-03-01 11/19 TD7623AFN DATA FORMAT a) WRITE MODE BYTE MSB LSB 1 Address Byte 1 1 0 0 0 MA1 MA0 R / W=0 ACK 2 Divider Byte (1) 0 N14 N13 N12 N11 N10 N9 N8 ACK 3 Divider Byte (2) N7 N6 N5 N4 N3 N2 N1 N0 ACK (L) 4 Control Byte 1 CP T2 T1 T0 RSa RSb OS ACK (L) 5 Band SW Byte × × × × B4 B3 B2 B1 ACK (L) × ACK (L) : : : DON’T Care Acknowledged Latch and transfer timing b) READ MODE BYTE 1 Address Byte 2 Status Byte MSB LSB 1 1 0 0 0 MA1 MA0 R/W=1 ACK POR FL 1 1 1 A2 A1 A0 ― ACK : Acknowledged DATA SPECIFICATIONS l MA1, MA0 : Programmable hardware address bits ADDRESS PIN APPLIED VOLTAGE MA1 MA0 0~0.1 VCC1 0 0 0.4 VCC1~0.6 VCC1 1 0 0~VCC1 0 1 0.9 VCC1~VCC1 1 1 l CP : Charge-pump output current setting [0] : ±200 µA (Typ.) [1] : ±800 µA (Typ.) 2001-03-01 12/19 TD7623AFN l T2, T1, T0 : Test mode setting CHARACTERISTIC T2 T1 T0 NOTE Normal operation 0 0 1 ― Reference signal output 1 0 0 Reference signal output : B4, Counter output : B2 1 / 2 counter divider output 1 0 1 Reference signal output : B4, 1 / 2 counter output : B2 Phase comparator test 0 0 0 Note: Comparative signal input : SDA Reference signal input : SCL (check output : NF) When testing the counter divider output, programmable counter data input is necessary. l RSa, RSb : X’tal reference frequency divider ratio select bits RSa RSb DIVIDER RATIO STEP FREQUENCY TUNING FREQUENCY 0 0 1 / 12 333.3 k 500 MHz~2300 MHz 0 1 1 / 16 250.0 k 500 MHz~2300 MHz 1 0 1 / 64 62.5 k 500 MHz~2000 MHz 1 1 1 / 80 50.0 k 500 MHz~1600 MHz l OS : Tuning amplifier control setting [0] : Tuning amp ON (Normal operation) [1] : Tuning amp OFF (Tr. Output is Low Level) l POR : Power-on reset flag [0] : Normal operation [1] : Reset operation l FL : Lock detect flag [0] : Unlocked [1] : Locked l A2, A1, A0 : 5-level A / D converter status. ADC PIN APPLIED VOLTAGE A2 A1 A0 0.60 VCC1~VCC1 1 0 0 0.45 VCC1~0.60 VCC1 0 1 1 0.30 VCC1~0.45 VCC1 0 1 0 0.15 VCC1~0.30 VCC1 0 0 1 0~0.15 VCC1 0 0 0 *: Accuracy is ±0.03 × VCC1 l X : DON’T Care 2001-03-01 13/19 TD7623AFN 2 I C BUS CONTROL SUMMARY The bus control format of TD7623AFN conforms to the Philips I2C bus control format. Data transmission format S P A (1) Start / Stop condition (2) Bit transfer (3) Acknowledge (4) Slave address : Start condition : Stop condition : Acknowledge A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 0 0 * * 0 Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 2001-03-01 14/19 TD7623AFN TEST CIRCUIT 1 Evaluation circuit board TEST CIRCUIT 2 Input sensitivity test circuit Test mode circuit 2001-03-01 15/19 TD7623AFN TEST CIRCUIT 3 Bandswitch drive test circuit SYSTEM APPLICATION DIAGRAM 2001-03-01 16/19 TD7623AFN TYPICAL INPUT SENSITIVITY CURVE FILTER COMPONENT EXPRESSION C1 R1 C2 with Kv Icomp ωn N ε fc = [Kv * Icomp/(2π)] / (ωn2 * N) = [2 * ε] / (ωn * C1) = 1 / (2π * fc * R1) : = Oscillator control sensitivity (radian / Second / Volts) = Charge-pump current (A) = Natural radian frequency (radian / Second) = Total counter ratio = Dumping-factor (generally : dumping-factor is about 0.5~1.0) = filter cut-off frequency with combination resistor R1. (generally : fc is about fr (reference frequency) / 20) 2001-03-01 17/19 TD7623AFN HANDLING PRECAUTIONS 1. The device should not be inserted into or removed from the test jig while the voltage is being applied: otherwise the device may be degraded or break down. Do not abruptly increase or decrease the power supply to the device either. (See Figure 1.) Overshoot or chattering of the power supply may cause the IC to be degraded. To avoid this filters should be incorporated on the power supply line. 2. The peripheral circuits described in this datasheet are given only as system examples for evaluating the device's performance. Toshiba intend neither to recommend the configuration or related values of the peripheral circuits nor to manufacture such application systems in large quantities. Please note that high-frequency characteristics of the device may vary depending on the external components, mounting method and other factors relating to the application design. Therefore, the characteristics of application circuits must be evaluated at the responsibility of the users incorporating the device into their design. Toshiba only guarantee the quality and characteristics of the device as described in this datasheet and do not assume any responsibility for the customers application design. 3. In order to better understand the quality and reliability of Toshiba semiconductor products and to incorporate them into design in an appropriate manner, please refer to the latest Semiconductor Reliability Handbook (Integrated Circuits) published by Toshiba Semiconductor Company. The handbook can also be viewed online at http://doc.semicon.toshiba.co.jp/noseek/us/sinrai/sinraifm.htm. 2001-03-01 18/19 TD7623AFN PACKAGE DIMENSIONS Weight: 0.07 g (Typ.) 2001-03-01 19/19