FINAL COM’L: -4/5/7/B/B-2/A, D/2 Advanced Micro Devices PAL16R8 Family 20-Pin TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS ■ As fast as 4.5 ns maximum propagation delay ■ Power-up reset for initialization ■ Popular 20-pin architectures: 16L8, 16R8, 16R6, 16R4 ■ Extensive third-party software and programmer support through FusionPLD partners ■ Programmable replacement for high-speed TTL logic ■ 20-Pin DIP and PLCC packages save space ■ Register preload for testability ■ 28-Pin PLCC-4 package provides ultra-clean high-speed signals GENERAL DESCRIPTION The PAL16R8 Family (PAL16L8, PAL16R8, PAL16R6, PAL16R4) includes the PAL16R8-5/4 Series which provides the highest speed in the 20-pin TTL PAL device family, making the series ideal for high-performance applications. The PAL16R8 Family is provided with standard 20-pin DIP and PLCC pinouts and a 28-pin PLCC pinout. The 28-pin PLCC pinout contains seven extra ground pins interleaved between the outputs to reduce noise and increase speed. The devices provide user-programmable logic for replacing conventional SSI/MSI gates and flip-flops at a reduced chip count. The family allows the systems engineer to implement the design on-chip, by opening fuse links to configure AND and OR gates within the device, according to the desired logic function. Complex interconnections between gates, which previously required time-consuming layout, are lifted from the PC board and placed on silicon, where they can be easily modified during prototyping or production. The PAL device implements the familiar Boolean logic transfer function, the sum of products. The PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed to create custom product terms, while the OR array sums selected terms at the outputs. In addition, the PAL device provides the following options: — Variable input/output pin ratio — Programmable three-state outputs — Registers with feedback Product terms with all connections opened assume the logical HIGH state; product terms connected to both true and complement of any single input assume the logical LOW state. Registers consist of D-type flip-flops that are loaded on the LOW-to-HIGH transition of the clock. Unused input pins should be tied to VCC or GND. The entire PAL device family is supported by the FusionPLD partners. The PAL family is programmed on conventional PAL device programmers with appropriate personality and socket adapter modules. Once the PAL device is programmed and verified, an additional connection may be opened to prevent pattern readout. This feature secures proprietary circuits. PRODUCT SELECTOR GUIDE Device Dedicated Inputs Outputs Product Terms/ Output Feedback Enable PAL16L8 10 6 comb. 2 comb. 7 7 I/O – prog. prog. PAL16R8 8 8 reg. 8 reg. pin PAL16R6 8 6 reg. 2 comb. 8 7 reg. I/O pin prog. PAL16R4 8 4 reg. 4 comb. 8 7 reg. I/O pin prog. Publication# 16492 Rev. D Issue Date: February 1996 Amendment /0 2-3 AMD BLOCK DIAGRAMS PAL16L8 INPUTS 10 Programmable AND Array (32 x 64) 7 O1 7 7 7 I/O2 I/O3 I/O4 7 7 I/O5 I/O6 7 7 I/O7 O8 16492D-1 PAL16R8 OE INPUTS CLK 8 Programmable AND Array (32 x 64) 8 Q D Q O1 8 Q D Q O2 8 Q D Q O3 8 Q D Q 8 Q O4 D Q O5 8 8 Q D Q O6 Q D Q O7 8 Q D Q O8 16492D-2 2-4 PAL16R8 Family AMD BLOCK DIAGRAMS PAL16R6 CLK OE INPUTS 8 Programmable AND Array (32 x 64) 7 Q I/O1 8 8 D Q D Q Q O2 8 D Q Q O3 8 D Q Q O4 8 8 D Q Q O5 O6 7 D Q Q O7 I/O8 16492D-3 PAL16R4 CLK OE 8 Programmable AND Array (32 x 64) 7 7 8 Q I/O1 I/O2 D Q O3 8 Q D Q 8 Q O4 D Q O5 8 Q 7 7 I/O7 I/O8 D Q O6 16492D-4 PAL16R8 Family 2-5 AMD CONNECTION DIAGRAMS Top View DIP I2 I1 (Note 1) VCC (Note 10) 20-Pin PLCC 3 2 1 20 19 20 VCC I1 2 19 (Note 10) I2 3 18 (Note 9) I3 4 17 (Note 8) I4 5 16 (Note 7) I3 4 18 (Note 9) I5 6 15 (Note 6) I4 5 17 (Note 8) I6 7 14 (Note 5) I5 6 16 (Note 7) I7 8 13 (Note 4) I6 7 15 (Note 6) I8 9 12 (Note 3) I7 8 14 (Note 5) 10 11 (Note 2) (Note 4) 10 11 12 13 (Note 3) 16492D-5 9 (Note 2) GND I8 1 GND (Note 1) 16492D-6 VCC 2 1 28 27 26 I2 I5 3 I3 I6 4 I4 I7 28-Pin PLCC PIN DESIGNATIONS I8 5 25 I1 GND 6 24 (Note 1) (Note 2) 7 23 VCC (Note 3) 8 22 (Note 10) GND 9 21 GND (Note 4) 10 20 (Note 9) GND 11 19 GND CLK GND I I/O O OE VCC (Note 8) GND (Note 7) GND (Note 6) GND (Note 5) Clock Ground Input Input/Output Output Output Enable Supply Voltage Note: 12 13 14 15 16 17 18 2-6 = = = = = = = Pin 1 is marked for orientation. 16492D-7 Note 16L8 16R8 16R6 16R4 1 I0 CLK CLK CLK 2 I9 OE OE OE 3 O1 O1 I/O1 I/O1 4 I/O2 O2 O2 I/O2 5 I/O3 O3 O3 O3 6 I/O4 O4 O4 O4 7 I/O5 O5 O5 O5 8 I/O6 O6 O6 O6 9 I/O7 O7 O7 I/O7 10 O8 O8 I/O8 I/O8 PAL16R8 Family AMD ORDERING INFORMATION Commercial Products AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: PAL 16 R 8 -5 P C FAMILY TYPE PAL = Programmable Array Logic OPTIONAL PROCESSING Blank = Standard Processing NUMBER OF ARRAY INPUTS OPERATING CONDITIONS C = Commercial (0°C to +75°C) OUTPUT TYPE R = Registered L = Active-Low Combinatorial PACKAGE TYPE P = 20-Pin Plastic DIP (PD 020) J = 20-Pin Plastic Leaded Chip Carrier (PL 020) 28-Pin Plastic Leaded Chip Carrier for -4 (PL 028) D = 20-Pin Ceramic DIP (CD 020) NUMBER OF OUTPUTS SPEED -4 = 4.5 ns tPD -5 = 5 ns tPD -7 = 7.5 ns tPD D = 10 ns tPD VERSION Blank = First Revision /2 = Second Revision Valid Combinations PAL16L8 PAL16R8 -5PC, -5JC, -4JC PAL16R6 Valid Combinations Valid Combinations lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. PAL16R4 PAL16L8-7 PAL16R8-7 PC, JC, DC PAL16R6-7 PAL16R4-7 PAL16L8D/2 PAL16R8D/2 PC, JC PAL16R6D/2 PAL16R4D/2 PAL16R8-4/5/7, D/2 (Com’l) 2-7 AMD ORDERING INFORMATION Commercial Products (MMI Marking Only) AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: PAL 16 R 8 B -2 C N a. FAMILY TYPE PAL = Programmable Array Logic i. OPTIONAL PROCESSING Blank = Standard Processing b. NUMBER OF ARRAY INPUTS h. c. OUTPUT TYPE R = Registered L = Active-Low Combinatorial d. NUMBER OF OUTPUTS PACKAGE TYPE N = 20-Pin Plastic DIP (PD 020) NL = 20-Pin Plastic Leaded Chip Carrier (PL 020) J = 20-Pin Ceramic DIP (CD 020) g. OPERATING CONDITIONS C = Commercial (0°C to +75°C) SPEED B = Very High Speed (15 ns–35 ns tPD) A = High Speed (25 ns–35 ns tPD) f. POWER Blank = Full Power (155 mA–180 mA ICC) -2 = Half Power (80 mA–90 mA ICC) -4 = Quarter Power (55 mA ICC) Valid Combinations PAL16L8 PAL16R8 PAL16R6 PAL16R4 2-8 B, B-2, A, B-4 CN, CNL, CJ Valid Combinations Valid Combinations lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Note: Marked with MMI logo. PAL16R8/B/B-2/A/B-4 (Com’l) AMD FUNCTIONAL DESCRIPTION Registers with Feedback Standard 20-Pin PAL Family The standard bipolar 20-pin PAL family devices have common electrical characteristics and programming procedures. Four different devices are available, including both registered and combinatorial devices. All parts are produced with a fuse link at each input to the AND gate array, and connections may be selectively removed by applying appropriate voltages to the circuit. Utilizing an easily-implemented programming algorithm, these products can be rapidly programmed to any customized pattern. Extra test words are preprogrammed during manufacturing to ensure extremely high field programming yields, and provide extra test paths to achieve excellent parametric correlation. Registered outputs are provided for data storage and synchronization. Registers are composed of D-type flip-flops that are loaded on the LOW-to-HIGH transition of the clock input. Register Preload The register on the AMD marked 16R8, 16R6, and 16R4 devices can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. Pinouts Power-Up Reset The PAL16R8 Family is available in the standard 20-pin DIP and PLCC pinouts and the PAL16R8-4 Series is available in the new 28-pin PLCC pinout. The 28-pin PLCC pinout gives the designer the cleanest possible signal with only 4.5 ns delay. All flip-flops power-up to a logic LOW for predictable system initialization. Outputs of the PAL16R8 Family will be HIGH due to the active-low outputs. The VCC rise must be monotonic and the reset delay time is 1000 ns maximum. The PAL16R8-4 pinout has been designed to minimize the noise that can be generated by high-speed signals. Because of its inherently shorter leads, the PLCC package is the best package for use in high-speed designs. The short leads and multiple ground signals reduce the effective lead inductance, minimizing ground bounce. Placing the ground pins between the outputs optimizes the ground bounce protection, and also isolates the outputs from each other, eliminating cross-talk. This pinout can reduce the effective propagation delay by as much as 20% from a standard DIP pinout. Design files for PAL16R8-4 Series devices are written as if the device had a standard 20-pin DIP pinout for most design software packages. Security Fuse Variable Input/Output Pin Ratio The registered devices have eight dedicated input lines, and each combinatorial output is an I/O pin. The PAL16L8 has ten dedicated input lines and six of the eight combinatorial outputs are I/O pins. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Unused input pins should be tied to VCC or GND. Programmable Three-State Outputs Each output has a three-state output buffer with threestate control. On combinatorial outputs, a product term controls the buffer, allowing enable and disable to be a function of any product of device inputs or output feedback. The combinatorial output provides a bidirectional I/O pin and may be configured as a dedicated input if the output buffer is always disabled. On registered outputs, an input pin controls the enabling of the three-state outputs. After programming and verification, a PAL16R8 Family design can be secured by programming the security fuse. Once programmed, this fuse defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. When the security fuse is programmed, the array will read as if every fuse is programmed. Quality and Testability The PAL16R8 Family offers a very high level of built-in quality. Extra programmable fuses provide a means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to provide the highest programming yields and post-programming functional yields in the industry. Technology The PAL16R8-5, -7 and D/2 are fabricated with AMD’s oxide isolated bipolar process. The array connections are formed with highly reliable PtSi fuses. The PAL16R8B, B-2, A and B-4 series are fabricated with AMD’s advanced trench-isolated bipolar process. The array connections are formed with proven TiW fuses for reliable operation. These processes reduce parasitic capacitances and minimum geometries to provide higher performance. PAL16R8 Family 2-9 AMD LOGIC DIAGRAM DIP and 20-Pin PLCC (28-Pin PLCC) Pinouts 16L8-5 16L8 (-4)(-4) I0 1 (24) 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 20 VCC (23) 0 19 O8 (22) 7 I1 2 (25) GND 8 (21) 18 I/O7 (20) 15 I2 3 (26) GND 16 (19) 17 I/O6 (18) 23 I3 4 (27) GND 24 (17) 16 I/O5 (16) 31 I4 5 (28) GND 32 (15) 15 I/O4 (14) VCC (1) I5 6 (2) 39 GND 40 (13) 14 I/O3 (12) 47 I6 7 (3) GND 48 (11) 13 I/O2 (10) 55 I7 8 (4) GND 56 (9) 12 O1 (8) 63 11 I9 (7) I8 9 (5) 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 GND 10 (6) 16492D-8 2-10 PAL16R8 Family AMD LOGIC DIAGRAM DIP and 20-Pin PLCC (28-Pin PLCC) Pinouts 16R8-5 16R8 (-4)(-4) CLK 1 (24) 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 20 VCC (23) 31 0 V D Q 7 I1 2 (25) Q GND (21) 8 V D Q 15 I2 3 (26) Q GND 16 V 23 Q GND V 31 Q GND 32 D Q (1) 39 I5 6 (2) Q GND V 47 Q 14 O 3 (12) GND (11) 48 V D Q 55 I7 8 (4) 15 O 4 (14) (13) 40 D Q I6 7 (3) 16 O5 (16) (15) V VCC 17 O 6 (18) (17) 24 D Q I4 5 (28) 18 O 7 (20) (19) D Q I3 4 (27) 19 O 8 (22) Q 13 O 2 (10) GND (9) 56 V D Q 63 I8 9 (5) Q 12 O1 (8) 11 OE (7) 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 GND 10 (6) 16492D-9 PAL16R8 Family 2-11 AMD LOGIC DIAGRAM DIP and 20-Pin PLCC (28-Pin PLCC) Pinouts 16R6-5 16R6 (-4)(-4) CLK 1 (24) 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 20 VCC (23) 31 0 19 I/O8 (22) 7 I1 2 (25) GND (21) 8 V D Q 15 I2 3 (26) Q GND (19) 16 V D Q 23 I3 4 (27) Q GND V 31 Q GND D Q V (1) 39 Q GND V 47 Q 14 O 3 (12) GND (11) 48 V D Q 55 I7 8 (4) 15 O 4 (14) (13) 40 D Q I6 7 (3) 16 O5 (16) (15) 32 VCC I5 6 (2) 17 O 6 (18) (17) 24 D Q I4 5 (28) 18 O 7 (20) Q 13 O 2 (10) GND 56 (9) 12 I/O1 (8) 63 I8 9 (5) 11 OE (7) 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 GND 10 (6) 16492D-10 2-12 PAL16R8 Family AMD LOGIC DIAGRAM DIP and 20-Pin PLCC (28-Pin PLCC) Pinouts 16R4-5 16R4 (-4)(-4) CLK 1 (24) 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 20 VCC (23) 31 0 19 I/O8 (22) 7 I1 2 (25) GND 8 (21) 18 I/O7 (20) 15 I2 3 (26) GND (19) 16 V D Q Q 17 O6 (18) 23 GND (17) 24 D Q 16 O5 V I3 4 (27) (16) Q 31 I4 5 (28) D Q (1) V VCC GND (15) 32 39 I5 6 (2) Q 15 O4 (14) GND (13) 40 V D Q Q 14 O3 (12) 47 I6 7 (3) GND (11) 48 13 I/O2 (10) 55 I7 8 (4) GND (9) 56 12 I/O1 (8) 63 I8 9 (5) 11 OE (7) 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 GND 10 (6) 16492D-11 PAL16R8 Family 2-13 AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Ambient Temperature with Power Applied . . . . . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Storage Temperature . . . . . . . . . . –55°C to +125°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to + 7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . –1.2 V to VCC + 0.5 V DC Input Current . . . . . . . . . . . . . –30 mA to + 5 mA Operating ranges define those limits between which the functionality of the device is guaranteed. DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . 2001 V Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = –3.2 mA VIN = VIH or VIL VCC = Min VOL Output LOW Voltage IOL = 24 mA VIN = VIH or VIL VCC = Min VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VI Input Clamp Voltage IIN = –18 mA, VCC = Min IIH Input HIGH Current IIL II Max 2.4 Unit V 0.5 2.0 V V 0.8 V –1.2 V VIN = 2.7 V, VCC = Max (Note 2) 25 µA Input LOW Current VIN = 0.4 V, VCC = Max (Note 2) –250 µA Maximum Input Current VIN = 5.5 V, VCC = Max 1 mA IOZH Off-State Output Leakage Current HIGH VOUT = 2.7 V, VCC = Max VIN = VIH or VIL (Note 2) 100 µA IOZL Off-State Output Leakage Current LOW VOUT = 0.4 V, VCC = Max VIN = VIH or VIL (Note 2) –100 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –130 mA ICC Supply Current VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max 210 mA –30 Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-14 PAL16R8-4/5 (Com’l) AMD CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Input Capacitance CLK, OE I1–I8 Output Capacitance Test Conditions Typ VIN = 2.0 V VCC = 5.0 V VOUT = 2.0 V TA = 25°C f = 1 MHz 8 5 Unit pF 8 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description tPD Input or Feedback to Combinatorial Output tS Setup Time from Input or Feedback to Clock tH tCO tSKEWR fMAX -4 Max Min (Note 3) Max Unit 1 5 1 4.5 ns 4.5 4.5 ns Hold Time 0 0 ns Clock to Output 1 Skew Between Registered Outputs (Note 4) Clock Width Maximum Frequency (Note 5) 4.0 1 1 16R8, 16R6, 16R4 LOW tWL tWH 16L8, 16R8, 16R4 -5 Min (Note 3) HIGH 3.5 ns 0.5 ns 4 4 ns 4 4 ns External Feedback 1/(tS + tCO) 117 125 MHz Internal Feedback (fCNT) 1/(tS + tCF) (Note 6) 125 125 MHz No Feedback 1/(tWH + tWL) 125 125 MHz tPZX OE to Output Enable 1 6.5 1 6.5 ns tPXZ OE to Output Disable 1 5 1 5 ns tEA Input to Output Enable Using Product Term Control 2 6.5 2 6.5 ns tER Input to Output Disable Using Product Term Control 2 5 2 5 ns 16L8, 16R6, 16R4 Notes: 2. See Switching Test Circuit for test conditions. 3. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements may alter these values; therefore, minimum values are recommended for simulation purposes only. 4. Skew testing takes into account pattern and switching direction differences between outputs. 5. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where the frequency may be affected. 6. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) – tS. PAL16R8-4/5 (Com’l) 2-15 AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to + 7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . . . . . –1.2 V to + 7.0 V DC Input Current . . . . . . . . . . . . . . –30 mA to + 5 mA Operating ranges define those limits between which the functionality of the device is guaranteed. DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = –3.2 mA VIN = VIH or VIL VCC = Min VOL Output LOW Voltage IOL = 24 mA VIN = VIH or VIL VCC = Min VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VI Input Clamp Voltage IIN = –18 mA, VCC = Min IIH Input HIGH Current IIL II Max 2.4 Unit V 0.5 2.0 V V 0.8 V –1.2 V VIN = 2.7 V, VCC = Max (Note 2) 25 µA Input LOW Current VIN = 0.4 V, VCC = Max (Note 2) –250 µA Maximum Input Current VIN = 5.5 V, VCC = Max 1 mA IOZH Off-State Output Leakage Current HIGH VOUT = 2.7 V, VCC = Max VIN = VIH or VIL (Note 2) 100 µA IOZL Off-State Output Leakage Current LOW VOUT = 0.4 V, VCC = Max VIN = VIH or VIL (Note 2) –100 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –130 mA ICC Supply Current VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max 180 mA –30 Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-16 PAL16R8-7 (Com’l) AMD CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Input Capacitance VIN = 2.0 V Output Capacitance VOUT = 2.0 V Typ 5 VCC = 5.0 V TA = 25°C f = 1 MHz Unit pF 8 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol tPD Parameter Description Input or Feedback to Combinatorial Output 1 Output Switching 16L8, 16R6, 16R4 Min (Note 3) 3 3 Max 7.5 7 Unit ns tS Setup Time from Input or Feedback to Clock 7 ns tH Hold Time 0 ns tCO Clock to Output 1 tSKEW Skew Between Registered Outputs (Note 4) 16R8, 16R6, tWL LOW 16R4 Clock Width tWH fMAX HIGH Maximum Frequency (Note 5) 6.5 1 ns ns 5 ns 5 ns External Feedback 1/(tS + tCO) 74 MHz Internal Feedback (fCNT) 1/(tS + tCF) (Note 6) 100 MHz No Feedback 1/(tWH + tWL) 100 MHz tPZX OE to Output Enable 1 8 ns tPXZ OE to Output Disable 1 8 ns tEA Input to Output Enable Using Product Term Control 16L8, 16R6, 3 10 ns tER Input to Output Disable Using Product Term Control 16R4 3 10 ns Notes: 2. See Switching Test Circuit for test conditions. 3. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements may alter these values; therefore, minimum values are recommended for simulation purposes only. 4. Skew is measured with all outputs switching in the same direction. 5. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where the frequency may be affected. 6. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) – tS. PAL16R8-7 (Com’l) 2-17 AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to + 7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . . . . . –1.5 V to + 5.5 V DC Output or I/O Pin Voltage . . . . . –0.5 V to + 5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = –3.2 mA VIN = VIH or VIL VCC = Min VOL Output LOW Voltage IOL = 24 mA VIN = VIH or VIL VCC = Min VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VI Input Clamp Voltage IIN = –18 mA, VCC = Min IIH Input HIGH Current IIL II Max 2.4 Unit V 0.5 2.0 V V 0.8 V –1.5 V VIN = 2.4 V, VCC = Max (Note 2) 25 µA Input LOW Current VIN = 0.4 V, VCC = Max (Note 2) –250 µA Maximum Input Current VIN = 5.5 V, VCC = Max 100 µA IOZH Off-State Output Leakage Current HIGH VOUT = 2.4 V, VCC = Max VIN = VIH or VIL (Note 2) 100 µA IOZL Off-State Output Leakage Current LOW VOUT = 0.4 V, VCC = Max VIN = VIH or VIL (Note 2) –100 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –130 mA ICC Supply Current VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max 180 mA –30 Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-18 PAL16R8D/2 (Com’l) AMD CAPACITANCE (Note 1) Parameter Symbol CIN Parameter Description Test Conditions Input Capacitance VIN = 2.0 V Typ VCC = 5.0 V 5 pF TA = 25°C COUT Output Capacitance VOUT = 2.0 V Unit f = 1 MHz 8 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description tPD Input or Feedback to Combinatorial Output Min (Note 3) Max Unit 3 10 ns 16L8, 16R6, 16R4 tS Setup Time from Input or Feedback to Clock 10 ns tH Hold Time 0 ns tCO Clock to Output 3 tWL Clock Width tWH fMAX LOW HIGH Maximum Frequency (Note 4) External Feedback 1/(tS + tCO) Internal Feedback (fCNT) 1/(tS + tCF) (Note 5) No Feedback 1/(tWH + tWL) 7 ns 8 ns 16R8, 16R6, 8 ns 16R4 58.8 MHz 60 MHz 62.5 MHz tPZX OE to Output Enable 2 10 ns tPXZ OE to Output Disable 2 10 ns tEA Input to Output Enable Using Product Term Control 16L8, 16R6, 3 10 ns tER Input to Output Disable Using Product Term Control 16R4 3 10 ns Notes: 2. See Switching Test Circuit for test conditions. 3. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements may alter these values; therefore, minimum values are recommended for simulation purposes only. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where the frequency may be affected. 5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) – tS. PAL16R8D/2 (Com’l) 2-19 AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . –1.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Max VOH Output HIGH Voltage IOH = –3.2 mA VIN = VIH or VIL VCC = Min VOL Output LOW Voltage IOL = 24 mA VIN = VIH or VIL VCC = Min VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VI Input Clamp Voltage IIN = –18 mA, VCC = Min IIH Input HIGH Current VIN = 2.4 V, VCC = Max (Note 2) 25 µA IIL Input LOW Current VIN = 0.4 V, VCC = Max (Note 2) –250 µA II Maximum Input Current VIN = 5.5 V, VCC = Max 100 µA IOZH Off-State Output Leakage Current HIGH VOUT = 2.4 V, VCC = Max VIN = VIH or VIL (Note 2) 100 µA IOZL Off-State Output Leakage Current LOW VOUT = 0.4 V, VCC = Max VIN = VIH or VIL (Note 2) –100 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –130 mA ICC Supply Current VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max 180 mA 2.4 V 0.5 2.0 –30 V V 0.8 –1.2 Unit V V Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-20 PAL16R8B (Com’l) AMD CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Input Capacitance VIN = 2.0 V Output Capacitance VOUT = 2.0 V Typ VCC = 5.0 V TA = 25°C f = 1 MHz Unit 8 9 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min Unit 15 ns tPD Input or Feedback to Combinatorial Output tS Setup Time from Input or Feedback to Clock 15 ns tH Hold Time 0 ns tCO Clock to Output or Feedback tWL Clock Width tWH fMAX 16L8, 16R6, 16R4 Max 12 LOW 16R8, 16R6, 16R4 HIGH Maximum Frequency (Note 3) ns 10 ns 10 ns External Feedback 1/(tS + tCO) 37 MHz No Feedback 1/(tWH + tWL) 50 MHz tPZX OE to Output Enable 15 ns tPXZ OE to Output Disable 15 ns tEA Input to Output Enable Using Product Term Control 15 ns tER Input to Output Disable Using Product Term Control 15 ns 16R8, 16R6, 16R4 Notes: 2. See Switching Test Circuit for test conditions. 3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. PAL16R8B (Com’l) 2-21 AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . –1.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = –3.2 mA VIN = VIH or VIL VCC = Min VOL Output LOW Voltage IOL = 24 mA VIN = VIH or VIL VCC = Min VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) Max 2.4 Unit V 0.5 2.0 V V 0.8 V VI Input Clamp Voltage IIN = –18 mA, VCC = Min –1.2 V IIH Input HIGH Current VIN = 2.7 V, VCC = Max (Note 2) 25 µA IIL Input LOW Current VIN = 0.4 V, VCC = Max (Note 2) –100 µA II Maximum Input Current VIN = 5.5 V, VCC = Max 100 µA IOZH Off-State Output Leakage Current HIGH VOUT = 2.7 V, VCC = Max VIN = VIH or VIL (Note 2) 100 µA IOZL Off-State Output Leakage Current LOW VOUT = 0.4 V, VCC = Max VIN = VIH or VIL (Note 2) –100 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –130 mA ICC Supply Current VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max 90 mA –30 Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-22 PAL16R8B-2 (Com’l) AMD CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Typ Input Capacitance VIN = 2.0 V VCC = 5.0 V 7 Output Capacitance VOUT = 2.0 V TA = 25°C f = 1 MHz 7 Unit pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min Unit 25 ns tPD Input or Feedback to Combinatorial Output tS Setup Time from Input or Feedback to Clock 25 ns tH Hold Time 0 ns tCO Clock to Output tWL Clock Width 15 LOW 15 16R8, 16R6, 16R4 HIGH tWH fMAX 16L8, 16R6, 16R4 Max Maximum Frequency (Note 4) ns ns 15 ns External Feedback 1/(tS + tCO) 25 MHz Internal Feedback (fCNT) 1/(tS + tCF) (Note 5) 28.5 MHz No Feedback 1/(tWH + tWL) 33 MHz tPZX OE to Output Enable 20 ns tPXZ OE to Output Disable 20 ns tEA Input to Output Enable Using Product Term Control 25 ns tER Input to Output Disable Using Product Term Control 25 ns 16R8, 16R6, 16R4 Notes: 2. See Switching Test Circuit for test conditions. 3. Calculated from measured fMAX internal. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) – tS. PAL16R8B-2 (Com’l) 2-23 AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to + 7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . –1.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = –3.2 mA VIN = VIH or VIL VCC = Min VOL Output LOW Voltage IOL = 24 mA VIN = VIH or VIL VCC = Min VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VI Input Clamp Voltage IIN = –18 mA, VCC = Min IIH Input HIGH Current IIL II Max 2.4 Unit V 0.5 2.0 V V 0.8 V –1.2 V VIN = 2.7 V, VCC = Max (Note 2) 25 µA Input LOW Current VIN = 0.4 V, VCC = Max (Note 2) –250 µA Maximum Input Current VIN = 5.5 V, VCC = Max 100 µA IOZH Off-State Output Leakage Current HIGH VOUT = 2.7 V, VCC = Max VIN = VIH or VIL (Note 2) 100 µA IOZL Off-State Output Leakage Current LOW VOUT = 0.4 V, VCC = Max VIN = VIH or VIL (Note 2) –100 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –130 mA ICC Supply Current 155 180 mA 16L8 16R8/6/4 VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max –30 Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VCC = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-24 PAL16R8A (Com’l) AMD CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Input Capacitance VIN = 2.0 V VCC = 5.0 V VOUT = 2.0 V TA = 25°C f = 1 MHz Output Capacitance Typ Unit 7 pF 7 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min tPD Input or Feedback to Combinatorial Output tS Setup Time from Input or Feedback to Clock 25 0 tH Hold Time tCO Clock to Output tWL Clock Width Maximum Frequency (Note 4) Max Unit 25 ns ns ns 15 LOW HIGH tWH fMAX 16L8, 16R6, 16R4 External Feedback 1/(tS + tCO) Internal Feedback (fCNT) 1/(tS + tCF) (Note 5) No Feedback 1/(tWH + tWL) 16R8, 16R6, 16R4 ns 15 ns 15 ns 25 MHz 28.5 MHz 33 MHz tPZX OE to Output Enable 20 ns tPXZ OE to Output Disable 20 ns tEA Input to Output Enable Using Product Term Control 25 ns tER Input to Output Disable Using Product Term Control 25 ns 16R8, 16R6, 16R4 Notes: 2. See Switching Test Circuit for test conditions. 3. Calculated from measured fMAX internal. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) – tS. PAL16R8A (Com’l) 2-25 AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . . . . . –1.5 V to +5.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . 5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = –1 mA VIN = VIH or VIL VCC = Min VOL Output LOW Voltage IOL = 8 mA VIN = VIH or VIL VCC = Min VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VI Input Clamp Voltage IIN = –18 mA, VCC = Min IIH Input HIGH Current IIL II Max 2.4 Unit V 0.5 2.0 V V 0.8 V –1.5 V VIN = 2.4 V, VCC = Max (Note 2) 25 µA Input LOW Current VIN = 0.4 V, VCC = Max (Note 2) –250 µA Maximum Input Current VIN = 5.5 V, VCC = Max 100 µA IOZH Off-State Output Leakage Current HIGH VOUT = 2.4 V, VCC = Max VIN = VIH or VIL (Note 2) 100 µA IOZL Off-State Output Leakage Current LOW VOUT = 0.4 V, VCC = Max VIN = VIH or VIL (Note 2) –100 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –250 mA ICC Supply Current VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max 55 mA –30 Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V as been chosen to avoid test problems caused by tester ground degradation. 2-26 PAL16R8B-4 (Com’l) AMD SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) Parameter Symbol Parameter Description Min Max Unit 35 ns tPD Input or Feedback to Combinatorial Output tS Setup Time from Input or Feedback to Clock 35 ns tH Hold Time 0 ns tCO Clock to Output or Feedback tWL Clock Width 16R8, 16R6, LOW 16R4 HIGH tWH fMAX 16L8, 16R6, 16R4 Maximum Frequency (Note 2) 25 ns 25 ns 25 ns External Feedback 1/(tS + tCO) 16 MHz No Feedback 1/(tWH + tWL) 20 MHz tPZX OE to Output Enable 25 ns tPXZ OE to Output Disable 25 ns tEA Input to Output Enable Using Product Term Control 16L8, 16R6, 35 ns tER Input to Output Disable Using Product Term Control 16R4 35 ns Notes: 1. See Switching Test Circuit for test conditions. 2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. PAL16R8B-4 (Com’l) 2-27 AMD SWITCHING WAVEFORMS Input or Feedback VT tS Input or Feedback VT tH VT Clock tPD Combinatorial Output VT 16492D-12 tCO Registered Output VT 16492D-13 Combinatorial Output Registered Output Clock Registered Output 1 VT tWH tSKEWR VT Clock Registered Output 2 VT tWL 16492D-14 16492D-15 Registered Output Skew Clock Width VT Input VT OE tER Output tEA VOH – 0.5V VOL + 0.5V tPXZ VT Output 16492D-16 VT VOL + 0.5V 16492D-17 OE to Output Disable/Enable Input to Output Disable/Enable Notes: 1. VT = 1.5 V 2. Input pulse amplitude 0 V to 3.0 V 3. Input rise and fall times 2 ns–3 ns typical. 2-28 tPZX VOH – 0.5V PAL16R8 Family AMD KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010-PAL SWITCHING TEST CIRCUIT 5V S1 R1 Output Test Point R2 CL 16492D-18 Commercial Specification S1 CL tPD, tCO Closed tPZX, tEA Z → H: Open Z → L: Closed 50 pF H → Z: Open 5 pF tPXZ, tER L → Z: Closed R1 R2 Measured Output Value All but B-4: All but B-4: 1.5 V 200 Ω 390 Ω 1.5 V B-4: B-4: H → Z: VOH – 0.5 V 800 Ω 1.56 kΩ L → Z: VOL + 0.5 V PAL16R8 Family 2-29 AMD MEASURED SWITCHING CHARACTERISTICS for the PAL16R8-5 VCC = 4.75 V, TA = 75°C (Note 1) 5.0 –5 4.5 tPD, ns 4.0 3.5 3.0 1 2 3 4 5 6 Number of Outputs Switching 7 8 16492D-19 tPD vs. Number of Outputs Switching 10 8 tPD, ns 6 –5 4 2 0 50 100 150 200 250 CL, pF tPD vs. Load Capacitance VCC = 5.25 V, TA = 25°C 16492D-20 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where tPD may be affected. 2-30 PAL16R8-5 AMD CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS for the PAL16R8-4/5 VCC = 5.0 V, TA = 25°C IOL, mA 15 10 5 VOL, V –0.6 –0.4 –0.2 –5 0.2 0.4 0.6 –10 –15 16492D-21 Output, LOW 20 IOH, mA VOH, V –3 –2 –1 1 –20 2 3 –40 –60 –80 –90 16492D-22 Output, HIGH II, µA 20 1 2 3 VI, V –3 –2 –1 –50 –100 –150 –200 16492D-23 Input PAL16R8-5 2-31 AMD MEASURED SWITCHING CHARACTERISTICS for the PAL16R8-7 VCC = 4.75 V, TA = 75°C (Note 1) 7.5 7 tPD, ns 6.5 6 1 2 3 4 5 6 7 8 NUMBER OF OUTPUTS SWITCHING 16492D-24 tPD vs. Number of Outputs Switching 8 7 tPD, ns 6 5 10 30 50 70 90 110 CL, pF 16492D-25 tPD vs. Load Capacitance Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where tPD may be affected. 2-32 PAL16R8-7 AMD CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS for the PAL16R8-7 VCC = 5.0 V, TA = 25°C IOL, mA 15 10 5 VOL, V –0.6 –0.4 –0.2 –5 0.2 0.4 0.6 –10 –15 16492D-26 Output, LOW IOH, mA 20 VOH, V –3 –2 –1 1 –20 2 3 –40 –60 –80 16492D-27 Output, HIGH II, µA 20 1 2 3 VI, V –3 –2 –1 –20 –40 –60 –80 16492D-28 Input PAL16R8-7 2-33 AMD INPUT/OUTPUT EQUIVALENT SCHEMATICS VCC Input Program/Verify Circuitry 16492D-29 Typical Input VCC 40 Ω NOM Output Input, I/O Pins Program/Verify/ Test Circuitry Preload Circuitry 16492D-30 Typical Output 2-34 PAL16R8-5 AMD POWER-UP RESET The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. The output state will be HIGH due to the inverting output buffer. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways Parameter Symbol VCC can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are: ■ The VCC rise must be monotonic. ■ Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Description Max Unit tPR Power-Up Reset Time 1000 ns tS Input or Feedback Setup Time tWL Clock Width LOW See Switching Characteristics VCC 4V Power tPR Registered Active-Low Output tS Clock tWL 16492D-31 Power-Up Reset Waveform PAL16R8 Family 2-35