NTMD3P03R2 Power MOSFET −3.05 Amps, −30 Volts Dual P−Channel SO−8 Features • • • • • • • High Efficiency Components in a Dual SO−8 Package High Density Power MOSFET with Low RDS(on) Miniature SO−8 Surface Mount Package − Saves Board Space Diode Exhibits High Speed with Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for the SO−8 Package is Provided http://onsemi.com VDSS RDS(ON) TYP ID MAX −30 V 85 mΩ @ −10 V −3.05 A Applications • DC−DC Converters • Low Voltage Motor Control • Power Management in Portable and Battery−Powered Products, i.e.: P−Channel D Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating G Symbol Value Unit Drain−to−Source Voltage VDSS −30 V Gate−to−Source Voltage − Continuous VGS ±20 V Thermal Resistance − Junction−to−Ambient (Note 1) Total Power Dissipation @ TA = 25°C Continuous Drain Current @ 25°C Continuous Drain Current @ 70°C Pulsed Drain Current (Note 4) RθJA PD ID ID IDM 171 0.73 −2.34 −1.87 −8.0 °C/W W A A A Thermal Resistance − Junction−to−Ambient (Note 2) Total Power Dissipation @ TA = 25°C Continuous Drain Current @ 25°C Continuous Drain Current @ 70°C Pulsed Drain Current (Note 4) RθJA PD ID ID IDM 100 1.25 −3.05 −2.44 −12 °C/W W A A A Thermal Resistance − Junction−to−Ambient (Note 3) Total Power Dissipation @ TA = 25°C Continuous Drain Current @ 25°C Continuous Drain Current @ 70°C Pulsed Drain Current (Note 4) RθJA PD ID ID IDM 62.5 2.0 −3.86 −3.1 −15 °C/W W A A A TJ, Tstg −55 to +150 °C 140 mJ Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = −30 Vdc, VGS = −4.5 Vdc, Peak IL = −7.5 Apk, L = 5 mH, RG = 25 Ω) EAS Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL May, 2004 − Rev. 1 MARKING DIAGRAM 8 1 ED3P03 LYWW SO−8 CASE 751 STYLE 11 ED3P03 L Y WW = Device Code = Assembly Location = Year = Work Week PIN ASSIGNMENT Source−1 1 8 Drain−1 Gate−1 2 7 Drain−1 Source−2 3 6 Drain−2 Gate−2 4 5 Drain−2 Top View °C 260 1. Minimum FR−4 or G−10 PCB, t = Steady State. 2. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided), t = steady state. 3. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided), t ≤ 10 seconds. 4. Pulse Test: Pulse Width = 300 s, Duty Cycle = 2%. Semiconductor Components Industries, LLC, 2004 S 1 ORDERING INFORMATION Device NTMD3P03R2 Package Shipping† SO−8 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NTMD3P03R2/D NTMD3P03R2 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Note 5) Symbol Characteristic Min Typ Max Unit −30 − − −30 − − − − − − − − −1.0 −20 −2.0 − − −100 − − 100 −1.0 − −1.7 3.6 −2.5 − − − 0.063 0.090 0.085 0.125 gFS − 5.0 − Mhos Ciss − 520 750 pF Coss − 170 325 Crss − 70 135 td(on) − 12 22 OFF CHARACTERISTICS V(BR)DSS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = −250 µAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = −24 Vdc, VGS = 0 Vdc, TJ = 25°C) (VDS = −24 Vdc, VGS = 0 Vdc, TJ = 125°C) (VDS = −30 Vdc, VGS = 0 Vdc, TJ = 25°C) IDSS Gate−Body Leakage Current (VGS = −20 Vdc, VDS = 0 Vdc) IGSS Gate−Body Leakage Current (VGS = +20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C µAdc nAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = −250 µAdc) Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−State Resistance (VGS = −10 Vdc, ID = −3.05 Adc) (VGS = −4.5 Vdc, ID = −1.5 Adc) RDS(on) Forward Transconductance (VDS = −15 Vdc, ID = −3.05 Adc) Vdc Ω DYNAMIC CHARACTERISTICS Input Capacitance (VDS = −24 24 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 6 and 7) Turn−On Delay Time (VDD = −24 Vdc, ID = −3.05 Adc, VGS = −10 10 Vdc Vdc, RG = 6.0 Ω) Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time (VDD = −24 Vdc, ID = −1.5 Adc, VGS = −4.5 4 5 Vdc Vdc, RG = 6.0 Ω) Rise Time Turn−Off Delay Time Fall Time Total Gate Charge (VDS = −24 Vdc, VGS = −10 Vdc, ID = −3.05 3 05 Adc) Ad ) Gate−Source Charge Gate−Drain Charge ns tr − 16 30 td(off) − 45 80 tf − 45 80 td(on) − 16 − tr − 42 − td(off) − 32 − tf − 35 − Qtot − 16 25 Qgs − 2.0 − Qgd − 4.5 − VSD − − −0.96 −0.78 −1.25 − Vdc trr − 34 − ns ta − 18 − tb − 16 − QRR − 0.03 − ns nC BODY−DRAIN DIODE RATINGS (Note 6) Diode Forward On−Voltage (IS = −3.05 Adc, VGS = 0 V) (IS = −3.05 Adc, VGS = 0 V, TJ = 125°C) Reverse Recovery Time (IS = −3.05 3 05 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/µs) Reverse Recovery Stored Charge 5. Handling precautions to protect against electrostatic discharge is mandatory. 6. Indicates Pulse Test: Pulse Width = 300 µs max, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 µC NTMD3P03R2 TYPICAL ELECTRICAL CHARACTERISTICS −ID, DRAIN CURRENT (AMPS) VGS = −4 V VGS = −4.6 V VGS = −6 V 4 VGS = −4.8 V TJ = 25°C VGS = −3.6 V VGS = −2.8 V VGS = −3.2 V VGS = −5 V 3 2 VGS = −2.6 V VGS = −3 V 1 0 0.25 0.5 0.75 1 1.25 1.5 1.75 TJ = 25°C 2 TJ = −55°C 1 1 2 3 4 5 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.6 0.5 0.4 0.3 0.2 0.1 5 4 6 7 8 0.7 ID = −1.5 A TJ = 25°C 0.6 0.5 0.4 0.3 0.2 0.1 0 2 4 3 5 6 7 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Gate−to−Source Voltage 0.25 TJ = 25°C 0.2 VGS = −4.5 V 0.15 VGS = −10 V 0.1 0.05 1 TJ = 100°C 3 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID = −3.05 A TJ = 25°C 3 4 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.7 0 VDS > = −10 V 5 0 2 RDS(on), DRAIN−TO−SOURCE RESISTANCE (Ω) RDS(on), DRAIN−TO−SOURCE RESISTANCE (Ω) VGS = −4.4 V VGS = −8 V 5 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (Ω) 6 VGS = −10 V 2 3 4 5 6 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) −ID, DRAIN CURRENT (AMPS) 6 1.6 1.4 ID = −3.05 A VGS = −10 V 1.2 1 0.8 0.6 −50 −25 0 25 50 75 100 125 −ID, DRAIN CURRENT (AMPS) TJ, JUNCTION TEMPERATURE (°C) Figure 5. On−Resistance vs. Drain Current and Gate Voltage Figure 6. On Resistance Variation with Temperature http://onsemi.com 3 150 NTMD3P03R2 10000 VDS = 0 V 1200 C, CAPACITANCE (pF) IDSS, LEAKAGE (nA) VGS = 0 V TJ = 150°C 1000 TJ = 125°C 100 VGS = 0 V Ciss 1000 800 Ciss Crss 600 400 Coss 200 Crss TJ = 25°C 10 14 18 22 26 0 10 30 0 5 −VDS 10 15 20 25 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Drain−to−Source Leakage Current vs. Voltage Figure 8. Capacitance Variation 30 30 1000 12 QT 10 VDS = −24 V ID = −3.05 A VGS = −10 V 25 VDS 20 8 VGS 15 6 Q1 4 tf tr td(on) 5 ID = −3.05 A TJ = 25°C 0 2 4 6 8 10 12 0 16 14 1 10 1 100 Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (Ω) Figure 9. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge Figure 10. Resistive Switching Time Variation vs. Gate Resistance 3 100 tr tf 1 10 IS, SOURCE CURRENT (AMPS) VDS = −24 V ID = −1.5 A VGS = −4.5 V 10 td(off) 10 10 Q2 2 0 100 1000 t, TIME (ns) 5 −VGS t, TIME (ns) −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 10 6 td(off) td(on) 100 VGS = 0 V TJ = 25°C 2.5 2 1.5 1 0.5 0 0.2 0.4 0.6 0.8 1 RG, GATE RESISTANCE (Ω) −VSD, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 11. Resistive Switching Time Variation vs. Gate Resistance Figure 12. Diode Forward Voltage vs. Current http://onsemi.com 4 1.2 NTMD3P03R2 VGS = 12 V SINGLE PULSE TC = 25°C 10 1.0 ms di/dt 10 ms IS dc 1.0 trr ta 0.01 tb TIME 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1.0 1 0.25 IS tp 10 IS 100 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 13. Maximum Rated Forward Biased Safe Operating Area Figure 14. Diode Reverse Recovery Waveform 1.0 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE −ID, DRAIN CURRENT (AMPS) 100 D = 0.5 0.2 0.1 0.1 Normalized to RθJA at Steady State (1″ pad) Chip Junction 2.32 Ω 18.5 Ω 50.9 Ω 37.1 Ω 56.8 Ω 0.05 0.02 0.0014 F 0.01 0.0073 F 0.022 F 0.105 F 0.484 F 1E−02 3.68 F Ambient Single Pulse 0.01 1E−03 24.4 Ω 1E−01 1E+00 1E+01 t, TIME (s) Figure 15. FET Thermal Response http://onsemi.com 5 1E+02 1E+03 NTMD3P03R2 PACKAGE DIMENSIONS SO−8 CASE 751−07 ISSUE AB NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 0.25 (0.010) S B 1 Y M M 4 K −Y− G C N DIM A B C D G H J K M N S X 45 SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S STYLE 11: PIN 1. 2. 3. 4. 5. 6. 7. 8. SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 DRAIN 2 DRAIN 1 DRAIN 1 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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