ONSEMI NTMS4816NR2G

NTMS4816N
Power MOSFET
30 V, 11 A, N-Channel, SO-8
Features
•Low RDS(on) to Minimize Conduction Losses
•Low Capacitance to Minimize Driver Losses
•Optimized Gate Charge to Minimize Switching Losses
•This is a Pb-Free Device
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V(BR)DSS
Applications
•Disk Drives
•DC-DC Converters
•Printers
RDS(ON) MAX
ID MAX
10 mW @ 10 V
30 V
11 A
16 mW @ 4.5 V
N-Channel
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Drain-to-Source Voltage
Gate-to-Source Voltage
Symbol
Value
Unit
VDSS
30
V
VGS
±20
V
ID
9.0
A
Continuous Drain
Current RqJA (Note 1)
Steady
State
TA = 25°C
Power Dissipation RqJA
(Note 1)
Steady
State
TA = 25°C
PD
1.37
W
Continuous Drain
Current RqJA (Note 2)
Steady
State
TA = 25°C
ID
6.8
A
TA = 70°C
G
7.2
TA = 70°C
TA = 25°C
Power Dissipation RqJA
(Note 2)
D
S
MARKING DIAGRAM/
PIN ASSIGNMENT
5.4
PD
0.78
W
1
Continuous Drain
Current RqJA, t v 10 s
(Note 1)
Steady
State
ID
Power Dissipation
RqJA, t v 10 s(Note 1)
Steady
State
TA = 25°C
PD
2.04
W
Pulsed Drain Current
TA = 25°C, tp = 10 ms
IDM
33
A
TJ,
Tstg
-55 to
150
°C
IS
2.7
A
EAS
78
mJ
260
°C
TA = 25°C
TA = 70°C
Operating Junction and Storage Temperature
8.8
Source Current (Body Diode)
Single Pulse Drain-to-Source Avalanche Energy
(TJ = 25°C, VDD = 30 V, VGS = 10 V,
IL = 12.5 Apk, L = 1.0 mH, RG = 25 W)
A
11
8
Drain
Drain
Drain
Drain
Top View
4816N = Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb-Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
Device
NTMS4816NR2G
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
SO-8
CASE 751
STYLE 12
Source
Source
Source
Gate
4816N
AYWWG
G
1
Symbol
Value
Unit
Junction-to-Ambient – Steady State (Note 1)
RqJA
91.5
°C/W
Junction-to-Ambient – t v 10 s (Note 1)
RqJA
61.3
Junction-to-Foot (Drain)
RqJF
22.5
Junction-to-Ambient – Steady State (Note 2)
RqJA
159.5
Package
Shipping†
SO-8
(Pb-Free)
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surfacemounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq
[1 oz] including traces).
2. Surfacemounted on FR4 board using the minimum recommended pad size.
© Semiconductor Components Industries, LLC, 2007
December, 2007 - Rev. 0
1
Publication Order Number:
NTMS4816N/D
NTMS4816N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain-to-Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain-to-Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
26
VGS = 0 V, VDS = 24 V
mV/°C
TJ = 25°C
1.0
TJ = 100°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
Gate-to-Source Leakage Current
V
±100
mA
nA
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold Temperature
Coefficient
VGS(TH)/TJ
Drain-to-Source On Resistance
RDS(on)
Forward Transconductance
1.5
3.0
6.0
gFS
V
mV/°C
VGS = 10 V, ID = 9 A
8.2
10
mW
VGS = 4.5 V, ID = 7.2 A
12.7
16
VDS = 1.5 V, ID = 9 A
26
S
1060
pF
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
126
Total Gate Charge
QG(TOT)
9.2
Threshold Gate Charge
QG(TH)
2.4
Gate-to-Source Charge
QGS
Gate-to-Drain Charge
QGD
Total Gate Charge
QG(TOT)
VGS = 0 V, f = 1.0 MHz, VDS = 25 V
VGS = 4.5 V, VDS = 15 V, ID = 9 A
220
nC
4.4
3.8
VGS = 10 V, VDS = 15 V, ID = 9 A
18.3
nC
td(on)
8.0
ns
tr
3.8
SWITCHING CHARACTERISTICS (Note 4)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
td(off)
VGS = 10 V, VDS = 15 V,
ID = 1.0 A, RG = 6.0 W
tf
21.6
8.0
DRAIN-SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
VGS = 0 V, IS = 2.7 A
TJ = 25°C
0.75
TJ = 125°C
0.55
tRR
20
Charge Time
ta
9.0
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 2.7 A
QRR
1.0
V
ns
11
9.0
nC
PACKAGE PARASITIC VALUES
LS
TA = 25°C
0.66
nH
Drain Inductance
LD
TA = 25°C
0.20
nH
Gate Inductance
LG
TA = 25°C
1.5
nH
Gate Resistance
RG
TA = 25°C
1.5
Source Inductance
3. Pulse Test: pulse width = 300 ms, duty cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
2.3
W
NTMS4816N
TYPICAL PERFORMANCE CURVES
20
ID, DRAIN CURRENT (AMPS)
3.4 V
3.2 V
5
3.0 V
2.8 V
0
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W)
3.6 V
3.8 V
10
VDS ≥ 10 V
0
0.5
1.0
1.5
2.0
2.5
10
3.0
TJ = 25°C
1
2
TJ = -55°C
3
4
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
TJ = 25°C
ID = 9 A
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.010
2
4
6
8
10
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
0.02
0.015
VGS = 4.5 V
0.0125
0.01
0.0075
0.005
VGS = 10 V
0.0025
0
5
10
15
20
ID, DRAIN CURRENT (AMPS)
Figure 4. On-Resistance vs. Drain Current and
Gate Voltage
100000
1.6
1.5
TJ = 25°C
0.0175
Figure 3. On-Resistance vs. Gate-to-Source
Voltage
VGS = 0 V
ID = 9 A
VGS = 10 V
1.4
IDSS, LEAKAGE (nA)
RDS(on), DRAIN-TO-SOURCE
RESISTANCE (NORMALIZED)
TJ = 100°C
5
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
0.050
0.005
15
0
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (AMPS)
15
20
TJ = 25°C
10V
6V
5V
4.5 V
4.2 V
4V
1.3
1.2
1.1
1.0
0.9
10000
TJ = 150°C
1000
TJ = 100°C
0.8
0.7
0.6
-50
100
-25
0
25
50
75
100
125
150
3
6
9
12
15
18
21
24
27
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with
Temperature
Figure 6. Drain-to-Source Leakage Current
vs. Voltage
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3
30
NTMS4816N
TYPICAL PERFORMANCE CURVES
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
TJ = 25°C
Ciss
C, CAPACITANCE (pF)
1200
VGS = 0 V
900
600
Coss
300
Crss
0
0
5
10
15
20
25
DRAIN-TO-SOURCE VOLTAGE (VOLTS)
QT
9
VDS
8
7
12
6
5
8
3
4
2
ID = 9 A
TJ = 25°C
1
0
0
30
4
0
20
4.5
IS, SOURCE CURRENT (AMPS)
VDD = 15 V
ID = 1 A
VGS = 10 V
td(off)
100
t, TIME (ns)
16
8
12
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate-To-Source and
Drain-To-Source Voltage vs. Total Charge
1000
tf
tr
td(on)
10
1
10
3.5
3
2.5
2
1.5
1
0.5
0.5
0.6
0.7
0.8
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100 ms
1 ms
1
10 ms
VGS = 20 V
SINGLE PULSE
TC = 25°C
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
dc
10
100
EAS, SINGLE PULSE DRAIN-TO-SOURCE
AVALANCHE ENERGY (mJ)
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
10
0.01
0.1
VGS = 0 V
TJ = 25°C
RG, GATE RESISTANCE (OHMS)
10 ms
0.1
4
0
0.4
100
100
ID, DRAIN CURRENT (AMPS)
QGD
QGS
4
Figure 7. Capacitance Variation
1
16
VGS
VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)
20
10
1500
80
ID = 12.5 A
60
40
20
0
25
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
125
50
75
100
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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4
150
NTMS4816N
PACKAGE DIMENSIONS
SOIC-8
CASE 751-07
ISSUE AJ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751-01 THRU 751-06 ARE OBSOLETE. NEW
STANDARD IS 751-07.
-XA
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
-YG
C
N
X 45 _
DIM
A
B
C
D
G
H
J
K
M
N
S
SEATING
PLANE
-Z-
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
SOLDERING FOOTPRINT*
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
1.52
0.060
7.0
0.275
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
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NTMS4816N/D