ONSEMI NCV8509PDW18

NCV8509 Series
Sequenced Linear
Dual−Voltage Regulator
The NCV8509 Series are dual voltage regulators whose output
voltages power up in such a manner as to protect the integrity of
modern day microcontroller I/O and ESD input structures. Newer
generation microcontrollers require two power supplies. One voltage
is used for powering the core, while the other powers the I/O.
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SOIC 16 LEAD
WIDE BODY
EXPOSED PAD
PDW SUFFIX
CASE 751R
Features
• Power−Up Sequence
• Output Voltage Options:
16
1
♦
•
•
•
•
•
•
•
•
VOUT1 5 V (±2%) 115 mA, VOUT2 2.6 V (2%) 100 mA
♦ VOUT1 5 V (±2%) 115 mA, VOUT2 2.5 V (2%) 100 mA
♦ VOUT1 3.3 V (±2%) 115 mA, VOUT2 1.8 V (2%) 100 mA
Low 175 A Quiescent Current
Power Shunt
Programmable RESET Time
Dual Drive RESET Valid
Programmable SLEW Rate Control
Thermal Shutdown
16 Lead SOW Exposed Pad
NCV Prefix, for Automotive and Other Applications Requiring Site
and Change Control
Typical Applications
• Automotive Powertrain
• Telematics
MARKING DIAGRAM
16
NCV8509xx
AWLYYWW
1
xx
= Voltage Ratings as Indicated Below:
26 = 5 V/2.6 V
25 = 5 V/2.5 V
18 = 3.3 V/1.8 V
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
MRA4004T3
REX
138 Ω
VBAT
CIN2
0.1 µF
VIN2
VOUT1
VOUT2
NCV8509
SLEW
PIN CONNECTIONS
CVOUT1
10 µF
1
CVOUT2
10 µF
Microprocessor
VIN1
CIN1
10 µF
RRESET
10 k
CSLEW
33 nF
SLEW
Delay
GND
NC
NC
RESET
NC
NC
16
NC
VOUT1
NC
VIN1
VIN2
NC
VOUT2
NC
RESET
Delay
GND
CDelay
33 nF
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
Figure 1. Application Diagram
 Semiconductor Components Industries, LLC, 2004
March, 2004 − Rev. 20
1
Publication Order Number:
NCV8509/D
NCV8509 Series
MAXIMUM RATINGS*
Rating
Value
Unit
−0.3 to 50
V
VIN1 Peak Transient Voltage
50
V
VIN2 (dc)
50
V
VIN2 (Current out of pin)
10
mA
Operating Voltage
50
V
−0.3 to 10
V
VOUT1
10
V
VOUT2
10
V
ElectrosElectrostatic Discharge (Human Body Model)
(Machine Model)
4.0
400
kV
V
Package Thermal Resistance, SOW−16 E Pad:
16
57
°C/W
°C/W
240 peak (Note 2)
°C
VIN1 (dc)
Input Voltage Range (SLEW, RESET, Delay)
Junction−to−Case, RθJC
Junction−to−Ambient, RθJA
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1)
*The maximum package power dissipation must be observed.
1. 60 second maximum above 183°C.
2. −5°C/+0°C allowable conditions.
ELECTRICAL CHARACTERISTICS (6.0 V < VIN1 < 18 V, IVOUT1 = 5.0 mA, IVOUT2 = 5.0 mA, −40°C < TJ < 125°C,
CVOUT1 = CVOUT2 = 10 F; unless otherwise noted.)
Test Conditions
Characteristic
Min
Typ
Max
Unit
4.9
3.234
5.0
3.3
5.1
3.366
V
V
VOUT1
Output Voltage
5 V Option
3.3 V Option
1.0 mA < IVOUT1 < 100 mA
1.0 mA < IVOUT1 < 100 mA
Dropout Voltage (VIN1 − VOUT1)
IOUT = 100 mA
IOUT = 100 µA
−
−
400
100
600
200
mV
mV
Load Regulation
1.0 mA < IVOUT1 < 100 mA
−
10
50
mV
Line Regulation
6.0 V < VIN1 < 18 V
−
10
50
mV
Current Limit
VOUT1 = VOUT1 (typ) − 500 mV
VOUT1 = 0 V
115
−
305
105
610
300
mA
mA
VOUT2
Output Voltage
2.6 V Option
2.5 V Option
1.8 V Option
1.0 mA < IVOUT2 < 100 mA
1.0 mA < IVOUT2 < 100 mA
1.0 mA < IVOUT2 < 100 mA
2.548
2.450
1.764
2.6
2.5
1.8
2.652
2.550
1.836
V
V
V
Load Regulation
1.0 mA < IVOUT2 < 100 mA
−
5.0
50
mV
Line Regulation
6.0 V < VIN1 = VIN2 < 18 V
−
10
50
mV
Current Limit
VOUT2 = VOUT2 (typ) − 500 mV
VOUT2 = 0 V
105
−
305
105
610
300
mA
mA
−
−
75
5.0
175
10
µA
mA
150
180
210
°C
General
Quiescent Current
IOUT1 = IOUT2 = 100 µA, VIN1 = 12 V
IOUT1 = IOUT2 = 50 mA, VIN1 = 14 V
Thermal Shutdown (Note 3)
(Guaranteed by Design)
3. Both outputs will turn off.
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2
NCV8509 Series
ELECTRICAL CHARACTERISTICS (continued) (6.0 V < VIN1 < 18 V, IVOUT1 = 5.0 mA, IVOUT2 = 5.0 mA, −40°C < TJ < 125°C,
CVOUT1 = CVOUT2 = 10 F; unless otherwise noted.)
Test Conditions
Characteristic
Min
Typ
Max
Unit
4.0
6.0
8.0
µA
−
−
710
469
−
−
V/s
V/s
−
−
−
370
355
256
−
−
−
V/s
V/s
V/s
1.5
1.8
2.1
V
94.5
96.5
98.5
%
4.5
2.97
2.34
2.25
1.62
4.73
3.12
2.46
2.36
1.70
0.965 × VOUT
0.965 × VOUT
0.965 × VOUT
0.965 × VOUT
0.965 × VOUT
V
V
V
V
V
SLEW
SLEW Charging Current
SLEW = 1.0 V
VOUT1 SLEW Rate (Note 4)
5 V Option
3.3 V Option
CSLEW = 33 nF
VOUT2 SLEW Rate
2.6 V Option
2.5 V Option
1.8 V Option
CSLEW = 33 nF
SLEW Control Threshold
(See Figure 41)
RESET
RESET Threshold Increasing
(Note 5)
−
RESET Threshold Decreasing
−
5 V Option
3.3 V Option
2.6 V Option
2.5 V Option
1.8 V Option
RESET Output Low
IRESET = 1.0 mA
−
0.1
0.4
V
RESET Output Peak
Power Down (See Figure 29)
−
0.6
1.0
V
50
33
26
25
18
100
66
52
50
36
150
99
78
75
54
mV
mV
mV
mV
mV
1.125
1.5
1.875
V
4.0
6.0
8.0
µA
RESET Threshold Hysteresis
5 V Option
3.3 V Option
2.6 V Option
2.5 V Option
1.8 V Option
−
Delay
Delay Switching Threshold
−
Delay Charge Current
Delay = 1.0 V
Delay Saturation Voltage
VOUT1 Out of Regulation
−
−
0.1
V
Delay Discharge Current
Delay = 5.0 V VOUT1 out of Regulation
10
−
−
mA
COUT1 = COUT2 , IOUT1 = IOUT2
COUT1 = COUT2 , IOUT1 = IOUT2
−
−
−
−
3.2
2.8
V
V
COUT1 = COUT2 , IOUT1 = IOUT2
−
−
100
mV
Output Tracking
Delta 1 [VOUT1 − VOUT2]
5 V Option
3.3 V Option
Delta 2 [VOUT2 − VOUT1]
Power Shunt
Shunt Voltage 1 (VIN2)
VIN1 = 6.0 V, IOUT2 = 100 mA, No REX
3.3
−
4.6
V
Shunt Voltage 2 (VIN2)
VIN1 = 12 V, 1.0 mA < IOUT2 < 100 mA, No REX
3.25
4.5
5.75
V
4. Not a tested parameter.
5. RESET signal sensitive to VOUT1 and VOUT2.
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3
NCV8509 Series
PIN DESCRIPTION
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Pin No.
Symbol
Description
1
SLEW
Control for output rise time during power up. Requires capacitor to ground.
2
Delay
Timing capacitor for RESET function.
3
GND
Ground.
4, 5, 7−9, 11, 14, 16
NC
6
RESET
No connection.
Active reset (accurate to VOUT > 1.0 V).
10
VOUT2
100 mA output (±2% output voltage) for powering microprocessor core.
12
VIN2
Input voltage for VOUT2.
13
VIN1
Input voltage for VOUT1, and internal circuitry.
15
VOUT1
100 mA output (±2% output voltage) for powering microprocessor I/O.
VIN1
VREF
CIN1
SLEW
SLEW
Control
REX
VIN2
CIN2
Bandgap
& Bias
Power Shunt
CSLEW
VIN1
VBG
+
+
+
−
VREF
VOUT1
Error Amp
VREF
COUT1
Start−Up
Current
+
−
VIN2
GND
+
+
+
−
−
+
VOUT1
VIN1
VBG
RESET Comp
VOUT2
Error Amp
VREF
COUT2
Start−Up
Current
VOUT1
−
+
RESET
VREF
Thermal
Shutdown
Delay
Discharge
Latch
Delay
CDelay
Figure 2. Block Diagram
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4
NCV8509 Series
TYPICAL PERFORMANCE CHARACTERISTICS
2.65
2.64
2.63
Voltage (V)
Voltage (V)
2.62
2.61
2.60
2.59
2.58
IVOUT1 = 5 mA
IVOUT2 = 5 mA
2.57
2.56
2.55
−40 −20
0
20
40
60
80
Temperature (°C)
100
120
140
3.37
3.36
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
3.24
3.23
−40 −20
Figure 3. 2.6 V Output Voltage
IVOUT1 = 5 mA
IVOUT2 = 5 mA
0
20
40
60
80
Temperature (°C)
100
120
140
Figure 4. 3.3 V Output Voltage
2.55
1.84
2.54
1.83
2.53
1.82
Voltage (V)
Voltage (V)
2.52
2.51
2.50
2.49
2.48
0
20
40
60
80
Temperature (°C)
100
120
1.79
IVOUT1 = 5 mA
IVOUT2 = 5 mA
1.77
2.46
2.45
−40 −20
1.80
1.78
IVOUT1 = 5 mA
IVOUT2 = 5 mA
2.47
1.81
1.76
−40 −20
140
5.10
5.0
5.08
4.5
5.06
4.0
5.04
3.5
5.02
5.00
4.98
4.96
40
60
80
Temperature (°C)
100
2.5
2.0
2.5 V
2.6 V
Rex = ∞
0.5
0
20
40
60
80
Temperature (°C)
100
140
3.0
1.0 1.8 V
4.92
4.90
−40 −20
120
1.5
IVOUT1 = 5 mA
IVOUT2 = 5 mA
4.94
20
Figure 6. 1.8 V Output Voltage
VIN2 (VOLTS)
Voltage (V)
Figure 5. 2.5 V Output Voltage
0
120
0
140
0
Figure 7. 5.0 V Output Voltage
2
4
6
8
10
VIN1 (VOLTS)
Figure 8. VIN2 versus VIN1
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5
12
14
16
NCV8509 Series
TYPICAL PERFORMANCE CHARACTERISTICS
1.8
12
1.6
125°C
125°C
1.4
10
25°C
25°C
8
−40°C
IQ (mA)
IQ (mA)
1.2
1.0
0.8
0.6
6
−40°C
4
0.4
2
0.2
0
0
5
0
10
15
IOUT1 (mA)
20
0
25
10
20
Figure 9. IQ versus IOUT1
30
40 50 60
IOUT1 (mA)
70
80
90
100
Figure 10. IQ versus IOUT1
1.2
3.0
−40°C
−40°C
1.0
2.5
25°C
125°C
IQ (mA)
IQ (mA)
25°C
2.0
0.8
0.6
125°C
1.5
0.4
1.0
0.2
0.5
0
0
5
0
10
15
IOUT2 (mA)
20
25
0
10
20
Figure 11. IQ versus IOUT2
30
40 50 60
IOUT2 (mA)
70
80
90
100
Figure 12. IQ versus IOUT2
14
2.5
125°C
12
25°C
2.0
1.5
IQ (mA)
IQ (mA)
10
1.0
−40°C
8
6
4
−40°C
0.5
125°C
2
25°C
0
0
0
5
10
15
IOUT1, IOUT2 (mA)
20
25
0
Figure 13. IQ versus IOUT
(VOUT1 & VOUT2)
10
20
30
40 50 60 70
IOUT1, IOUT2 (mA)
Figure 14. IQ versus IOUT
(VOUT1 & VOUT2)
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6
80
90 100
NCV8509 Series
TYPICAL PERFORMANCE CHARACTERISTICS
6
4.0
3.5
5
3.0
VOUT1 (V)
VOUT1 (V)
4
3
2
125°C
1
25°C
2.5
2.0
1.5
1.0
−40°C
0.5
0
125°C
0
0
2
1
3
4
6
5
8
7
0
10
9
1
25°C
2
3
−40°C
4
VIN1 (V)
2.5
2.5
2.0
2.0
VOUT2 (V)
3.0
1.5
1.0
0.5
0.5
25°C
125°C
0
1
2
3
−40°C
125°C
0
5
4
7
6
9
8
10
0
1
25°C
2
3
Figure 17. VOUT2 (2.6 V) versus VIN1
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1
25°C
2
3
5
6
VIN1 (V)
7
8
Figure 18. VOUT2 (2.5 V) versus VIN1
2.0
125°C
9
10
9
10
−40°C
4
VIN1 (V)
0
8
1.5
1.0
0
7
Figure 16. VOUT1 (3.3 V) versus VIN1
3.0
VOUT2 (V)
VOUT2 (V)
Figure 15. VOUT1 (5 V) versus VIN1
5
6
VIN1 (V)
−40°C
4
6
5
VIN1 (V)
7
8
Figure 19. VOUT2 (1.8 V) versus VIN1
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7
9
10
NCV8509 Series
TYPICAL PERFORMANCE CHARACTERISTICS
10
40
RESET DELAY TIME (mS)
35
9.5
30
25
TIME (mS)
9.0
8.5
20
15
10
8.0
5
7.5
−40 −20
0
0
80
20
40
60
TEMPERATURE (°C)
100
120
20
0
Figure 20. Reset Delay Time versus
Temperature
40
60
80
100
CDelay (nF)
120
140
160
Figure 21. Reset Delay Time versus CDelay
2500
800
5V
5V
700
2000
600
VOLTS/SEC
VOLTS/SEC
3.3 V
1500
2.6 V
1000 2.5 V
1.8 V
3.3 V
500
2.6 V
400
300 2.5 V
200 1.8 V
500
100
0
0
0
10
20
30
40 50 60
CSLEW (nF)
70
80
90
100
30
40
Figure 22. Slew Rate versus CSlew
50
60
70
CSlew (nF)
80
90
100
Figure 23. Slew Rate versus CSlew
1000
100
UNSTABLE
REGION
3.3 V
UNSTABLE
REGION
5.0 V
2.5 V
ESR ()
ESR ()
100
STABLE
REGION
2.6 V
10
1.8 V
10
STABLE
REGION
CVOUT1 = 10 F
1
CVOUT2 = 10 F
1
0
10
20
30 40 50 60 70
OUTPUT CURRENT (mA)
80
90
0
100
Figure 24. VOUT1 Output Capacitor ESR
10
20
30 40 50 60 70
OUTPUT CURRENT (mA)
80
Figure 25. VOUT2 Output Capacitor ESR
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8
90
100
NCV8509 Series
TIMING DIAGRAMS
VIN1
Outputs are not actively discharged.
VOUT1
VOUT2
Figure 26. Response to Impulse
VIN1
VIN1
VOUT1
VOUT1
VIN1
VOUT1
Z(VOUT1) << Z(VOUT2)
VOUT2
VOUT2
Z(VOUT1) >> Z(VOUT2)
VOUT2
Figure 27. Output Decay vs. Load Impedance
Max VIN Delta
I(VIN2) × REX
Power Shunt Off
4.5 V
Power Shunt On
VIN1
VIN2
Figure 28. VIN Power Shunt
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9
NCV8509 Series
CIRCUIT DESCRIPTION
VIN
VOUT1
RESET
Reset Delay
Power Up
Reset Delay
Short on
VOUT1
Reset Delay
VIN1 Fast
Turn Off
RESET
Output Peak
Figure 29. Dual Drive RESET Valid
RESET
The delay capacitor is discharged when the regulation
(RESET threshold) has been violated. This is a latched
incident. The capacitor will fully discharge and wait for the
device to regulate before going through the delay time event
again.
The RESET function gets its drive from both the input
(VIN1) and the output (VOUT1). Because of this, it is able to
maintain a more reliable reset valid signal. Most regulators
maintain a valid reset signal down to 1 V on the output
voltage. The reset on the NCV8509 is valid down to 0 V on
the output voltage VOUT1 (power is provided via VIN1) and
the reset on the NCV8509 is valid down to 0 V on the input
voltage VIN1 (power is provided via VOUT1). Refer to
Figure 29 for operation timing diagrams.
Power Shunt
REX routes some of the current used in the VOUT2 to a
second input pin (VIN2). This is accomplished by using an
internal shunt. A simplified version of this shunt is shown in
Figure 30. This has the effect of reducing the amount of
power dissipated on chip. The effects of choosing the
external resistor value are shown in Figure 31.
Selection of the optimum Rex resistor value can be done
using the following equation:
Delay Function
The reset delay circuit provides a programmable (by
external capacitor) delay on the RESET output lead.
The delay lead provides source current (typically 6.0 µA)
to the external delay capacitor during the following
proceedings:
1. During power up (once the regulation threshold
has been verified);
2. After a reset event has occurred and the device is
back in regulation.
(Vin(max) 4.5)
Iout2(max)
When not using the power shunt, short VIN1 to VIN2.
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10
NCV8509 Series
1.8
VIN1
1.6
1.4
REX > 138
REX
Watts
1.2
VIN2
REX = 138
1.0
0.8
0.6
Voltage
Regulator
REX < 138
0.4
0.2
0
VOUT2
IOUT2 = 100 mA
0
5
15
20
25
VIN
Figure 30. Power Shunt
Figure 31. Power On Chip
VIN1
18 V
135 Ω
10
VIN1
6.0 V
VIN1
6.0 V
135 Ω
135 Ω
100 mA
21.5 mA
VIN2
4.5 V
VIN2
3.1 V
VIN2
4.5 V
VOUT2
2.5 V
21.5 mA
VOUT2
2.5 V
100 mA
VOUT2
2.5 V
100 mA
RLOAD
Figure 32.
+
600 mV
−
RLOAD
RLOAD
Figure 33.
Figure 34.
Why Use a Power Shunt?
VIN1
6.0 V
The power shunt circuitry helps manage and optimize
power dissipation on the integrated circuit.
Figure 32 shows a 100 mA load. A 135 Ω resistor
dissipates 1.35 W as shown.
Without the power shunt, the 135 Ω resistor would run
into head room issues at 6.0 V and would only be able to
drive 21.5 mA as shown in Figure 33 before causing the
2.5 V output to collapse.
Figure 34 shows the power shunt circuitry adding the
current back in at low voltage operation. So the power is
moved off chip at high voltage where it is needed most.
To further clarify, Figure 35 shows the maximum allowed
resistor value (29 Ω) without the power shunt for 6.0 V
operation.
Figure 36 shows the scenario at high voltage. Only 290 mW
of power is dissipated off chip compared to Figure 32 with
1.35 W.
29 Ω
+
600 mV
−
100 mA
100 mA
VIN2
3.1 V
VIN2
15.1 V
VOUT2
2.5 V
100 mA
VOUT2
2.5 V
100 mA
Figure 35.
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VIN1
18 V
29 Ω
RLOAD
11
21.5 mA
78.5 mA
RLOAD
Figure 36.
NCV8509 Series
NCV8509
Power Dissipation
Shunt
VIN1
NCV8509 has a power shunt circuit which reduces the
power on chip by utilizing an external resistor, REX. Thus
the power on chip, PIC, is equal to the total power, PT, minus
the power dissipated in the resistor PREX. Refer to Figure 37.
PIC PTOTAL PREX
Iq
REX
(1)
where
PTOTAL (VIN1 VOUT1) IOUT1
+
VSAT Q1
−
VZ
(2)
VIN2
(VIN1 VOUT2) IOUT2 (VIN1 Iq)
Control
Circuitry
Q2
and
PREX (VIN1 VIN2) IOUT2
Q3
(3)
VOUT2
VOUT1
IOUT2
IOUT1
GND
Figure 37.
VIN1 VSAT
VIN2 VREF
VIN1 (IOUT2 REX)
for VIN1 (VREF VSAT)
(4)
for (VREF VSAT) VIN1 (VREF (IOUT2 REX))
for (VREF (IOUT2 IOUT)) VIN1
where VREF = VZ − VBE when Q1 is normally conducting.
Based on equation 3, the power in REX is dependent on
VIN2. The voltage on VIN2 is controlled by the shunt circuit,
which has three modes of operation, as seen in Figure 38.
Mode 1. At low battery VIN2 is equal to VIN1 minus the
saturation voltage of the shunt output NPN.
Mode 2. Once VIN1 rises above the reference voltage of
the shunt circuit, VIN2 will regulate at the VREF.
Mode 3. VIN2 would continue to regulate at VREF, but
since IOUT2 is not infinite, when VIN1 rises higher than the
reference voltage plus the voltage drop across the external
resistor REX, it will force VIN2 to be VIN1 − (IOUT2 × REX).
Equation 4 provides a summary for VIN2.
Combining equations 3 and 4 gives three different
equations for power across REX.
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12
PMODE1 (VSAT IOUT2)
(5)
PMODE2 (VIN1 VREF) IOUT2
(6)
PMODE3 IOUT22 REX
(7)
NCV8509 Series
Max VIN Delta
I(VIN2) × REX
Shunt Off
4.5 V
Shunt On
VIN1
VIN2
Mode 1
Mode 3
VIN1 VREF VSAT
VIN1 VREF (IOUT2 REX)
VIN2 VIN1 VSAT
VIN2 VIN1 (IOUT2 REX)
Mode 2
VREF VSAT VIN1 VREF (IOUT2 REX)
VIN2 VREF
Figure 38. VIN Shunt
Thermal Resistance,
Junction to Ambient, RJA, (°C/W)
100
80
RJA’s less than the calculated value in equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
70
Heat Sinks
90
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RJA:
60
50
40
0
200
600
400
Copper Area (mm2)
800
RJA RJC RCS RSA
Figure 39. 16 Lead SOW (Exposed Pad), JA as a
Function of the Pad Copper Area (2 oz. Cu
Thickness), Board Material = 0.0625 G−10/R−4
where:
RJC = the junction−to−case thermal resistance,
RCS = the case−to−heatsink thermal resistance, and
RSA = the heatsink−to−ambient thermal resistance.
RJC appears in the package section of the data sheet. Like
RJA, it too is a function of package type. RCS and RSA are
functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heat sink manufacturers.
Once the value of PIC(max) is known, the maximum
permissible value of RJA can be calculated:
T
RJA 150°C A
PIC
(9)
(8)
The value of RJA can then be compared with those in the
package section of the data sheet. Those packages with
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13
NCV8509 Series
≈ 10 µs
VOUT1
Fast SLEW Rate >> Soft Start
≈ 10 µs
Fast SLEW Rate >> Soft Start
VOUT2
Disable Time
Disable Time
Decay Time Dependent
on External Load
Decay Time Dependent
on External Load
Short On
VOUT1
Short On
VOUT2
Figure 40. Fault Response. Note the High SLEW Rate Coming Out of Fault Conditions.
Soft Start Only Applies to a Power Up Sequence.
Slew Rate Control
Slew time can be calculated using the standard capacitor
equation.
Figure 41 shows the circuitry associated with Slew Rate
Control. The diagram highlights the control of one output for
simplicity. VOUT1 and VOUT2 are both controlled on the IC.
The slew rate capacitor (CSLEW) is charged with an
on−chip current source runing at 6.0 A (typ.). Charging a
capacitor with a current source creates a linear voltage ramp
as shown in Figure 42.
The lowest voltage to the positive terminals of the
comparator (Error Amp) dominates the output voltage
(VOUT). Consequently, when CSLEW is fully discharged on
power up, it is the dominant factor on the positive terminal
and disables the output. The output (VOUT) follows the
linear ramp on the SLEW pin (after being gained up with R1
and R2) until VBG becomes the dominant voltage. This
occurs when SLEW = VBG + VD1 or approximately 1.8 V.
I C dv , t dt
Using a 33 nF capacitor, the slew time is:
t
V
Av OUT
1.28 V
For a 5 V output, the gain would be:
Av 5 V 3.9 VV
1.28 V
assuming VBG = 1.28 V.
The resultant slew rate on the output is the slew rate on the
SLEW pin multiplied by the gain, or:
VIN1
(182 Vs) (3.9 VV) 710 Vs
D2
VBG
+
+
−
VOUT
Error Amp
R1
SLEW Pin Voltage (V)
D1
SLEW
CSLEW
(33 nF)(1.8 V)
9.9 ms
6 A
The corresponding slew rate for this is 1.8 V/9.9 ms =
182 V/s ON THE SLEW PIN.
To calculate the slew rate on outputs, you must multiply
by the gain set up by R1 and R2.
Internal
Voltage
Rail ≈ 3.8 V
6.0 µA
C(V)
I
R2
3.8
Outputs in Regulation
1.8
tSLEW
Figure 41. Slew Control Circuitry
Time (ms)
Figure 42.
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14
NCV8509 Series
ORDERING INFORMATION
Device
Output Voltage
Package
NCV8509PDW26
NCV8509PDW26R2
47 Units/Rail
5 V/2.6
V/2 6 V
1000 Tape & Reel
SOIC 16 Lead
Wide Body
Exposed Pad
NCV8509PDW25
NCV8509PDW25R2
5 V/2.5
V/2 5 V
NCV8509PDW18
NCV8509PDW18R2
Shipping
47 Units/Rail
1000 Tape & Reel
47 Units/Rail
3 3 V/1.8
3.3
V/1 8 V
1000 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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15
NCV8509 Series
PACKAGE DIMENSIONS
SOIC 16 LEAD WIDE BODY
EXPOSED PAD
PDW SUFFIX
CASE 751R−02
ISSUE A
−U−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL BE
0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
6. 751R−01 OBSOLETE, NEW STANDARD 751R−02.
A
M
16
9
P
0.25 (0.010)
M
W
M
B
1
R x 45
8
−W−
G
PIN 1 I.D.
14 PL
DETAIL E
TOP SIDE
C
F
−T−
0.10 (0.004) T
K
D 16 PL
0.25 (0.010)
M
T U
SEATING
PLANE
W
S
S
DIM
A
B
C
D
F
G
H
J
K
L
M
P
R
MILLIMETERS
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
3.76
3.86
0.25
0.32
0.10
0.25
4.58
4.78
0
7
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.148
0.152
0.010
0.012
0.004
0.009
0.180
0.188
0
7
0.395
0.415
0.010
0.029
J
DETAIL E
H
EXPOSED PAD
1
8
L
16
9
BACK SIDE
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Phone: 81−3−5773−3850
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16
For additional information, please contact your
local Sales Representative.
NCV8509/D