Revised November 1999 74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The ABT374 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops. ■ Edge-triggered D-type inputs ■ Buffered positive edge-triggered clock ■ 3-STATE outputs for bus-oriented applications ■ Output sink capability of 64 mA, source capability of 32 mA ■ Guaranteed output skew ■ Guaranteed multiple output switching specifications ■ Output switching specified for both 50 pF and 250 pF loads ■ Guaranteed simultaneous switching, noise level and dynamic threshold performance ■ Guaranteed latchup protection ■ High impedance glitch free bus loading during entire power up and power down cycle ■ Non-destructive hot insertion capability Ordering Code: Order Number 74ABT374CSC 74ABT374CSJ Package Number M20B M20D 74ABT374CMSA MSA20 74ABT374CMTC MTC20 74ABT374CPC N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names © 1999 Fairchild Semiconductor Corporation DS011510 Description D0–D7 Data Inputs CP Clock Pulse Input (Active Rising Edge) OE 3-STATE Output Enable Input (Active LOW) O0–O7 3-STATE Outputs www.fairchildsemi.com 74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs November 1992 74ABT374 Functional Description Function Table The ABT374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs are in a high impedance state. Operation of the OE input does not affect the state of the flipflops. Inputs Internal Outputs Function OE CP H H L NC Z Hold H H H NC Z Hold D Q O L L Z Load H H Z Load L L L Data Available H H H L H L NC NC No Change in Data L H H NC NC No Change in Data H H L L Data Available H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions −65°C to +150°C Storage Temperature Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage VCC Pin Potential to −40°C to +85°C +4.5V to +5.5V Minimum Input Edge Rate (∆V/∆t) −0.5V to +7.0V Data Input Input Voltage (Note 2) −0.5V to +7.0V Enable Input 20 mV/ns Input Current (Note 2) −30 mA to +5.0 mA Clock Input 100mV/ns Ground Pin 50 mV/ns Voltage Applied to Any Output in the Disabled or Power-Off State −0.5V to 5.5V in the HIGH State −0.5V to VCC Current Applied to Output twice the rated IOL (mA) in LOW State (Max) DC Latchup Source Current: −150 mA OE Pin (Across Comm Operating Range) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. −500 mA Other Pins Over Voltage Latchup (I/O) 10V Note 2: Either voltage limit or current limit is sufficient to protect inputs DC Electrical Characteristics Symbol Parameter Min Typ Max 2.0 Units VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH Output HIGH Voltage VCC V Conditions Recognized HIGH Signal Recognized LOW Signal Min IIN = −18 mA IOH = −3 mA 2.5 V Min 2.0 V Min IOH = −32 mA V Min IOL = 64 mA µA Max µA Max VOL Output LOW Voltage 0.55 IIH Input HIGH Current 1 1 IBVI Input HIGH Current Breakdown Test 7 IIL Input LOW Current −1 VID Input Leakage Test −1 4.75 µA Max V 0.0 VIN = 2.7V (Note 4) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 4) VIN = 0.0V IID = 1.9 µA, All Other Pins Grounded IOZH Output Leakage Current 10 µA 0 − 5.5V VOUT = 2.7V; OE = 2.0V IOZL Output Leakage Current −10 µA 0 − 5.5V VOUT = 0.5V; OE = 2.0V IOS Output Short-Circuit Current −275 mA Max VOUT = 0.0V ICEX Output High Leakage Current 50 µA Max VOUT = VCC IZZ Bus Drainage Test 100 µA 0.0 VOUT = 5.5V; All Others VCC or GND ICCH Power Supply Current 50 µA Max All Outputs HIGH ICCL Power Supply Current 30 mA Max All Outputs LOW ICCZ Power Supply Current 50 µA Max OE = VCC; All Others at VCC or GND ICCT Additional ICC/Input Outputs Enabled 2.5 mA Outputs 3-STATE 2.5 mA Max Enable Input VI = VCC − 2.1V Outputs 3-STATE 2.5 mA Data Input VI = VCC − 2.1V mA/ Outputs OPEN −100 VI = VCC − 2.1V All Others at VCC or GND ICCD Dynamic ICC No Load (Note 4) 0.30 MHz Max OE = GND, (Note 3) One Bit Toggling, 50% Duty Cycle Note 3: For 8-bit toggling, ICCD <0.8 mA/MHz. Note 4: Guaranteed, but not tested. 3 www.fairchildsemi.com 74ABT374 Absolute Maximum Ratings(Note 1) 74ABT374 DC Electrical Characteristics (SOIC package) Symbol Parameter Min Typ Max Units VCC 0.5 0.8 Conditions CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL V 5.0 TA = 25°C (Note 5) VOLV Quiet Output Minimum Dynamic VOL −1.3 −0.9 V 5.0 TA = 25°C (Note 5) VOHV Minimum HIGH Level Dynamic Output Voltage 2.5 3.0 V 5.0 TA = 25°C (Note 6) VIHD Minimum HIGH Level Dynamic Input Voltage 2.0 1.6 V 5.0 TA = 25°C (Note 7) VILD Maximum LOW Level Dynamic Input Voltage V 5.0 TA = 25°C (Note 7) 1.3 0.8 Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not tested. Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 7: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD ). Guaranteed, but not tested. AC Electrical Characteristics (SOIC and SSOP Package) Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = −40°C to +85°C VCC = +5.0V VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ fMAX Maximum Clock Frequency 150 200 tPLH Propagation Delay 2.0 3.2 5.0 1.4 6.6 2.0 5.0 tPHL CP to On 2.0 3.3 5.0 2.0 7.6 2.0 5.0 tPZH Output Enable Time tPZL tPHZ Output Disable Time tPLZ Max Min Max 150 Min Units Max 150 MHz 1.5 3.1 5.3 0.8 5.7 1.5 5.3 1.5 3.1 5.3 1.5 7.2 1.5 5.3 1.5 3.6 5.4 1.3 7.2 1.5 5.4 1.5 3.4 5.4 1.0 7.0 1.5 5.4 ns ns ns AC Operating Requirements Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = −40°C to +85°C VCC = +5.0V V CC = 4.5V to 5.5V VCC = 4.5V to 5.5V CL = 50 pF CL = 50 pF CL = 50 pF Min Max Min Max Min tS(H) Setup Time, HIGH 1.5 2.5 1.0 tS(L) or LOW Dn to CP 1.5 2.5 1.5 tH(H) Hold Time, HIGH 1.0 2.5 1.0 tH(L) or LOW Dn to CP 1.0 2.5 1.0 tW(H) Pulse Width, CP 3.0 3.3 3.0 tW(L) HIGH or LOW 3.0 3.3 3.0 www.fairchildsemi.com 4 Units Max ns ns ns 74ABT374 Extended AC Electrical Characteristics (SOIC Package) Symbol TA = −40°C to +85°C TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V CL = 50 pF CL = 250 pF CL = 250 pF 8 Outputs Switching (Note 9) 8 Outputs Switching Parameter (Note 8) (Note 10) Min Max Min Max Min Max tPLH Propagation Delay 1.5 5.7 2.0 7.8 2.0 10.0 tPHL CP to On 1.5 5.7 2.0 7.8 2.0 10.0 tPZH Output Enable Time 1.5 6.2 2.0 8.0 2.0 10.5 1.5 6.2 2.0 8.0 2.0 10.5 1.0 5.5 1.0 5.5 tPZL Output Disable Time tPHZ tPZL Units (Note 11) ns ns (Note 11) ns Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 11: The 3-STATE delay Time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet. Skew (Note 16) (SOIC Package) Symbol TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 250 pF 8 Outputs Switching 8 Outputs Switching (Note 12) (Note 13) Max Max 1.0 1.8 ns 1.0 1.8 ns 1.8 4.3 ns 2.0 4.3 ns 2.5 4.6 ns Parameter tOSHL Pin to Pin Skew (Note 14) HL Transitions tOSLH Pin to Pin Skew (Note 14) LH Transitions tPS Duty Cycle (Note 13) LH–HL Skew tOST Pin to Pin Skew (Note 14) LH/HL Transitions tPV Device to Device Skew (Note 15) LH/HL Transitions Units Note 12: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 13: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). This specification is guaranteed but not tested. Note 15: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. Note 16: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Capacitance Symbol Parameter Typ Units Conditions (TA = 25°C) CIN Input Capacitance 5.0 pF V CC = 0V COUT (Note 17) Output Capacitance 9.0 pF V CC = 5.0V Note 17: COUT is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. 5 www.fairchildsemi.com 74ABT374 AC Loading *Includes jig and probe capacitance FIGURE 2. VM = 1.5V FIGURE 1. Standard AC Test Load Input Pulse Requirements Amplitude Rep. Rate tw tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 5. Propagation Delay, Pulse Width Waveforms FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms www.fairchildsemi.com 6 74ABT374 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M20B 7 www.fairchildsemi.com 74ABT374 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 8 74ABT374 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20 9 www.fairchildsemi.com 74ABT374 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 10 74ABT374 Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MO-001, 0.300” Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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