FUJITSU SEMICONDUCTOR DATA SHEET DS04-28501-2E ASSP Single Chip 8-Bit A/D and 9-Bit D/A Converter MB40168/MB40178 ■ DESCRIPTION The Fujitsu MB40168 and MB40178 are high speed, low power single chip A/D and D/A converters designed for video processing applications. The A/D converter has a resolution of 8 bits while the D/A converter has 9bit resolution. They are fabricated in Fujitsu’s advanced bipolar technology, and housed in a 48-pin plastic shrink DIP or 44-pin plastic QFP package. ■ FEATURES • Resolution • • • • • A/D: 8 bits D/A: 9 bits Conversion Rate A/D: Max. 20 MSPS D/A: Max. 40 MSPS Linearity Error A/D: Max. + 0.3% D/A: Max. + 0.2% On-chip reference voltage generator (resistor divided method) and clamp circuit Analog Input Voltage 3 to 5 V without clamp circuit 0 to 3 V in 1.95 VP-P clamp circuit Analog Output Voltage 3 to 5 V (Continued) ■ PACKAGES 48 pin, Plastic SH-DIP (DIP-48P-M01) 44 pin, Plastic QFP (FPT-44P-M11) This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. MB40168/MB40178 (Continued) • Digital Input/Output Interface • Power Supply Voltage • Power Dissipation • Package Options TTL Levels + 5.0 V single power supply Typ. 350 mW 48-pin Plastic Shrink DIP/ 44-pin Plastic QFP Package ■ PIN ASSIGNMENTS • MB40168 (TOP VIEW) D.GND 1 48 A.GND DACLK 2 47 V CCD (LSB) D D9 3 46 V CCA D D8 4 45 A.OUT D D7 5 44 COMP D D6 6 43 V RIN COMP A.OUT VCCA V CCD A.GND D.GND D.GND DACLK D D9 (LSB) D D8 D D7 (TOP VIEW) 3 31 V RB D D3 9 40 NC D D3 4 30 D.GND D D2 10 39 D.GND D D2 5 29 A.GND (MSB) D D1 11 38 A.GND (MSB) D D1 6 28 V CCD NC 12 37 V CCD (LSB) D A8 7 27 V CCA NC 13 36 V CCD D A7 8 26 V RM NC 14 35 V CCA D A6 9 25 V INA (LSB) D A8 15 34 V CCA D A5 10 24 V CLMP D A7 16 33 V RM D A4 11 23 12 13 14 15 16 17 18 19 20 21 22 V OUTC D A6 17 32 V INA D A5 18 31 V CLMP D A4 19 30 V OUTC D A3 20 29 V INC D A2 21 28 V RT (MSB) D A1 22 27 V CCA ADCLK 23 26 V CCD D.GND 24 25 A.GND (FPT-44P-M11) V INC D D4 V RT V RB V CCA 41 V CCD 8 A.GND D D4 A.GND V REF D.GND 32 ADCLK 2 (MSB) D A1 D D5 D A3 1 D A2 D D6 44 43 42 41 40 39 38 37 36 35 34 33 V RIN D D5 7 42 V REF (DIP-48P-M01) 2 MB40168/MB40178 • MB40178 (TOP VIEW) D.GND 1 48 A.GND DACLK 2 47 V CCD (MSB) D D1 3 46 V CCA D D2 4 45 A.OUT D D3 5 44 COMP D D4 6 43 V RIN COMP A.OUT VCCA V CCD A.GND D.GND D.GND DACLK D D1 (MSB) D D2 D D3 (TOP VIEW) 3 31 V RB D D7 9 40 NC D D7 4 30 D.GND D D8 10 39 D.GND D D8 5 29 A.GND (LSB) D D9 11 38 A.GND (LSB) D D9 6 28 V CCD NC 12 37 V CCD (LSB) D A8 7 27 V CCA NC 13 36 V CCD D A7 8 26 V RM NC 14 35 V CCA D A6 9 25 V INA (LSB) D A8 15 34 V CCA D A5 10 24 V CLMP D A7 16 33 V RM D A4 11 23 12 13 14 15 16 17 18 19 20 21 22 V OUTC D A6 17 32 V INA D A5 18 31 V CLMP D A4 19 30 V OUTC D A3 20 29 V INC D A2 21 28 V RT (MSB) D A1 22 27 V CCA ADCLK 23 26 V CCD D.GND 24 25 A.GND (FPT-44P-M11) V INC D D6 V RT V RB V CCA 41 V CCD 8 A.GND D D6 A.GND V REF D.GND 32 ADCLK 2 (MSB) D A1 D D5 D A3 1 D A2 D D4 44 43 42 41 40 39 38 37 36 35 34 33 V RIN D D5 7 42 V REF (DIP-48P-M01) 3 MB40168/MB40178 ■ PIN DESCRIPTION Symbol Pin No. I/O Name & Function QFP-44 SH-DIP-48 VCCD 19, 28, 37 26, 36, 37, 47 — Digital Power Supply pins (+ 5 V). VCCA 20, 27, 36 27, 34, 35, 46 — Analog Power Supply pins (+ 5 V). DGND 16, 30, 39, 40 1, 24, 39 — Digital Ground (0 V). These pins should be connected to the analog ground on the application system. AGND 17, 18, 29, 38 25, 38, 48 — Analog Ground (0 V). These pins should be connected to the analog ground on the application system. DA8 - DA1 7 - 14 15 - 22 O ADC Digital Output pins. TTL level. ADCLK 15 23 I ADC Clock Input pin. TTL level. VRT 21 28 I ADC Reference Voltage Input pin. (5 V Input) VINC 22 29 I Sync Tip Clamp Circuit Analog Input pin. (0 - 3 V, 1.95 VP-P). When a clamp circuit is not used, this pin is connected to ground. VOUTC 23 30 O Clamp Circuit Analog Output pin. It is used by adding a capacitor (1 µF or more) between VCLMP and VOVTC pins. When a clamp circuit is not used, this pin is left open. VCLMP 24 31 O Clamp Voltage Output pin (3.05V Output). When a clamp circuit is not used, this pin is left open. VINA 25 32 I ADC Analog Signal Input pin. (3 - 5 V) VRM 26 33 — VRB 31 41 I ADC Reference Voltage Input pin. (3 V) VREF 32 42 O Reference Voltage Output pin. (Resistor Divider, 3 V) By connecting this pin to VRB pin, 3V Voltages are generated. When a reference voltage is not used, this pin is left open. VRIN 33 43 I DAC Reference Voltage Input pin (3 V) COMP 34 44 — Phase Compensation Capacitor pin. (Capacitor greater than 0.1 µF should be connected between this pin and Analog Ground.) AOUT 35 45 O Analog Signal Output pin DACLK 41 2 I DAC Clock Input pin. TTL level. 3 - 11*2 I DAC Digital Data Input pins. TTL level. DD9 - DD1 1 - 6 *1 42 - 44 ADC Middle Reference Voltage Monitor pin. (Mid of VRT - VRB is set to this pin). Normally this pin is left open. *1: MB40168 (MSB: 6 pin, LSB: 42 pin), MB40178 (MSB: 42 pin, LSB: 6 pin) *2: MB40168 (MSB: 11 pin, LSB: 3 pin), MB40178 (MSB: 3 pin, LSB: 11 pin) 4 MB40168/MB40178 ■ BLOCKDIAGRAM VCCD VCCA VINA ADCLK VRT R1 1 DA1 (MSB) R 2 DA2 R DA3 127 Latch & Buffer 255 to 8 Encoder R/2 VRM DA4 DA5 R/2 128 DA6 DA7 R 254 DA8 (LSB) R 255 R2 VRB VINC VOUTC ≈ 0.6VCCA + 50mV Reference voltage generator Clamp VCLMP 0.6VCCA VREF COMP VRIN Reference resistor DACLK Amp DD9 (LSB) 9 DD1 (MSB) Input buffer 9 Master Slave register 9 DGND Buffer 9 Current switch 9 R-2R Ladder resistor network AOUT AGND 5 MB40168/MB40178 ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Power supply voltage VCCA, VCCD –0.5 to 7.0 V Analog input voltage VINA –0.5 to VCC + 0.5 V VRT, VRB, VRIN –0.5 to VCC + 0.5 V Clamp circuit input voltage VINC –0.5 to VCC + 0.5 V Digital input voltage VIND –0.5 to 7.0 V Storage temperature TSTG –55 to +125 °C Reference voltage Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 6 MB40168/MB40178 ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Unit Min. Typ. Max. VCCA, VCCD 4.75 5.00 5.25 V Clamp circuit input voltage *2 VINC 0 — 3 V Analog input voltage VINA VRB — VRT V Top VRT VCCA – 0.1 VCCA VCCA + 0.1 V Bottom VRB 2.75 3.0 3.25 V VCCA - VRIN 0.7 2.0 2.2 V VRIN 2.65 3.0 4.3 V Digital input high voltage VIHD 2.0 — — V Digital input low voltage VILD — — 0.8 V Digital output high current IOH –400 — — µA Digital output low current IOL — — 1.6 mA A/D fCLKAD — — 20 MHz D/A fCLKDA — — 40 MHz Minimum high clock pulse width A/D tWHAD 22.5 — — ns D/A tWHDA 10.5 — — ns Minimum Low clock pulse width A/D tWLAD 22.5 — — ns D/A tWLAD 10.5 — — ns Set up time tSU 10 — — ns Hold time tH 4 — — ns Clamp capacitance CCLMP 1 — — µF Phase compensation capacitance CCOMP 0.1 — — µF Ta –20 — +70 Power supply voltage *1 ADC reference voltage *3 DAC reference voltage Clock frequency Ambient operating temperature o C *1: VCCA and VCCD must be used in the same voltage level. *2: VINC must have an amplitude of VRT - VCLMP. *3: VRT - VRB must have 2.0V±0.1V. 7 MB40168/MB40178 ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics • Analog Block (VCCA = VCCD = 4.75 V to 5.25 V, Ta = –20 oC to +70 oC) Parameter 8 Symbol Condition ADC resolution — DAC resolution — Value Unit Min. Typ. Max. — — 8 — bits — — 9 — bits — ± 0.15 ± 0.3 % — ± 0.1 ± 0.2 % 0.3 1.3 — MΩ ADC linearity error LEAD DAC linearity error LEDA DC accuracy VCCA = VCCD = 5.0 V Analog input equivalent impedance RINA RINA = Analog input capacitance CINA fINA = 1 MHz — 40 — pF Analog input high current IIHA VINA = VRT — — 45 µA Analog input low current IILA VINA = VRB — — 40 µA Reference output voltage VREF 0.6VCCA – 0.1 0.6VCCA 0.6VCCA+ 0.1 V Clamp voltage VCLMP — — VREF + 50 mV — V ADC reference current IRB — –8.5 –5.5 –3.0 mA DAC reference current IRIN VRIN = 3.000 V — — 10 µA Clamp circuit input current IINC VINC = 0 V –600 –200 — µA VCCA–20mV VCCA — V 2.934 3.004 3.072 V 192 240 288 Ω — 70 125 mA Full scale output voltage VOFS Zero scale output voltage VOZS Output impedance RO Supply current ICC VRT –VRB IIHA – IILA VREF, VRB, VRIN shorted together — VCCA = 5.00 V VCCD = 5.00 V VRIN = 3.000 V Ta = +25 oC — MB40168/MB40178 • Digital Block (VCCA = VCCD = 4.75 V to 5.25 V, Ta = –20 oC to +70 oC) Parameter Symbol Value Condition Min. Typ. Max. Unit Digital output high voltage VOHD IOH = –400 µA 2.7 — — V Digital output low voltage VOLD IOL = 1.6 mA — — 0.4 V Digital input high voltage VIHD — 2.0 — — V Digital input low voltage VILD — — — 0.8 V Digital input high current IIHD VIHD = 2.7 V — — 20 µA Digital input low curent IILD VILD = 0.4 V –100 — — µA 2. AC CHARACTERISTICS (VCCA = VCCD = 4.75 V to 5.25 V, Ta = –20 oC to +70 oC) Parameter Symbol Condition A/D fSAD D/A Value Unit Min. Typ. Max. — 20 — — MSPS fSDA — 40 — — MSPS Digital output delay time tpd AD — 8 15 30 ns Analog output delay time tpd DA — 10 — ns — 5 — ns — 5 — ns — 16 — ns Maximum conversion rate Analog output rise time tr Analog output fall time tf Settling time tset LH, tset HL CL = 15 pF Terminating resistor AOUT = 240 Ω 9 MB40168/MB40178 ■ LINEARITY ERROR OF A/D CONVERSION • Ideal Characteristic Step Output Code 255 11111111 254 11111110 253 • • • 129 11111101 • • • 10000001 128 10000000 127 • • • 2 01111111 • • • 00000010 1 00000001 0 00000000 VZT ≅ 3.006V VFT ≅ 4.996V VINA Note: The values for VZT and VFT are typical values under conditions that VCCA = VCCD = VRT = 5.000V and VRB = 3.000V. • Actual Characteristic Step Output Code 255 11111111 254 11111110 253 • • • 129 11111101 • • • 10000001 128 10000000 127 • • • 2 01111111 • • • 00000010 1 00000001 0 00000000 LE253 LE129 LE128 LE127 LE2 LE1 VZT 10 VINA VFT MB40168/MB40178 ■ OUTPUT VOLTAGE CHARACTERISTIC OF D/A CONVERTER BLOCK Input Output DD1 ~ DD9 A.OUT 511 (VCCA) VOFS 5.000V 5.000V 0 VOZS (VRIN) 3.004V 3.000V 1 LSB = 4mV ■ CALCULATION OF DAC OUTPUT VOLTAGE WHEN THE IDEAL CONVERSION IS PERFORMED AOUTN = VCCA – 511-N 512 x (VCCA – VRIN) (N: Digital code (0 ~ 511) VOFS = VCCA 511 VOZS = VCCA – 512 x (VCCA – VRIN) 11 MB40168/MB40178 ■ EQUIVALENT CIRCUITS OF ADC BLOCK • Analog Input Equivalent Circuit VCCA VCCA VINA VINA VD CINA RINA IBIAS A.GND A.GND A.GND VRB x 255 circuits CINA: Junction Capacitance of non-linear emitter follower RINA: Linear resistance model of input current by the comparator switching VINA < VRB: ∞ CLK = “H”: ∞ VRB: This is the voltage on VRB Pin, not VRB Pin itself. IBIAS: Constant input bias current VD: Base-Collector junction diode of emitter follower transistor • Clamp Input Equivalent Circuit VCCA 2.0mA 0.6 x VCC + 50mV +VBE 850kΩ VINC A.GND VCLMP VOUTC - + CCLMP 12 MB40168/MB40178 • Digital Input Equivalent Circuit VCCD 6.5kΩ 50kΩ 3.2kΩ 50kΩ 3.2kΩ Clock Input ADCLK VTH = 1.4V D.GND • Digital Output Load Circuit To pin tested Test point CL = 15pF D.GND NOTE: CL includes the floating capacitance of probe and jig. 13 MB40168/MB40178 ■ EQUIVALENT CIRCUITS OF DAC BLOCK • Digital Input Equivalent Circuit VCCD 50kΩ 50kΩ Digital Input D01 - D09 DACLK VTH = 1.4V D.GND • Analog Output Equivalent Circuit VCCA RO = 240Ω A.OUT IO A.GND • Reference Voltage Generator Equivalent Circuit VCCA ≅ 20kΩ Buffer VREF ≅ 30kΩ A.GND 14 IRB MB40168/MB40178 ■ TYPICAL CONNECTION CIRCUITS Example 1: Video Signal Input to VINC Pin +5V +5V VCCA Video Signal Input VCCD VINC VOUTC 1 µF MB40168/MB40178 + VCLMP VINA AGND DGND Example 2: Video Signal Input to VCLMP and VINA Pins +5V +5V VCCA VCCD VINC +9V VOUTC MB40168/MB40178 External Circuit VCLMP 2.2 kΩ 1 µF + - VINA Video Signal Input 2SA933 AGND DGND AGND 15 MB40168/MB40178 ■ CLAMP CIRCUIT OPERATION Clamp Circuit Clamp Voltage is set at 0.6 x VCC + 50 mV (typ.) VCCA VCCA I ≈ 2 mA Bias Circuit VINC AGND ≈ 3.05 V VOUTC CCLMP + VCLMP VINA A/D Converter Signal Level at VINA pin VCCA = 5.0 V Signal Level at VINC pin AGND VCLMP ≈ 3.05 V VREF ≈ 3.0 V Note: When Clamp Circuit is not applied the signals should be connected as follows: VINC: Connect to GND. VOUTC: Leave open. VCLMP: Leave open. 16 MB40168/MB40178 ■ TYPICAL CONNECTION CIRCUIT(Example) System Analog Ground DAC Clock Input Digiral Input (DAC) 1 DGND AGND 48 2 DACLK VCCD 47 3 (LSB) DD9 VCCA 46 4 DD8 AOUT 45 5 DD7 COMP 44 6 DD6 VRIN 43 7 DD5 VREF 42 8 DD4 VRB 41 9 DD3 NC 40 10 DD2 DGND 39 11 (MSB) DD1 Digiral Output (DAC) ADC Clock Input Analog O/P (DAC) 0.1 µF 0.1 µF MB40168 AGND 38 Open 12 NC VCCD 37 Open 13 NC VCCD 36 Open 14 NC VCCA 35 15 (LSB) DA8 VCCA 34 16 DA7 0.1 µF System Analog Power Supply 2 µF VRM 33 17 DA6 VINA 32 18 DA5 VCLMP 31 19 DA4 VOUTC 30 20 DA3 VINC 29 21 DA2 VRT 28 22 (MSB) DA1 VCCA 27 23 ADCLK VCCD 26 Open 1 µF Analog Input (ADC) 1 µF 24 DGND AGND 25 17 MB40168/MB40178 ■ NOTES ON PCB LAYOUT Power Supply Lines The device’s power supply lines (VCCA, VCCD, AGND and DGND) should be laid out as analog lines and should be separated in so far as possible from other digital lines in order to reduce noise. Also the track widths of these lines should be as wide as possible to reduce parasitic impedance. Coupling Capacitors The device’s power supply lines VCCA and VCCD and the reference voltage pins VRIN, VREF, VRB, and VRT should be decoupled to analog ground by means of approx. 1 µF capacitors which should be placed as close as possible to these pins. Digital Output Load The load at the digital outputs should be kept as low as possible to prevent noise in the power supply lines caused by digital output switching. If, due to long wiring, the load becomes large then a buffer with small input capacitance should be inserted to reduce load capacitance. ■ OTHER NOTES ON OPERATION When using the D/A converter with its VRIN pin connected to the VREF pin, the A/D converter’s VRB pin must also be connected to the VREF because otherwise the internal reference voltage generation circuitry cannot output 3 V. When using the D/A converter with 8 bit resolution the DD9 (LSB) pin should be grounded. 18 MB40168/MB40178 ■ PACKAGE DIMENSIONS 48 pin, Plastic SH-DIP (DIP-48P-M01) +0.20 43.69 –0.30 +.008 1.720 –.012 INDEX-1 13.80±0.25 (.543±.010) INDEX-2 0.51(.020)MIN 5.25(.207) MAX 0.25±0.05 (.010±.002) 3.00(.118) MIN +0.50 1.00 –0 +.020 .039 –0 1.778±0.18 (.070±.007) 1.778(.070) MAX C 1994 FUJITSU LIMITED D48002S-3C-3 0.45±0.10 (.018±.004) 15.24(.600) TYP 15°MAX 40.894(1.610)REF Dimensions in mm (inches). (Continued) 19 MB40168/MB40178 44 pin, Plastic QFP (FPT-44P-M11) 14.40±0.40 SQ (.567±.016) 10.00±0.20 SQ (.394±.008) 33 2.35(.093)MAX 0.05(.002)MIN (STAND OFF) 23 Details of "A" part 34 22 0.15(.006) 8.00 (.315) REF INDEX 0.20(.008) 11.60±0.30 (.457±.012) 0.18(.007)MAX 0.53(.021)MAX "A" 44 12 Details of "B" part LEAD No. 1 0.80(.0315)TYP 11 0.30±0.10 (.012±.004) 0.16(.006) M 0.15±0.05 (.006±.002) 0~10° "B" 1.40±0.30 (.055±.012) 0.10(.004) C 20 1994 FUJITSU LIMITED F44018S-1C-1 Dimensions in mm (inch). MB40168/MB40178 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3753 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281 0770 Fax: (65) 281 0220 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. F9703 FUJITSU LIMITED 24 Printed in Japan