MITSUBISHI MH8S64DALD-7

Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
DESCRIPTION
The MH8S64DALD is 8388608 - word by 64-bit
Synchronous DRAM module. This consists of eight
industry standard 8Mx8 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable
for easy interchange or addition of modules.
FEATURES
Frequency
85pin
1pin
94pin
10pin
95pin
11pin
124pin
40pin
125pin
41pin
168pin
84pin
CLK Access Time
(Component SDRAM)
-6
133MHz
5.4ns(CL=3)
-7
100MHz
6.0ns(CL=2)
-8
100MHz
6.0ns(CL=3)
Utilizes industry standard 8M x 8 Sy nchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
Max. Clock frequency -6:133MHz,-7,8:100MHz
Fully synchronous operation referenced to clock
rising edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled
by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
Discrete IC and module design conform to
PC100/PC133 specification.
APPLICATION
PC main memory
MIT-DS-0339-0.0
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ELECTRIC
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17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
PIN NO.
PIN NAME
PIN NO.
PIN NAME
PIN NO.
PIN NAME
PIN NO.
PIN NAME
1
VSS
43
VSS
85
VSS
127
VSS
CKE0
2
DQ0
44
NC
86
DQ32
128
3
DQ1
45
/S2
87
DQ33
129
NC
4
DQ2
46
DQMB2
88
DQ34
130
DQMB6
5
DQ3
47
DQMB3
89
DQ35
131
DQMB7
6
VDD
48
NC
90
VDD
132
NC
7
DQ4
49
VDD
91
DQ36
133
VDD
8
DQ5
50
NC
92
DQ37
134
NC
9
DQ6
51
DQ38
135
NC
10
DQ7
52
NC
NC
93
94
DQ39
136
NC
11
DQ8
53
NC
95
DQ40
137
NC
12
VSS
54
VSS
96
VSS
138
VSS
13
DQ9
55
DQ16
97
DQ41
139
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
VDD
101
DQ45
143
VDD
18
VDD
60
DQ20
102
VDD
144
DQ52
19
DQ14
61
NC
103
DQ46
145
NC
20
DQ15
62
104
DQ47
146
NC
21
63
105
NC
147
NC
22
NC
NC
NC
NC
64
VSS
106
NC
148
VSS
23
VSS
65
DQ21
107
VSS
149
DQ53
24
NC
66
DQ22
108
NC
150
DQ54
25
NC
67
DQ23
109
NC
151
DQ55
26
68
VSS
110
VDD
152
VSS
27
VDD
/WE0
69
DQ24
111
/CAS
153
DQ56
28
DQMB0
70
DQ25
112
DQMB4
154
DQ57
29
DQMB1
71
DQ26
113
DQMB5
155
DQ58
30
/S0
72
DQ27
114
NC
156
DQ59
31
NC
73
VDD
115
/RAS
157
VDD
32
VSS
74
DQ28
116
VSS
158
DQ60
33
A0
75
DQ29
117
A1
159
DQ61
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
36
A6
78
VSS
120
A7
162
VSS
37
A8
79
CK2
121
A9
163
CK3
38
A10
80
NC
122
BA0
164
NC
39
BA1
81
WP
123
A11
165
SA0
40
VDD
82
SDA
124
VDD
166
SA1
SCL
VDD
125
126
CK1
167
168
SA2
VDD
41
42
VDD
CK0
83
84
NC
NC = No Connection
MIT-DS-0339-0.0
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17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Block Diagram
/S0
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB4
DQM /CS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQM /CS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
D4
DQMB5
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D1
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
/S2
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
/RAS
/CAS
/WE
BA0,BA1,A<11:0>
Vcc
Vss
MIT-DS-0339-0.0
DQMB6
DQM /CS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
DQM /CS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
D6
DQMB7
DQM /CS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
DQM /CS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
D7
CK0
4SDRAMs+3.3pF cap.
CK2
4SDRAMs+3.3pF cap.
CK1
CK3
SERIAL PD
D0 - D7 CKE0
D0 - D7
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ELECTRIC
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SCL
WP
47K
A0
A1
A2
SDA
SA0 SA1 SA2
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Serial Presence Detect Table I
Byte
SPD enrty data
SPD DATA(hex)
Defines # bytes written into serial memory at module mfgr
128
80
Total # bytes of SPD memory device
256 Bytes
08
Fundamental memory type
SDRAM
04
3
# Row Addresses on this assembly
A0-A11
0C
4
# Column Addresses on this assembly
A0-A8
09
5
# Module Banks on this assembly
1BANK
01
6
Data Width of this assembly...
x64
40
0
1
2
Function described
7
... Data Width continuation
0
00
8
Voltage interface standard of this assembly
-6
LVTTL
7.5ns
01
75
-7,-8
10ns
A0
SDRAM Access from Clock
-6
5.4ns
54
tAC for CL=3
-7,-8
6ns
60
9
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=3
10
11
DIMM Configuration type (Non-parity,Parity,ECC)
Non-PARITY
00
12
Refresh Rate/Type
self refresh(15.625uS)
80
13
SDRAM width,Primary DRAM
x8
08
Error Checking SDRAM data width
N/A
00
1
1/2/4/8/Full page
01
8F
14
15
Minimum Clock Delay,Back to Back Random Column Addresses
16
Burst Lengths Supported
17
# Banks on Each SDRAM device
18
CAS# Latency
4bank
04
-6
3
04
-7,-8
2/3
06
0
01
19
CS# Latency
20
Write Latency
0
01
21
SDRAM Module Attributes
non-buffered,non-registered
22
SDRAM Device Attributes:General
23
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
24
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
25
26
N/A
00
-7
10ns
A0
-8
-6
13ns
N/A
D0
00
-7
6ns
-8
7ns
60
70
N/A
00
-6
N/A
22.5ns
00
17
-7,-8
20ns
14
-6
-7,-8
15ns
20ns
0F
14
SDRAM Cycle time(3rd highest CAS latency)
Precharge to Active Minimum
28
Row Active to Row Active Min.
30
-6
SDRAM Access form Clock(3rd highest CAS latency)
27
29
Precharge All,Auto precharge
00
0E
RAS to CAS Delay Min
Active to Precharge Min
MIT-DS-0339-0.0
-6
22.5ns
17
-7,-8
20ns
14
-6
45ns
2D
-7,-8
50ns
32
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17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Serial Presence Detect Table II
31
Density of each bank on module
32
Command and Address signal input setup time
33
34
35
36-61
Command and Address signal input hold time
Data signal input setup time
Data signal input hold time
64MByte
-6
1.5ns
15
-7,-8
2ns
20
-6
0.8ns
08
-7,-8
1ns
10
-6
1.5ns
15
-7,-8
2ns
20
-6
0.8ns
08
-7,-8
1ns
10
-6
option
JEDEC2
00
02
Superset Information (may be used in future)
62
SPD Revision
-7,-8
63
10
Checksum for bytes 0-62
rev 1.2A
12
Check sum for -6
92
Check sum for -7
05
Check sum for -8
45
64-71
Manufactures Jedec ID code per JEP-108E
MITSUBISHI
1CFFFFFFFFFFFFFF
72
Manufacturing location
Miyoshi,Japan
01
Tajima,Japan
02
73-90
NC,USA
03
Germany
04
MH8S64DALD-6
4D483853363444414C442D36202020202020
MH8S64DALD-7
4D483853363444414C442D37202020202020
MH8S64DALD-8
4D483853363444414C442D38202020202020
Revision Code
PCB revision
rrrr
Manufacturing date
Manufactures Part Number
91-92
year/week code
yyww
95-98
93-94
Assembly Serial Number
serial number
ssssssss
99-125
Manufacture Specific Data
option
00
126
Intetl specification frequency
100MHz
64
127
Intel specification CAS# Latency support
-7
CL=2/3,AP,CK0,2
AF
-6,-8
CL=3,AP,CK0,2
AD
open
00
128+
Unused storage locations
MIT-DS-0339-0.0
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17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
PIN FUNCTION
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
CKE0
Input
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
/S
(/S0,2)
Input
Chip Select: When /S is high,any command means
No Operation.
/RAS,/CAS,/WE
Input
Combination of /RAS,/CAS,/WE defines basic commands.
Input
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-8.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
Input
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
CK
(CK0 ~ CK3)
A0-11
BA0,1
DQ0-63
DQMB0-7
Vdd,Vss
Input/Output Data In and Data out are referenced to the rising edge of
CK
Input
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
Power Supply Power Supply for the memory mounted module.
SCL
Input
Serial clock for serial PD
SDA
Output
Serial data for serial PD
SA0-3
Input
MIT-DS-0339-0.0
Address input for serial PD
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
BASIC FUNCTIONS
The MH8S64DALD provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge.
In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
/WE
Command
CKE
Ref resh Option @ref resh command
A10
Precharge Option @precharge or read/write command
def ine basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
COMMAND TRUTH TABLE
CKE CKE
n-1
n
/RAS /CAS
A11
COMMAND
MNEMONIC
Deselect
No Operation
DESEL
NOP
H
H
X
X
H
L
X
H
X
H
X
H
X
X
X
X
X
X
X
X
ACT
H
X
L
L
H
H
V
V
V
V
Single Bank Precharge
Precharge All Bank
PRE
PREA
H
H
X
X
L
L
L
L
H
H
L
L
V
X
X
X
L
H
X
X
Column Address Entry
& Write
WRIT E
H
X
L
H
L
L
V
V
L
V
Column Address Entry
& Write with AutoPrecharge
WRITEA
H
X
L
H
L
L
V
V
H
V
Column Address Entry
& Read
READ
H
X
L
H
L
H
V
V
L
V
Column Address Entry
& Read with Auto
Precharge
READA
H
X
L
H
L
H
V
V
H
V
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
REFA
REFS
REFSX
Burst Terminate
Mode Register Set
TERM
MRS
H
H
L
L
H
H
H
L
H
H
X
X
L
L
H
L
L
L
L
L
X
H
H
L
L
L
X
H
H
L
H
H
X
H
L
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
V*1
Row Adress Entry &
Bank Activate
/S
/WE BA0,1
A10 A0-9
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
MIT-DS-0339-0.0
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17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
FUNCTION TRUTH TABLE
/S
IDLE
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
L
L
H
L
L
L
L
H
BA,A10
X
PRE/PREA
REFA
L
L
L
L
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TBST
NOP
L
H
L
H
BA,CA,A10
L
H
L
L
BA,CA,A10
L
L
H
H
BA,RA
ACT
Bank Active/ILLEGAL*2
L
L
H
L
BA,A10
PRE/PREA
Precharge/Precharge All
L
L
L
H
X
L
L
L
L
H
X
X
X
X
DESEL
NOP(Continue Burst to END)
L
H
H
H
X
NOP
NOP(Continue Burst to END)
L
H
H
L
BA
TBST
Terminate Burst
ROW ACTIVE
READ
/RAS /CAS
/WE
Address
Command
Current State
Op-Code,
Mode-Add
Op-Code,
Mode-Add
Action
READ/WRIT E ILLEGAL*2
MRS
READ/READA
Bank Active,Latch RA
NOP*4
Auto-Refresh*5
Mode Register Set*5
Begin Read,Latch CA,
Determine Auto-Precharge
WRITE/
Begin Write,Latch CA,
WRITEA
Determine Auto-Precharge
REFA
ILLEGAL
MRS
ILLEGAL
Terminate Burst,Latch CA,
L
H
L
H
BA,CA,A10
READ/READA Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
L
H
L
L
BA,CA,A10 WRITE/WRITEA Begin Write,Determine AutoPrecharge*3
MIT-DS-0339-0.0
L
L
H
H
BA,RA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
L
L
L
L
Op-Code,
Mode-Add
Bank Active/ILLEGAL*2
Terminate Burst,Precharge
REFA
ILLEGAL
MRS
ILLEGAL
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17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
FUNCTION TRUTH TABLE(continued)
Action
X
DESEL
NOP(Continue Burst to END)
H
X
NOP
NOP(Continue Burst to END)
L
BA
TBST
Terminate Burst
/S
WRIT E
H
X
X
X
L
H
H
L
H
H
L
/RAS /CAS
Command
Current State
H
L
/WE
H
Address
BA,CA,A10
Terminate Burst,Latch CA,
READ/READA Begin Read,Determine AutoPrecharge*3
L
H
L
L
BA,CA,A10
WRITE/
WRITEA
Terminate Burst,Latch CA,
Begin Write,Determine AutoPrecharge*3
L
L
H
H
BA,RA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
READ with
H
X
X
X
X
DESEL
NOP(Continue Burst to END)
AUT O
L
H
H
H
X
NOP
NOP(Continue Burst to END)
PRECHARGE
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
H
BA,CA,A10
L
H
L
L
BA,CA,A10
L
L
H
H
BA,RA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
L
L
L
L
WRITE with
H
X
X
X
X
DESEL
NOP(Continue Burst to END)
AUT O
L
H
H
H
X
NOP
NOP(Continue Burst to END)
PRECHARGE
L
H
H
L
TBST
ILLEGAL
L
H
L
H
BA
BA,CA,A10
L
H
L
L
BA,CA,A10
L
L
H
H
BA,RA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
MIT-DS-0339-0.0
Bank Active/ILLEGAL*2
Terminate Burst,Precharge
READ/READA ILLEGAL
WRITE/
WRITEA
Op-Code,
Mode-Add
ILLEGAL
Bank Active/ILLEGAL*2
ILLEGAL*2
REFA
ILLEGAL
MRS
ILLEGAL
READ/READA ILLEGAL
WRITE/
WRITEA
MITSUBISHI
ELECTRIC
( 10 / 55 )
ILLEGAL
Bank Active/ILLEGAL*2
ILLEGAL*2
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
FUNCTION TRUTH TABLE(continued)
/RAS /CAS
/WE
Address
Command
Current State
/S
Action
PRE -
H
X
X
X
X
DESEL
NOP(Idle after tRP)
CHARGING
L
H
H
H
X
NOP
NOP(Idle after tRP)
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
L
L
H
L
BA,A10
PRE/PREA
L
L
L
H
X
L
L
L
L
READ/WRIT E ILLEGAL*2
Op-Code,
ILLEGAL*2
NOP*4(Idle after tRP)
REFA
ILLEGAL
MRS
ILLEGAL
Mode-Add
ROW
H
X
X
X
X
DESEL
NOP(Row Active after tRCD
ACTIVATING
L
H
H
H
X
NOP
NOP(Row Active after tRCD
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL*2
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL*2
L
L
L
H
X
L
L
L
L
WRITE RE-
H
X
X
X
X
DESEL
NOP
COVERING
L
H
H
H
X
NOP
NOP
L
H
H
L
BA
TBST
ILLEGAL*2
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL*2
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL*2
L
L
L
H
X
L
L
L
L
MIT-DS-0339-0.0
READ/WRIT E ILLEGAL*2
Op-Code,
Mode-Add
REFA
ILLEGAL
MRS
ILLEGAL
READ/WRIT E ILLEGAL*2
Op-Code,
Mode-Add
MITSUBISHI
ELECTRIC
( 11 / 55 )
REFA
ILLEGAL
MRS
ILLEGAL
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
FUNCTION TRUTH TABLE(continued)
Current State
/S
/RAS /CAS
/WE
Address
Command
Action
RE-
H
X
X
X
X
DESEL
NOP(Idle after tRC)
FRESHING
L
H
H
H
X
NOP
NOP(Idle after tRC)
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
MODE
H
X
X
X
X
DESEL
NOP(Idle after tRSC)
REGISTER
L
H
H
H
X
NOP
NOP(Idle after tRSC)
SETTING
L
H
H
L
BA
TBST
ILLEGAL
L
H
L
X
BA,CA,A10
L
L
H
H
BA,RA
ACT
ILLEGAL
L
L
H
L
BA,A10
PRE/PREA
ILLEGAL
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
MRS
ILLEGAL
READ/WRIT E ILLEGAL
Op-Code,
Mode-Add
READ/WRIT E ILLEGAL
Op-Code,
Mode-Add
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
MIT-DS-0339-0.0
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
FUNCTION TRUTH TABLE FOR CKE
Current State
CKE
n-1
CKE
n
/S
SELF -
H
X
X
X
REFRESH*1
L
H
H
L
H
L
/RAS /CAS
Action
/WE
Add
X
X
X
INVALID
X
X
X
X
Exit Self-Refresh(Idle after tRC)
L
H
H
H
X
Exit Self-Refresh(Idle after tRC)
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP(Maintain Self-Refresh)
POWER
H
X
X
X
X
X
X
INVALID
DOWN
L
H
X
X
X
X
X
Exit Power Down to Idle
L
L
X
X
X
X
X
NOP(Maintain Self-Refresh)
ALL BANKS
H
H
X
X
X
X
X
Refer to Function Truth Table
IDLE*2
H
L
L
L
L
H
X
Enter Self-Refresh
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Refer to Current State = Power Down
ANY STATE
H
H
X
X
X
X
X
Refer to Function Truth Table
other than
H
L
X
X
X
X
X
Begin CK0 Suspend at Next Cycle*3
listed above
L
H
X
X
X
X
X
Exit CK0 Suspend at Next Cycle*3
L
L
X
X
X
X
X
Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A m inimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All banks idle State.
3. Must be legal command.
MIT-DS-0339-0.0
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
REFS
REFSX
MRS
MODE
REGISTER
SET
REFA
IDLE
AUTO
REFRESH
CKEL
CKEH
CLK
SUSPEND
ACT
POWER
DOWN
CKEL
CKEH
TBST(for Full Page)
TBST(for Full Page)
ROW
ACTIVE
READ
WRITE
WRITE
SUSPEND
READA
WRITEA
CKEL
READ
WRITE
WRITE
CKEL
READ
CKEH
CKEH
WRITEA
READA
WRITEA
READA
CKEL
WRITEA
SUSPEND
POWER
APPLIED
READ
SUSPEND
CKEL
PRE
WRITEA
CKEH
POWER
ON
PRE
PRE
READA
PRE
CKEH
READA
SUSPEND
PRE
CHARGE
Automatic Sequence
Command Sequence
MIT-DS-0339-0.0
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent
a SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP
condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which
may be issue when both banks are in idle state. After tRSC from a MRS command, the
SDRAM is ready for new command.
CK
/S
BA0 BA1 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1 A0
/RAS
/CAS
0
0
0
0
WM
0
0
LTMODE
BT
BL
/WE
BA0,1 A11-0
CL
LATENCY
MODE
/CAS LATENCY
000
001
010
R
R
2
0
1
1
1
1
3
R
R
R
R
WRIT E
MODE
MIT-DS-0339-0.0
1
0
0
1
1
0
1
1
0
1
0
1
BURST
SINGLE BIT
BURST
LENGTH
BURST
TYPE
V
BL
BT= 0
BT= 1
0
0
1
1
0
0
1
0
1
0
1
2
4
8
R
1
2
4
8
R
101
110
111
R
R
FP
R
R
R
0
0
0
0
1
0
1
SEQUENTIAL
INTERLEAVED
R:Reserved for Future Use
FP: Full Page
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
CK
Command
Read
Write
Y
Y
Address
Q0
DQ
CL= 3
BL= 4
/CAS Latency
Q1
Q2
Q3
D0
Burst Length
D1
D2
D3
Burst Length
Burst Type
Initial Address BL
Column Addressing
A2
A1
A0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
Sequential
Interleaved
8
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
-
0
0
0
1
2
3
0
1
2
3
-
0
1
1
2
3
0
1
0
3
2
4
-
1
0
2
3
0
1
2
3
0
1
-
1
1
3
0
1
2
3
2
1
0
-
-
0
0
1
0
1
1
0
1
0
2
-
-
1
MIT-DS-0339-0.0
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
OPERATION DESCRIPTION
BANK ACTIVATE
One of four banks is activated by an ACT command.
An bank is selected by BA0-1. A row is selected by A0-11.
Multiple banks can be active state concurrently by issuing multiple ACT commands.
Minimum activation interval between one bank and another bank is tRRD.
PRECHARGE
An open bank is deactivated by a PRE command.
A bank to be deactivated is designated by BA0-1.
When multiple banks are active, a precharge all command (PREA, PRE + A10=H)
deactivates all of open banks at the same time. BA0-1 are "Don't Care" in this case.
Minimum delay time of an ACT command after a PRE command to the same bank is tRP.
Bank Activation and Precharge All (BL=4, CL=2)
CK
Command ACT
ACT
A0-9,11
READ
ACT
tRP
Xa
Xb
Yb
A10
Xa
Xb
0
BA0,1
00
01
01
DQ
PRE
tRCD
tRRD
Xa
Xa
1
00
Qa0
Qa1
Qa2
Qa3
Precharge all
READ
A READ command can be issued to any active bank. The start address is specified by A0-8
(x8) . 1st output data is available after the /CAS Latency from the READ. The consecutive data
length is defined by the Burst Length. The address sequence of the burst data is defined by
the Burst Type. Minimum delay time of a READ command after an ACT command to the
same bank is tRCD.
When A10 is high at a READ command, auto-precharge (READA) is performed. Any
command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal
precharge is complete. The internal precharge starts at the BL after READA. The next ACT
command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL >
tRASmin must be met.
MIT-DS-0339-0.0
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Multi Bank Interleaving READ (BL=4, CL=2)
CK
Command ACT
READ
ACT
tRCD
READ PRE
tRCD
ACT
tRP
A0-9, 11
Xa
Ya
Xb
Yb
A10
Xa
0
Xb
0
0
Xa
00
01
01
00
00
Qa2
Qa3
BA0,1
00
DQ
Qa0
Qa1
Xa
Qb0
Qb1
Qb2
Qb3
READ with Auto-Precharge (BL=4, CL=2)
CK
Command ACT
READ
tRCD
A0-9, 11
A10
BA0,1
ACT
tRP
BL
Xa
Ya
Xa
Xa
1
Xa
00
00
00
DQ
Qa0
Qa1
Qa2
Qa3
Internal precharge starts
Auto-Precharge Timing (READ BL=4)
CK
Command ACT
READ
tRCD
CL=3
DQ
CL=2
DQ
ACT
BL
Qa0
Qa0
Qa1
Qa2
Qa1
Qa2
Qa3
Qa3
Internal precharge starts
MIT-DS-0339-0.0
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
WRITE
A WRITE command can be issued to any active bank. The start address is specified by A0-8
(x8). 1st input data is set at the same cycle as the WRITE. The consecutive data length to be
written is defined by the Burst Length. The address sequence of burst data is defined by the
Burst Type. Minimum delay time of a WRITE command after an ACT command to the same
bank is tRCD. From the last input data to the PRE command, the write recovery time (tWR) is
required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is performed.
Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal
precharge is complete. The internal precharge starts at tWR after the last input data cycle.
The next ACT command can be issued after (BL + tWR -1 + tRP) from the previous WRITEA.
In any case, tRCD + BL + tWR -1 > tRASmin must be met.
WRITE (BL=4)
CK
Command ACT
Write
PRE
tRCD
BL
Xa
Ya
A10
Xa
0
BA0,1
00
00
A0-9, 11
ACT
tRP
Xa
0
Xa
00
tWR
DQ
Da0
Da1
Da2
Da3
WRITE with Auto-Precharge (BL=4)
CK
Command ACT
Write
ACT
tRCD
A0-9, 11
A10
BA0,1
tRP
BL
Xa
Ya
Xa
Xa
1
Xa
00
00
00
tWR
DQ
Da0
Da1
Da2
Da3
Internal precharge begins
MIT-DS-0339-0.0
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read oparation can be interrupted by new read of the same or the other bank. Random
column access is allowed READ to READ interval is minimum 1 CK
Read Interrupted by Read (BL=4, CL=2)
CK
Command
READ
A0-9,11
READ READ
Ya
Yb
Yc
A10
0
0
0
BA0,1
00
00
10
DQ
Qa0
Qa1
Qa2 Qb0
Qc0
Qc1
Qc2
Qc3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any active bank. Random column access
is allowed. In this case, the DQ should be controlled adequately by using the DQMB0-7 to
prevent the bus contention. The output is disabled automatically 1 cycle after WRITE
assertion.
Read Interrupted by Write (BL=4, CL=2)
CK
Command ACT
READ
Write
A0-9,11
Xa
Ya
Ya
A10
Xa
0
0
00
00
BA0,1
00
DQMB0-7
DQ
Qa0
Da0
Da1
Output disable by DQM
MIT-DS-0339-0.0
Da2
Da3
by WRITE
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
[ Read Interrupted by Precharge ]
A burst read operation can be interrupted by precharge of the same bank . Read to PRE
interval is minimum 1 CK. A PRE command output disable latency is equivalent to the
/CAS Latency.
Read Interrupted by Precharge (BL=4)
CK
Command
READ
PRE
DQ
Q0
Q1
Q0
Q1
Q2
CL=3
Command
READ
PRE
DQ
Command
READ PRE
DQ
Command
Q0
PRE
READ
DQ
Q0
Q1
Q2
CL=2
Command
READ
DQ
Command
DQ
MIT-DS-0339-0.0
PRE
Q0
Q1
READ PRE
Q0
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
[ Read Interrupted by Burst Terminate ]
Similarly to the precharge, burst terminate command can interrupt burst read operation
and disable the data output. The terminated bank remains active,READ to TBST interval is
minimum of 1 CK. A TBSTcommand to output disable latency is equivalent to the /CAS
Latency.
Read Interrupted by Terminate (BL=4)
CK
Command
READ
TBST
DQ
Command
READ
Q0
Q1
Q0
Q1
Q2
TBST
CL=3
DQ
Command
READ TBST
DQ
Command
Q0
TBST
READ
DQ
Command
Q0
Q1
Q2
TBST
READ
CL=2
DQ
Command
DQ
MIT-DS-0339-0.0
Q0
Q1
READ TBST
Q0
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any active bank. Random
column access is allowed. WRITE to WRITE interval is minimum 1 CK.
Write Interrupted by Write (BL=4)
CK
Command
Write
A0-9, 11
Ya
Write Write
Yb
Yc
A10
0
0
0
BA0,1
00
00
10
DQ
Da0
Db0
Dc0
Da1
Da2
Dc1
Dc2
Dc3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of any active bank. Random column
access is allowed. WRITE to READ interval is minimum 1 CK. The input data on DQ
at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=2)
CK
Command ACT
Write
READ
A0-9,11
Xa
Ya
Yb
A10
Xa
0
0
BA0,1
00
00
00
DQ
Da0
Da1
Qb0
Qb1
Qb2
Qb3
don't care
MIT-DS-0339-0.0
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17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank . Write
recovery time(tWR) is required from the last data to PRE command. During write
recovery, data inputs must be masked by DQM.
Write Interrupted by Precharge (BL=4)
CK
Command
ACT
Write
PRE
ACT
tRP
A0-9,11
Xa
Ya
Xa
A10
0
0
0
0
BA0,1
00
00
00
00
DQMB0-7
tWR
DQ
Da0
Da1
[ Write Interrupted by Burst Terminate ]
Burst terminate command can terminate burst write operation. In this case, the
write recovery time is not required and the bank remains active.The WRITE to TBST
minimum interval is 1CK.
Write Interrupted by Burst Terminate (BL=4)
CK
Command
ACT
Write
A0-9,11
Xa
Ya
Yb
A10
0
0
0
BA0,1
00
00
00
DQ
MIT-DS-0339-0.0
Da0
TBST
Da1
Write
Db0
Db1
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ELECTRIC
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Db2
Db3
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
[ Write with Auto-Precharge interrupted by Write or Read to anotehr Bank ]
Burst write with auto-precharge can be interrupted by write or read toanother bank .
Next ACT command can be issued after (BL+tWR-1+tRP) from the WRITEA. Autoprecharge interrrupted by a command to the same bank is inhibited.
WRITEA Interrupted by WRITE to another bank (BL=4)
CK
Command
Write
A0-9,11
Write
BL
Ya
ACT
tRP
Ya
Xa
tWR
A10
1
0
Xa
BA0,1
00
10
00
DQ
Da0
Da1
Db0
Db1
Db2
Db3
activate
auto-precharge interrupted
WRITEA interrupted by READ to another bank (CL=2,BL=4)
CK
Command
Write
Read
ACT
BL
Ya
A0-9,11
tRP
Yb
Xa
tWR
A10
1
0
Xa
BA0,1
00
10
00
DQ
Da0
Da1
auto-precharge interrupted
MIT-DS-0339-0.0
Db0
Db1
Db2
Db3
activate
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17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
[ Read with Auto-Precharge interrupted by Read to anotehr Bank ]
Burst read with auto-precharge can be interrupted by read to another bank . Next
ACT command can be issued after (BL+tRP) from the READA. Auto-precharge
interrrupted by a command to the same bank is inhibited.
READA Interrupted by READ to another bank (CL=2,BL=4)
CK
Command
Read
A0-9,11
Ya
Read
BL
ACT
tRP
Ya
Xa
tWR
A10
1
0
Xa
BA0,1
00
10
00
DQ
Qa0
Qa1
auto-precharge interrupted
Qb0
Qb1
Qb2
Qb3
activate
Full Page Burst
Full page burst length is available for only the sequential burst type. Full page burst
read or write is repeated untill aPrecharge or a Burst Terminate command is
issued. In case of the full page burst , a read or write with auto-precharge command
is illegal.
Single Write
When single write mode is set, burst length for write is always one, independently
of Burst Length defined by (A2-0).
MIT-DS-0339-0.0
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,
/WE=/CKE=H) command. The refresh address is generated internally. 4096 REFA
cycle within 64ms refresh 64Mbit memory cells. The auto-refresh is performed on
4banks concurrently. Before performing an auto-refresh, all banks must be in the
idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any command
must not be issued before tRFC from the REFA command.
Auto-Refresh
CK
/S
NOP or DESLECT
/RAS
/CAS
/WE
CKE
minimum tRFC
A0-11
BA0,1
Auto Refresh on All Banks
MIT-DS-0339-0.0
Auto Refresh on All Banks
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,
/WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is
kept low.During the self-refresh mode, CKE is asynchronous and the only enabled
input , all other inputs including CK are disabled and ignored, so that power
consumption due to synchronous inputs is saved. To exit the self-refresh, supplying
stable CK inputs, asserting DESEL or NOP command and then asserting CKE=H.
After tRFC from the 1st CK edge follwing CKE=H, all banks are in the idle state and
a new command can be issued after, but DESEL or NOP commands must be
asserted till then.
Self-Refresh
CK
Stable CK
/S
NOP
/RAS
/CAS
/WE
CKE
new command
A0-11
X
BA0,1
00
Self Refresh Entry
MIT-DS-0339-0.0
Self Refresh Exit
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ELECTRIC
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minimum tRFC
for recovery
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
CLK SUSPEND and POWER DOWN
CKE controls the internal CLK at the following cycle. Figure below shows how CKE
works. By negating CKE, the next internal CLK is suspended. The purpose of CLK
suspend is power down, output suspend or input suspend. CKE is a synchronous
input except during the self-refresh mode. CLK suspend can be performed either
when the banks are active or idle. A command at the suspended cycle is ignored.
CK
(ext.CLK)
tIH
tIS
tIH
tIS
CKE
int.CLK
Power Down by CKE
CK
Standby Power Down
CKE
Command
PRE NOP NOP
NOP
Activ e Power Down
CKE
Command
ACT NOP NOP
NOP
DQ Suspend by CKE
CK
CKE
Command
DQ
MIT-DS-0339-0.0
Write
D0
READ
D1
D2
D3
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Q0
Q1
Q2
Q3
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
DQM CONTROL
DQMB0-7 is a dual function signal defined as the data mask for writes and the
output disable for reads. During writes, DQMB0-7 masks input data word by word.
DQMB0-7 to Data In latency is 0.
During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z
latency is 2.
DQM Function
CK
Command
READ
Write
DQMB0-7
DQ
D0
D2
D3
Q0
masked by DQMB=H
MIT-DS-0339-0.0
Q1
Q3
disabled by DQMB=H
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
ABSOLUTE M AXIMUM RATINGS
Symbol
Parameter
Condition
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 ~ 4.6
V
VI
Input Voltage
with respect to Vss
-0.5 ~ Vdd+0.5
V
VO
Output Voltage
with respect to Vss
-0.5 ~ Vdd+0.5
V
IO
Output Current
50
mA
Pd
Power Dissipation
8
W
Topr
Operating Temperature
0 ~ 70
°C
Tstg
Storage Temperature
-40 ~ 100
°C
Ta=25°C
RECOM M ENDED OPERATING CONDITION
(Ta=0 ~ 70°C, unless otherwise noted)
Lim its
Parameter
Symbol
Min.
Typ.
Max.
Unit
Vdd
Supply Voltage
3.0
3.3
3.6
V
Vss
Supply Voltage
0
0
0
V
VIH
High-Level Input Voltage all inputs
2.0
Vdd+0.3
V
VIL
Low-Level Input Voltage all inputs
-0.3
0.8
V
Note)
1:VIH(max)=5.5V f or pulse width less than 10ns.
2.VIL(min)=-1.0 f or pulse width less than 10ns.
CAPACITANCE
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol
Parameter
Test Condition
CI(C)
Input Capacitance, address pin (-6)
@1MHz
1.4V bias
Input Capacitance, /RAS,/CAS,/WE
200mV swing
CI(K)
Input Capacitance, CK pin
CI/O
Input Capacitance, I/O pin
CI(A)
MIT-DS-0339-0.0
(-7,-8)
VI = Vss
f=1MHz
Vi=25mVrms
MITSUBISHI
ELECTRIC
( 31 / 55 )
Lim its(max.)
Unit
-6
-7,-8
45.5
60
pF
45.5
60
pF
32.3
40
pF
16.5
22
pF
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Parameter
Symbol
operating current
one bank activ e (discrete)
Icc1
Test Condition
tRC=min.tCLK=min, BL=1,CL=3
precharge stanby
Icc2P CKE=L,tCLK=15ns, /CS>Vcc-0.2V
current
in power-down mode
Icc2PS CKE=CLK=L, /CS>Vcc-0.2V
precharge stanby current Icc2N CKE=H,tCLK=15ns,VIH>Vcc-0.2V,VIL<0.2V
in non power-down mode Icc2NS
CKE=H,CLK=L,VIH>Vcc-0.2V,VIL<0.2V(f ixed)
active stanby current
in non power-down mode
Icc3N
CKE=H,tCLK=15ns
burst current
auto-refresh current
Icc3NS CKE=H,CLK=L
tCLK=min, BL=4, CL=3,all banks activ e(discerte)
Icc4
tRC=min, tCLK=min
Icc5
self-refresh current
Icc6
one bank activ e (discrete)
Limits
(max)
CKE <0.2V
Unit
-6
-7, -8
600
560
mA
16
16
mA
8
160
120
8
160
120
mA
mA
mA
240
240
mA
200
200
mA
720
1040
560
880
mA
8
8
mA
mA
Note)
1:Icc(max) is specif ied at the output open condition.
2.Input signals are changed one time during 30ns.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol
VOH(DC)
VOL(DC)
IOZ
VOH(AC)
Ii
VOL(AC)
Limits
Min. Max. Unit
High-Level Output Voltage(DC) IOH=-2mA
2.4
V
Low-Level Output Voltage(DC) IOL=2mA
0.4
V
Q
floating
VO=0
~
Vdd
-5
5
uA
Off-stare
Output
Current
High-Level Output Voltage(AC) CL=50pF, IOH=2
V
-40
Input Current
2mA
40
VIH=0 ~ Vdd+0.3V
Low-Level
Output Voltage(AC) CL=50pF,
IOL=2mA
0.8 uA
V
MIT-DS-0339-0.0
Parameter
Test Condition
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ELECTRIC
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17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
AC TIM ING REQUIREMENTS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
Input Timing Measurement Level: 1.4V
-6
Symbol Parameter
Min.
tCLK
tCH
tCL
tT
tIS
tIH
tRC
tRFC
tRCD
tRAS
tRP
tWR
tRRD
tRSC
tSRX
tPDE
tREF
Lim its
-7
CL=2
Max.
Min.
-8
Max.
Min.
Unit
Max.
10
10
13
ns
7.5
CL=3
CK High pulse width
2.5
CK Low pilse width
2.5
Transition time of CK
1
Input Setup time(all inputs)
1.5
Input Hold time(all inputs)
0.8
Row cycle tim e
67.5
Refresh cycle time
75
Row to Column Delay
20
Row Active time
45
Row Precharge time
20
Write Recovery time
15
15
Act to Act Deley time
Mode Register Set Cycle tim e 10
Self Refresh Exit time
7.5
Power Down Exit time
7.5
Refresh Interval time
10
3
3
1
2
1
70
80
20
50
20
20
20
10
10
10
10
3
3
1
2
1
70
80
20
50
20
20
20
10
10
10
ns
ns
ns
10 ns
ns
ns
ns
ns
ns
100K ns
ns
ns
ns
ns
ns
ns
64 ms
CK cycle tim e
10
100K
10
100K
64
64
Note:1 The timing requirements are assumed tT=1ns.If tT is longer than 1ns,(tT-1)ns
should be added to the parameter.
CK
1.4V
Any AC timing is
referenced to the input
Signal
1.4V
signal crossing
through 1.4V.
MIT-DS-0339-0.0
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
SWITCHING CHARACTERISTICS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise note3)
Lim its
-6
-7
-8
Max.
Max.
Min.
Max.
Min.
Min.
Symbol Parameter
tAC
tOH
tOLZ
tOHZ
Access time from CK
Output Hold tim e
from CK
Unit
CL=2
6
6
7
ns
CL=3
5.4
6
6
ns
CL=2
3
3
3
ns
CL=3
2.7
3
3
ns
0
0
0
ns
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
2.7
5.4
3
6
3
6
ns
Note)
1 If clock rising time is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
Output Load Condition
For -7,-8
V TT =1.4V
CK
50½
1.4V
V REF =1.4V
V OUT
DQ
1.4V
50pF
Output Timing
Measurement
Reference Point
For -6
V OUT
50pF
1.4V
CK
tOLZ
DQ
1.4V
tAC
MIT-DS-0339-0.0
tOH
tOHZ
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Burst Write (single bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
tWR
CKE
DQM
A0-8
X
A10
X
X
A9,11
X
X
BA0,1
0
0
D0
DQ
ACT#0
X
Y
0
D0
WRITE#0
D0
0
D0
Y
0
D0
PRE#0
ACT#0
D0
D0
D0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0339-0.0
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17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Burst Write (multi bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
tWR
tWR
CKE
DQM
A0-8
X
X
A10
X
A9,11
BA0,1
X
X
X
X
X
X
X
X
X
0
1
0
D0
DQ
ACT#0
Y
Y
D0
WRITE#0
ACT#1
D0
D0
1
0
D1
D1
0
D1
PRE#0
WRITE#1
D1
1
2
Y
0
D0
ACT#0
D0
D0
D0
ACT#2 WRITE#0
PRE#1
Italic parameter indicates minimum case
MIT-DS-0339-0.0
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17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Burst Read (single bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency =2
A0-8
X
A10
X
X
A9,11
X
X
BA0,1
0
Y
X
0
0
0
Y
0
CL=3
Q0
DQ
ACT#0
READ#0
Q0
Q0
Q0
PRE#0
Q0
ACT#0
Q0
READ#0
READ to PRE ³BL allows full data out
Italic parameter indicates minimum case
MIT-DS-0339-0.0
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Burst Read (multiple bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency =2
A0-8
X
X
A10
X
A9,11
BA0,1
Y
X
X
X
X
X
X
X
X
X
0
1
Y
0
1
CL=3
ACT#0
READ#0
ACT#1
0
1
2
Q1
Q1
Q1
0
CL=3
Q0
DQ
0
Y
Q0
Q0
Q0
PRE#0
READ#1
Q1
Q0
ACT#0
READ#0
PRE#1 ACT#2
Italic parameter indicates minimum case
MIT-DS-0339-0.0
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Burst Write (multi bank) with Auto-Precharge @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
/RAS
tRCD
tRCD
tRCD
/CAS
BL-1+ tWR + tRP
BL-1+ tWR + tRP
/WE
CKE
DQM
A0-8
X
X
A10
X
X
X
X
A9,11
X
X
X
X
0
1
BA0,1
Y
0
D0
DQ
ACT#0
ACT#1
Y
X
1
D0
D0
D0
WRITE#0 with
AutoPrecharge
D1
D1
D1
Y
X
0
0
1
D1
D0
D0
ACT#0
WRITE#1 with
AutoPrecharge
Y
1
D0
WRITE#0
ACT#1
D0
D1
WRITE#1
Italic parameter indicates minimum case
MIT-DS-0339-0.0
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17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
/CS
tRRD
tRRD
/RAS
tRCD
tRCD
tRCD
/CAS
BL+tRP
BL+tRP
/WE
CKE
DQM
DQM read latency =2
A0-8
X
X
A10
X
X
X
X
A9,11
X
X
X
X
0
1
BA0,1
Y
Y
1
0
CL=3
ACT#0
ACT#1
Y
0
0
CL=3
Q0
DQ
X
READ#0 with
Auto-Precharge
Q0
Q0
X
Y
1
1
CL=3
Q0
Q1
Q1
ACT#0
READ#1 with
Auto-Precharge
Q1
Q1
Q0
Q0
READ#0
ACT#1
Italic parameter indicates minimum case
MIT-DS-0339-0.0
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Page Mode Burst Write (multi bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
X
A10
X
X
A9,11
X
X
BA0,1
0
1
Y
Y
Y
Y
0
0
1
0
D0
DQ
ACT#0
D0
D0
WRITE#0
ACT#1
D0
D0
D0
D0
D0
D1
D1
WRITE#0
D1
D1
D0
D0
D0
WRITE#0
WRITE#1
Italic parameter indicates minimum case
MIT-DS-0339-0.0
MITSUBISHI
ELECTRIC
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17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Page Mode Burst Read (multi bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=2
A0-8
X
X
A10
X
X
A9,11
X
X
0
1
BA0,1
Y
Y
Y
Y
0
0
1
0
CL=3
CL=3
Q0
DQ
ACT#0
READ#0
ACT#1
Q0
Q0
CL=3
Q0
Q0
Q0
Q0
READ#0
Q0
Q1
Q1
Q1
Q1
READ#0
READ#1
Italic parameter indicates minimum case
MIT-DS-0339-0.0
MITSUBISHI
ELECTRIC
( 42 / 55 )
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Write Interrupted by Write / Read @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
tCCD
/CAS
/WE
CKE
DQM
A0-8
X
X
A10
X
X
A9,11
X
X
0
1
BA0,1
Y
Y
Y
Y
Y
0
0
0
1
0
CL=3
D0
DQ
D0
D0
D0
D0
D0
D1
D1
Q0
Q0
Q0
Q0
ACT#0
WRITE#0 WRITE#0 WRITE#0
READ#0
ACT#1
WRITE#1
Burst Write can be interrupted by Write or Read of any active bank.
Italic parameter indicates minimum case
MIT-DS-0339-0.0
MITSUBISHI
ELECTRIC
( 43 / 55 )
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Read Interrupted by Read / Write @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=2
A0-8
X
X
A10
X
X
A9,11
X
X
BA0,1
0
1
DQ
ACT#0
Y
Y
Y
Y
Y
Y
0
0
0
1
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q1
Q1
Q0
D0
D0
READ#0 READ#0 READ#0
READ#0
WRITE#0
ACT#1
READ#1
blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
MIT-DS-0339-0.0
MITSUBISHI
ELECTRIC
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17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Write Interrupted by Precharge @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
X
A10
X
X
X
A9,11
X
X
X
BA0,1
0
1
0
D0
DQ
Y
Y
D0
ACT#0
WRITE#0
ACT#1
D0
D0
X
1
0
D1
D1
1
1
1
D1
PRE#0
WRITE#1
PRE#1
Burst Write is not interrupted
by Precharge of the other bank.
Y
ACT#1
D1
D1
WRITE#1
Burst Write is interrupted by
Precharge of the same bank.
Italic parameter indicates minimum case
MIT-DS-0339-0.0
MITSUBISHI
ELECTRIC
( 45 / 55 )
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Read Interrupted by Precharge @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRRD
tRP
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
DQM read latency=2
A0-8
X
X
A10
X
X
X
A9,11
X
X
X
0
1
BA0,1
Y
Y
0
Q0
DQ
ACT#0
READ#0
ACT#1
X
1
0
1
Q0
Q0
Q0
1
Q1
PRE#0
READ#1
PRE#1
Burst Read is not interrupted
by Precharge of the other bank.
Y
1
Q1
ACT#1
READ#1
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
MIT-DS-0339-0.0
MITSUBISHI
ELECTRIC
( 46 / 55 )
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Mode Register Setting
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRSC
tRC
/RAS
tRCD
/CAS
/WE
CKE
DQM
M
A0-8
X
A10
X
A9,11
X
0
BA0,1
0
Y
0
D0
DQ
Auto-Ref (last of 8 cycles)
Mode
Register
Setting
ACT#0
D0
D0
D0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0339-0.0
MITSUBISHI
ELECTRIC
( 47 / 55 )
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Auto-Refresh @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
tRC
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
Y
0
D0
DQ
D0
D0
Auto-Refresh
ACT#0
Before Auto-Refresh,
all banks must be idle state.
After tRC from Auto-Refresh,
all banks are idle state.
D0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0339-0.0
MITSUBISHI
ELECTRIC
( 48 / 55 )
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Self-Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
tRC
CLK can be stopped
/CS
/RAS
/CAS
/WE
tSRX
CKE
CKE must be low to maintain Self-Refresh
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
DQ
Self-Refresh Entry
Before Self-Refresh Entry,
all banks must be idle state.
Self-Refresh Exit
ACT#0
After tRC from Self-Refresh Exit,
all banks are idle state.
Italic parameter indicates minimum case
MIT-DS-0339-0.0
MITSUBISHI
ELECTRIC
( 49 / 55 )
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
DQM Write Mask @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
Y
Y
Y
0
0
0
masked
D0
DQ
ACT#0
D0
WRITE#0
D0
D0
masked
D0
WRITE#0
D0
D0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0339-0.0
MITSUBISHI
ELECTRIC
( 50 / 55 )
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
DQM Read Mask @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM read latency=2
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
Y
Y
Y
0
0
0
masked
Q0
DQ
ACT#0
READ#0
Q0
Q0
Q0
READ#0
masked
Q0
Q0
Q0
READ#0
Italic parameter indicates minimum case
MIT-DS-0339-0.0
MITSUBISHI
ELECTRIC
( 51 / 55 )
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Power Down
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
/CAS
/WE
Standby Power Down
Active Power Down
CKE
CKE latency=1
DQM
A0-8
X
A10
X
A9,11
X
0
BA0,1
DQ
Precharge All
ACT#0
Italic parameter indicates minimum case
MIT-DS-0339-0.0
MITSUBISHI
ELECTRIC
( 52 / 55 )
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
CLK Suspend @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
CKE latency=1
CKE latency=1
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
Y
Y
0
0
D0
DQ
ACT#0
D0
D0
D0
WRITE#0
READ#0
CLK suspended
Q0
Q0
Q0
Q0
CLK suspended
Italic parameter indicates minimum case
MIT-DS-0339-0.0
MITSUBISHI
ELECTRIC
( 53 / 55 )
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
OUTLINE
MIT-DS-0339-0.0
MITSUBISHI
ELECTRIC
( 54 / 55 )
17.Sep.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912 -BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making
semiconductor products better and more reliable,but there is always the
possibility that trouble may occur with them. Trouble with semiconductors
consideration to safety when making your circuit designs,with appropriate
measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of
non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the
customer's application;they do not convey any license under any
intellectual property rights,or any other rights,belonging to Mitsubishi
Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage,
or infringement of any third-party's rights,originating in the use of any
product data,diagrams,charts or ci rcuit application examples contained in
these materials.
3.All information contained in these materials,including product data,
diagrams and charts,represent information on products at the time of
publication of these materials,and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other
reasons. It is therefore recommended that customers contact Mitsubishi
Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product
listed herein.
4.Mitsubishi Electric Corporation semiconductors are not designed or
manufactured for use in a device or system that is used under
circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor when considering the use of a product contained herein
for special applications,such as apparatus or systems for transportation,
vehicular,medical,aerospace,nuclear,or undersea repeater use.
5.The prior written approval of Mitsubishi Electric Corporation is necessary to
reprint or reproduce in whole or in part these materials.
6.If these products or technologies are subject the Japanese export
control restrictions,they must be exported under a license from the
Japanese government and cannot be imported into a country other than
the approved destination.
Any diversion or reexport contrary to the export control laws and
regulations of Japan and/or the country of destination is prohibited.
7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or
the products contained therein.
MIT-DS-0339-0.0
MITSUBISHI
ELECTRIC
( 55 / 55 )
17.Sep.1999